JPS63154976A - Circuit for testing large-scale integrated circuit apparatus - Google Patents

Abstract

PURPOSE:To enable the non-contact testing of LSI pins, by a method wherein pin scan out circuits are provided for respective LSIs and a voltage waveform of an LSI pin to be tested is sampled to observe a pseudo waveform obtained from a logic output. CONSTITUTION:For example, a voltage generated in a pin 1' is compared with a reference voltage Vref by a comparator 21 and when a pin output is higher, the output is 1 while it is 0 when the pin output is lower. A selection circuit 3 selects a pin I/O1' based on a pin address signal inputted from a pin address terminal ADT and an output of the comparator 21 is outputted to a latch circuit 4. At this point, the selection circuit 3 inverts an comparator output to be sent to the subsequent stage. The latch circuit 4 latches an output of the selection circuit 3 by a clock pulse from a clock pulse generator 5 to be outputted to a pin scan out terminal SOT. This operation is performed varying the sampling point and the Vref sequentially to determine a pseudo waveform and then, a test is performed.

Description

[Detailed Description of the Invention] [(Already required)] The present invention provides a method for testing large-scale integrated circuit devices.
Each SI is equipped with a pin scan-out circuit, and the LS under test
The voltage waveform of the I-bin is sampled and a pseudo waveform obtained by logic output is used to enable testing without contacting the LSI pins.

[Industrial application field]

The present invention relates to a test circuit for large-scale integrated circuit (LSI) devices, and more particularly to a test circuit that allows non-contact observation of voltage waveforms appearing at input/output (I10) pins of each LSI mounted on a printed circuit board. .

[Problems to be solved by conventional techniques and inventions] No. 6
The figure is a schematic configuration diagram of a conventional LSI device testing device. In FIG. 6, the LSI 63 which is the test object
A plurality of LSI terminals (pins) 64 are provided on its outer periphery. In order to test the internal circuit through these pins, a probe card 62 having probes 61 provided on its inner periphery is used. Probe 61 is LSI pin 6
4, and the respective probes and pins come into contact with each other when the probe card 62 is mounted on the LSI 63. LSI after installation
A tester 65 checks whether a predetermined value appears on each pin.

However, with recent high-density packaging of LSIs, the spacing and width of pins are becoming narrower and narrower, resulting in problems such as destruction of LSI pins by probes and poor contact during testing. There are also cases where the pins are not directly visible, such as on the underside of the package. Such a problem can always occur in a system in which the pin and probe are in mechanical contact, and as a drastic countermeasure, a system that does not use a probe and achieves contact is required.

c. Means and operation for solving the problems] The present invention provides a test circuit for an LSI device that solves the above problems. According to the present invention, in an LSI device, each LSI on a printed circuit board The same number of comparators are provided on each pin for all I10 pins, and a reference input terminal RT for supplying the reference voltage to all these comparators is provided separately from the I10 pin. Within the LSI, the logic output is stored in a 7-channel circuit as a temporary memory through a selection circuit that selects one of the comparator outputs for each block, and the latch outputs of each block are OR-connected to I10. The bin is connected to a scan-out terminal SOT separate from the bin, and the reference input terminal RT and scan-out terminal SOT of each LSI are further connected within the LSI device to external terminals of the LSI device. During the test, the LSI device is operated, a periodic voltage waveform is generated in one LSI bin that is focused on for testing the LSI device, and the memory retention timing of the latch circuit is determined by each phase point of the voltage waveform. First, the reference voltage is kept constant and the comparator output, which is the comparison result at the initial phase point of the measurement range, is taken out to the outside of the LSI device via the latch circuit, and then the phase point is changed and the above processing is carried out. Repeat this process by sequentially changing the reference voltage step by step to cover the amplitude of the observed waveform, reconstruct each obtained logic output to obtain a pseudo-waveform of the observed waveform, and observe this pseudo-waveform. By doing this, LSI tests can be performed.

In short, the present invention includes a bin scan out circuit in each LSI as a means for observing the voltage waveform of the 110 pin of the LSI, and the J pin scan out circuit includes a comparator, an I10 pin selection circuit, and a latch. By connecting all the pin scan alert circuits for each LSI and connecting them to the external I10 terminal of the LSI device, the voltage waveform can be output as a logic output from the external terminal of the LSI device without touching each LSI bin. It is made so that it can be obtained.

〔Example〕

FIG. 1 is a detailed external view of an LSI device having a test circuit according to the present invention. In FIG. 1, 1 is an LSI, 2 is a comparator, 3 is a selection circuit, 4 is a latch circuit, and 5 is a clock pulse generator. The LSII has the following
Eight input/output bins from I10■ to ■10■ are provided.

These pins are connected to one input of each of comparators 2. Eight comparators 2 (21 to 2B) are provided for each 1/Ohi:/. A reference voltage is input to the other input of the comparator 2 via the reference input terminal RT, and the outputs of all comparators are supplied to the selection circuit 3.
is input. Further, an address signal for selecting a pin and a select signal for selecting the LSI select input terminal SIT are input to the comparator 2 via the pin address terminal ADT. The output of the selection circuit 3 is input to the latch circuit 4, and the output from the latch circuit is output based on the clock pulse of the clock pulse generator 5. The clock pulse generator 5 has a clock control terminal CL.
This is done by a clock control signal input via KT. A pin scan out circuit psoc is configured by the above-mentioned comparator, selection circuit, latch circuit, and clock pulse generator. Therefore, all LSIs are provided with this pin scan-out circuit psoc.

In such a configuration, the method for observing the voltage generated at the I10 bin of the LSI is performed as follows. For example, the voltage generated at pin T10■ is compared with reference voltage Vref in comparator 21. Pin output is Vref
The output of the comparator is 1'' when the level is higher than 0, and 0 when it is lower.
pin I10 based on the pin address signal input from
■ is selected, and the output of the comparator 21 is the latch circuit 4
is output to. At this time, the selection circuit 3 inverts the comparator output and sends it to the next stage. The latch circuit 4 is activated by the selection circuit 3 by the clock pulse from the clock pulse generator 5.
The output is latched and output to the pin scan out terminal SOT.

FIG. 2 is a partial circuit diagram of the LSI device. Each LSI
and pin scan out circuit psoc to form an LSI unit (LSI unit), which is arranged in multiple units to form an LS
It constitutes an I device. A switching circuit SWC including a decoder circuit DC is provided to select these LSI units. I10 pin and bin scanout circuit p
Terminal SOT for soc.

RT, CLKT, ADT, etc. are connected to the outside as common terminals of each LSI unit.

FIG. 3 is an overall configuration diagram including a test device (tester) connected to the LSI device. Each I10 pin of the LSI and the test circuit (the test circuit is the bin scan out circuit psoc
and a switching circuit SWC) are connected to a tester. Details of the tester T are shown in FIG. 5, which will be described later.

Figure 4 shows the pin address, L
This is a timing chart in a state in which the SI address has been determined, that is, in a state in which the I10 pin has been selected. Here, for ease of explanation, the steps of the reference input voltage are 0.
An example of 2 V and a quarter period phase step is shown. However, in actual use, even finer reference voltage steps are required. In this embodiment, 12 clock pulses are generated to observe one waveform. As is obvious, the finer the step of the reference voltage, the more a pseudo waveform that is closer to the original waveform can be obtained, and the test accuracy improves accordingly.

In FIG. 4, it is assumed that the output waveform of the I10 pin is as shown in (a). That is, it is assumed that this waveform is not actually connected and measured, but is output for the sake of explanation. Therefore, by using the method according to the present invention, a waveform that approximates such a waveform can be obtained without contact while shifting the sampling point and the reference voltage.
The obtained pseudo waveform is regarded as the waveform actually output from the I10 bin. This is (C)
It is obtained by changing the sampling point and the reference voltage Vref in stages as shown in FIG.

That is, the comparator first compares the first high reference voltage Vref 1 and the output voltage V of the I10 pin, and then
If it is higher than Vref, "1" is determined, and if it is lower than Vref, "0" is determined for each phase step. 4! The voltage Vref is Vref 2 , Vref 3
The value is lowered step by step to find "1" and "0" in the same way. As a result of performing this operation while shifting the sampling points, the distribution of "1" and "0" as shown in (d) is obtained, and the waveform shown by the dotted line at the boundary between "1" and "0" is from the I10 pin. It can be obtained as a pseudo waveform W of the output waveform.

FIG. 5 is a detailed block diagram of the tester shown in FIG. 3.

The file 51 stores a test program for testing the LSI. Reference voltage generation section 52
is for generating various reference voltages Vref. The test pattern generating section 53 is for generating a test pattern according to the test program in the file 51, and is supplied to the r10 pin. A clock controller 54 generates clock pulses for sampling. LSI
The pin stress generating section 55 generates an address for the I10 pin. The physical tester signal allocation section 56 is for allocating which 110 pins are to be used.

[Effect of the invention] As explained above, according to the present invention, the LSI test can be
Since the test can be performed without contacting the SI pins, it is possible to avoid all contact failures and pin breakages that occur in the past, and it is also possible to easily test pins that are not visible on the surface of the LSI. Test accuracy is greatly improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an LSI having a test circuit according to the present invention, Fig. 2 is a partial block diagram of an LSI device according to the present invention, Fig. 3 is an overall configuration diagram including a tester, and Fig. 4 is a sampling diagram. Timing chart, Figure 5 is a detailed block diagram of the tester, and Figure 6 is a conventional LSI.
This is a method of testing equipment. (Explanation of symbols) 1...LSI, 2...Comparator, 3
...Select circuit, 4...Latch circuit, 5...
・Clock pulse generator, LSIU...LSI unit, psoc...pin scan out circuit, SWC...
switching circuit. LSIU Block diagram of an LSI having a test circuit according to the invention (1) Partial block diagram of an LSI device according to the invention (2) Overall block diagram including a tester (3) Figure 3 (1-cycle pull/pull timing chart) (4) L
Detailed block diagram of J tester Figure 5 Conventional LSI device testing method

Claims (1)

[Claims] 1. A test circuit for a large-scale integrated circuit device composed of a plurality of large-scale integrated circuits, including a comparator provided for each input/output pin of the large-scale integrated circuit, and a test circuit that receives and selects the output of the comparator. a pin scan out circuit comprising a selection circuit that outputs an output for each selected pin, a latch circuit that latches the output of the selection circuit and outputs it in response to a clock pulse, and a clock generator that generates the clock pulse; a switching circuit that selects one of all the pin scan-out circuits provided for each large-scale integrated circuit and supplies a test pattern; Comparing the voltage with a reference voltage input to the other side and outputting a comparison result to the selection circuit, the selection circuit outputting the comparison result to the latch circuit based on an address signal indicating the input/output pin, The latch circuit outputs a logical value at a timing corresponding to the sampling phase point by the clock pulse, and changes the output matrix of the logical value by sequentially changing the reference voltage and the sampling phase point in a stepwise manner. A test circuit for a large-scale integrated circuit device, wherein a test is performed by obtaining a pseudo waveform from the matrix and observing an output voltage waveform of the input/output pin using this waveform.