JP2002156389A - Sampling digitizer and semiconductor integrated circuit testing device provided with the sampling digitizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sampling digitizer, capable of freely changing a sampling rate of data to be read into a digitizer, without changing the sampling rate in a sampling head. SOLUTION: In this sampling digitizer composed of the sampling head 11, a clock-generating part 12 and the digitizer 13, a thinning circuit 22 limiting the number of passing clock signals is inserted in a supply path of clock signals ranging from the clock generating part to the digitizer. The number of thinning of the thinning circuit is set at a desired value, and a low-speed data signal output from the sampling head is fetched into the digitizer at a desired sampling rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique called "sampling digitizer", which is generally referred to as a "sampling digitizer" in the technical field. More specifically, with respect to a device for performing such operations (hereinafter referred to as a sampling digitizer), specifically, it is taken into a device for observing, measuring, and / or analyzing a signal waveform without changing the sampling rate of a clock signal for sampling a high-speed repetitive signal. The present invention relates to a sampling digitizer that can freely change a data sampling rate, and a semiconductor integrated circuit test device including the sampling digitizer.

[0002]

BACKGROUND OF THE INVENTION As is well known in the art, a sampling digitizer, as shown in FIG. 1, includes a sampling head (typically constituted by a circuit having a diode bridge) 11 and a clock generator. A high-speed repetitive signal (waveform) input to the sampling head 11 including a unit 12 and a device (hereinafter, referred to as a digitizer) 13 for observing, measuring, and / or analyzing a signal waveform.
The HRS is converted into a low-speed repetitive signal (waveform) by an equivalent sampling method described later, and the digitizer 13 observes, measures, analyzes, etc. the waveform of the low-speed repetitive signal, thereby obtaining an input high-speed repetitive signal. It is an apparatus that can perform observation, measurement, analysis, etc. of the HRS waveform.

FIG. 2A shows an equivalent sampling method.
Is input to the sampling head 11, the waveform of the high-speed repetitive signal HRS is sequentially sampled from a specific sample point (for example, point a) at a constant minute time interval Δt. In order to achieve this, it is necessary to generate a clock signal having a period Δt that is even faster than the high-speed repetitive signal HRS. For example, the frequency of the high-speed repetitive signal HRS is 1 GHz.
This is not possible in cases such as high z. For this reason, the waveform of the high-speed repetitive signal HRS is sequentially shifted from the specific sample point (for example, point a) by a certain minute time interval Δt at every certain cycle nT considerably longer than the cycle T, Sample. Specifically, as shown in FIG. 2B, a constant sampling rate (period) of (nT + Δt) is supplied from the clock generator 12.
At T1, a clock signal CLK1 is generated (therefore, the frequency is 1 / (nT + Δt)) and supplied to the sampling head 11. As a result, the high-speed repetitive signal H
The sample timings t1, t2, t3,.
.. Is sequentially delayed by a fixed minute time Δt, so that the waveform data obtained by sequentially sampling the waveform of the high-speed repetitive signal HRS from a specific sampling point (eg, point a) at a fixed minute time interval Δt Substantially the same waveform data can be obtained.

As shown in FIG. 2C, sampling timings t1, t2, t3,.
.. A low-speed data signal SM converted into waveform data a, b, c,...
PD is generated at a sampling rate T1. The waveform data a, b, c,... Are captured by the digitizer 13 by applying the clock signal CLK1 of the same sampling rate T1 from the clock generator 12 to the digitizer 13, and are synthesized at a constant minute time interval Δt. Reproducing, as shown in FIG. 2D, the sampling rate T
A low-speed repetition signal LRS1 having a cycle T3 obtained by multiplying 1 by the number of samples per cycle T of the high-speed repetition signal HRS is obtained. This low-speed repetitive signal LRS1
Is substantially the same as the waveform of the high-speed repetitive signal HRS.

Here, n is a high-speed repetition signal HRS
At a period nT in which a certain minute time Δt is not added.
Is a positive integer divided by the frequency of the clock signal (= 1 / nT). Therefore, 1 / nT represents the frequency of the clock signal used when sampling the waveform of the high-speed repetitive signal HRS at a fixed sampling point (for example, a fixed point at the leading edge of the waveform) every fixed cycle nT. In addition,
The constant minute time interval Δt corresponds to the high-speed repetition signal H
Since it is equivalent to the time interval between two adjacent sample points of the RS waveform, it is called an equivalent sampling time in this technical field. In this specification, Δt is also referred to as an equivalent sampling time.

In FIG. 2, in order to easily understand the operation of the equivalent sampling method, the waveform of the high-speed repetitive signal HRS is enlarged and the equivalent sampling time Δt is lengthened. For this reason, in the figure, n = 3, and the sampling rate T1 of the clock signal CLK1 is 3T + Δt (T1 = 3T + Δt). However, as described below, usually, the frequency of the high-speed repetitive signal HRS is the clock signal having the period nT. So much higher than the frequency,
n is a considerably large value. Explaining using specific numerical values, for example, the frequency of the high-speed repetitive signal HRS is 1 G
Hz (therefore, the period T is 1 ns). When the frequency of the clock signal having the period nT is 1 MHz, one period T (1n
s) is set to 100 (high-speed repetition signal H).
Assuming that 100 data are acquired from one cycle T of RS), the time interval between two adjacent sample points is 1 ns /
100 = 10 ps. That is, the equivalent sampling time Δt is 10 ps. Therefore, the sampling rate T1 = 1 ns × (1 GHz / 1 M
Hz) +10 ps = 1 μs + 10 ps and the clock signal C
When LK1 is generated and supplied to the sampling head 11, the sampling head 11 outputs waveform data a, b, c,... Whose amplitude level changes stepwise according to the sample timings t1, t2, t3,. Is generated at the sampling rate T1 = 1 μs + 10 ps. These waveform data are captured by the digitizer 13, and the captured waveform data is synthesized at a time interval of an equivalent sampling time of 10 ps and reproduced, as shown in FIG. 2D (1 μs + 10p).
s) A low-speed repetitive signal L having a period T3 of × 100
RS1 is obtained.

As described above, the conventional sampling head 11
And the digitizer 13 are supplied with a clock signal CLLK1 having the same sampling rate to generate a high-speed repetition signal HRS.
And sampling of the sampled data into the digitizer 13. By the way, the above-mentioned sampling digitizer is a semiconductor integrated circuit (hereinafter referred to as I
C) is also used in a semiconductor integrated circuit test device (IC test device) for testing the same. For example, a test pattern signal is written to an IC under test at a high speed, a test pattern signal read at a high speed from the IC under test is converted into a low speed signal, and the waveform is observed, measured and / or analyzed, and the IC under test is
For example, a sampling digitizer is used to test how fast a high-speed signal can be reliably responded to.

As is well known, in the art, ICs
The one whose main part is a logic circuit (logic part) is called a logic IC, and the one whose main part is a memory is called a memory IC. An IC in which a logic part and a memory part are mixed on one chip is a system LSI,
It is called a system on chip (SOC) or the like.
FIG. 3 shows a schematic configuration of a general IC test apparatus (hereinafter, referred to as an IC tester) conventionally used. The illustrated IC tester includes an IC tester main body 100 and a test head 2.
And the IC tester body 100
In this example, the controller 101 and the timing generator 1
02, the pattern generator 103, and the waveform formatter 1
04, a driver 105, a comparator 106, a logical comparator 107, a failure analysis memory 108, and a voltage generator 109.

The test head 200 is an IC tester body 10
0, and a predetermined number of I
A C socket (not shown) is mounted. Further, a printed circuit board called a pin card in this technical field is housed inside the test head 200.
The circuit including the driver 105 and the comparator 106 of the IC tester main body 100 is mounted on this pin card. This pin card is the IC to be tested (IC under test) 3
00 is provided for each I / O pin (input / output terminal). In general, the test head 200 is attached to a test section of an IC transport and processing device called a handler in this technical field, and the test head 200 and the IC tester main body 100 are electrically connected by a signal transmission means such as a cable or an optical fiber. Connected.

The IC under test 300 is mounted on an IC socket of the test head 200, and through this IC socket,
A test pattern signal is applied from the IC tester main body 100 to an IC under test (generally called a DUT) 300, and a response signal from the IC under test 300 is supplied to the IC tester main body 100 to perform testing and measurement of the IC under test 300. Will be The controller 101 is configured by a computer system, stores a test program created by a user (programmer) in advance, and controls the entire IC tester according to the test program. The controller 101
Timing generator 102, pattern generator 103, waveform formatter 104, logical comparator 107, failure analysis memory 108, voltage generator 109 through tester bus 111
And the like, and these timing generators 102,
Pattern generator 103, waveform formatter 104, logic comparator 107, failure analysis memory 108, voltage generator 10
9 and the like operate as terminals, and execute a test of the IC under test 300 according to a control command output from the controller 101.

A test of the IC under test 300, for example, a functional test is performed as follows. Prior to the start of the test, the pattern generator 103 previously stores the pattern generation order described in the test program stored in the controller 101.
When a test start command is given from No. 1, test pattern data to be applied to the IC under test 300 is output in accordance with the stored pattern generation order. The pattern generator 103 generally includes an ALPG (Algorithmic Pattern).
n Generator). The ALPG is a pattern generator that generates a test pattern to be applied to a semiconductor device (for example, an IC) by operation using a register having an internal operation function.

Before starting the test, the timing generator 102 previously stores timing data to be output for each test cycle described in the test program stored in the controller 101. A clock pulse is output for each test cycle in accordance with the timing data obtained. This clock pulse is provided to the waveform formatter 104, the logic comparator 107, and the like.
The waveform formatter 104 includes the test pattern data output from the pattern generator 103 and the timing generator 10.
2 defines a rising timing and a falling timing of the logic waveform based on the clock pulse output from the clock signal 2 and has an actual waveform that changes to H logic (logic "1") and L logic (logic "0"). A test pattern signal is generated, and the test pattern signal is applied to the IC under test 300 through the driver 105.

The driver 105 includes a waveform formatter 10
4 outputs the desired amplitude (H logic, that is, the voltage VIH and L logic of logic “1”,
That is, the voltage is specified to the logic “0” voltage VIL) and applied to the IC socket of the test head 200 to drive the IC under test 300. The comparator 106 determines whether the logic value of the response signal output from the IC under test 300 has a normal voltage value. That is, the voltage of the H logic is equal to the prescribed voltage value VOH.
If the above value is indicated and the voltage of L logic is the specified voltage value V
It is determined whether the value indicates OL or less.

When the judgment result is good, the comparator 1
The output signal of the determination result output from the logical comparator 1
07, the logical comparator 107 compares the logical value with expected value pattern data given from the pattern generator 103 to determine whether or not the IC under test 300 has output a normal response signal. The comparison result of the logical comparator 107 is taken into the failure analysis memory 108. If a defect occurs, the defective test pattern address and the IC under test
The output logic data of the 300 defective pins and the expected value pattern data at that time are stored in the failure analysis memory 108,
After the test, it is used for evaluating the LSI.

The voltage generator 109 generates amplitude voltages VIH and VIL to be applied to the driver 105 and comparison voltages VOH and VOL to be applied to the comparator 106 according to the set values sent from the controller 101. As a result, a drive signal having an amplitude value that matches the standard of the IC under test 300 is generated from the driver 105, and the response signal of the IC under test 300 indicates the logical value of the voltage that matches the standard of the IC under test 300 in the comparator 106. It can be determined whether or not it has. The above-described sampling digitizer is mounted on a pin card housed inside the test head 200, for example, an IC under test.
Observe the waveform of the response signal read at high speed from 300,
Measure and / or analyze. First, a test pattern signal is written to the IC under test 300 at a high speed, and the waveform of the test pattern signal read at a high speed from each pin of the IC under test is observed, measured, and / or measured by the sampling digitizer having the above configuration.
Or analyze. By observing, measuring and analyzing this waveform,
It can be correctly determined whether or not the IC under test 300 is defective. By this test, for example, the operation speed of the IC under test can be classified into several categories, and a test is performed to determine how fast the IC under test can reliably respond to a high-speed signal. You can also.

[0016]

As described above, conventionally, a clock signal of the same sampling rate is applied to a sampling head and a digitizer to sample a high-speed repetitive signal and take in the sampled data into the digitizer. Was. In order for the waveform to be reproducible and to be accurately observed, measured and / or analyzed, the sampling rate of the clock signal for sampling the high-speed repetitive signal at the sampling head must be measured within a certain rate range. . For this reason, there is a problem that the sampling rate for taking the sampled data into the digitizer is also limited to within the above-mentioned fixed rate range.

On the other hand, depending on the type of the device to be tested and the test items, the sampled data is taken in at a low sampling rate and it is desired to observe, measure and / or analyze the data at a high resolution with a digitizer. If you want to observe, measure and / or analyze at medium resolution with a digitizer and capture the data at a high resolution, and want to observe, measure and / or analyze at low resolution with a digitizer and capture the sampled data at high resolution, etc. Depending on the application,
Alternatively, a sampling digitizer that can be captured by a digitizer at a sampling rate that meets the needs of the user has been desired.

If such a versatile sampling digitizer is incorporated in an IC test apparatus, the number of IC test items can be further increased, so that most kinds of IC tests can be performed efficiently. . An object of the present invention is to provide a sampling digitizer which can freely change the sampling rate of data taken in the digitizer while the sampling rate in the sampling head remains constant. Another object of the present invention is to provide a sampling digitizer which has a plurality of digitizers and which can capture a low-speed data signal output from a sampling head into these digitizers at a desired sampling rate.

Still another object of the present invention is to provide an IC test apparatus capable of increasing the number of IC test items.

[0020]

In order to achieve the above object, according to a first aspect of the present invention, a clock generating means for generating a clock signal at a predetermined sampling rate, and a high-speed repetitive signal to be inputted are provided. A sampling unit that samples by a clock signal supplied from the clock generation unit and converts it into a low-speed data signal;
A signal waveform observation, measurement or analysis device to which a low-speed data signal output from the sampling unit is supplied, and a clock signal supply path from the clock generation means to the signal waveform observation, measurement or analysis device, There is provided a sampling digitizer comprising a thinning means for selectively thinning a clock signal applied to a signal waveform observation, measurement or analysis device.

The decimation number set in the decimation means is m
Assuming that the sampling rate of the clock signal for sampling the high-speed repetitive signal is T1, the low-speed data signal is read into the signal waveform observation, measurement or analysis device at a sampling rate of (m + 1) × T1. With a plurality of signal waveform observation, measurement or analysis devices,
A multiplexer for selectively supplying a low-speed data signal output from the sampling unit to the plurality of signal waveform observation, measurement or analysis devices is provided, and according to a decimation number m set in the decimation unit, A single signal waveform observation, measurement, or analysis device that supplies the low-speed data signal may be selected from the plurality of signal waveform observation, measurement, or analysis devices by the multiplexer.

The signal waveform observation, measurement or analysis device may be constituted by an oscilloscope. According to a second aspect of the present invention, a test pattern signal is applied to a semiconductor integrated circuit under test, a response signal read from the semiconductor integrated circuit under test is logically compared, and a response signal of the semiconductor integrated circuit under test is determined based on the comparison result. In a semiconductor integrated circuit test apparatus for judging pass / fail, a semiconductor integrated circuit test apparatus including any one of the sampling digitizers described in the first aspect is provided.

In a preferred embodiment, the sampling digitizer is mounted on a pin card housed in a test head of a semiconductor integrated circuit test device. According to the above configuration, the sampling rate of the data taken into the digitizer can be freely changed while the sampling rate of the sampling head remains constant.
It is possible to provide a sampling digitizer that can take sampled data into a digitizer at a sampling rate according to an application or a user's request.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a sampling digitizer according to the present invention will be described in detail with reference to FIGS. In FIG. 4, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted unless necessary. FIG. 4 is a block diagram showing a first embodiment of a sampling digitizer according to the present invention. As in the conventional sampling digitizer shown in FIG.
2 and a digitizer 13. The function and operation of this sampling digitizer have already been described with reference to FIGS. 1 and 2 and will not be described here.

In this embodiment, a thinning circuit 22 for limiting the number of passing clock signals is inserted in a clock signal supply path from the clock generating unit 12 to the digitizer 13 of the sampling digitizer having the above configuration. The clock signal supplied from the clock generator 12 is decimated by the decimation number m set in, and is applied to the digitizer 13. The decimation number m set in the decimation circuit 22 is determined according to the sampling rate of a low-speed data signal to be captured by the digitizer 13. As described above, the sampling head 11
Is supplied with a high-speed repetitive signal as shown in FIG. 2A. When this high-speed repetitive signal is equivalently sampled by the clock signal CLK1 supplied from the clock generator 12, the sampling head 11 outputs, for example, the signal shown in FIG.
A low-speed data signal SMPD shown in FIG. Since the clock signal CLK1 shown in FIG. 5B is supplied to the thinning circuit 22, it is desired that the digitizer 13 capture the data signal SMPD at a rate twice as high as the sampling rate of the low-speed data signal SMPD (sampling rate in the sampling head 11). In this case, the thinning number m of the thinning circuit 22 is set to “1”.

When the decimation number m is 1, the decimation circuit 22 passes the supplied clock signal CLK1 every other clock from the first clock signal as shown in FIG. 5C. Therefore, the decimating circuit 22 outputs one-half of the clock signal CLK1 and the clock signal CLK1.
A clock signal CL having a period 2 × T1 twice as long as the period T1 of 1
Since K2 is output, the low-speed data signal SMPD is taken into the digitizer 13 at a double sampling rate. Next, a description will be given using specific numerical values.
For example, if the frequency of the high-speed repetitive signal HRS input to the sampling head 11 is 1 GHz (therefore, the cycle is 1 ns), and the number of samplings per cycle (1 ns) of the high-speed repetitive signal HRS is 100,
The equivalent sampling time Δt is 10 ps. Therefore,
Assuming that the frequency of a clock signal having a period nT is 1 MHz,
From the clock generator 12, as described above, the sampling rate T1 = 1ns × (1 GHz / 1 MHz) +10
A clock signal CLK1 is generated at ps = 1 μs + 10 ps and supplied to the sampling head 11 and the thinning circuit 22.

For example, the decimation number m = 9 in the decimation circuit 22
When 9 is set, the clock signal CLK1 supplied to the decimating circuit 22 is divided every 99 clock signals when the first clock signal passes (it is blocked from passing). One clock signal CLK2 is output from the thinning circuit 22 and applied to the digitizer 13. Therefore, the digitizer 13 outputs the first, 101st, and second low speed data signals SMPD.
Only the 01st,... Sampling data is captured, and the remaining sampling data is not captured. That is, only the first sampling data is captured every 100 samplings of the high-speed repetition signal HRS, and the remaining 99 sampling data are not captured. Therefore, the digitizer 13 supplies the low-speed data signal S
Data is taken in at a sampling rate (100 × T1) that is 100 times the sampling rate T1 of the MPD.

Further, the thinning number m = 49 is provided to the thinning circuit 22.
Is set, the clock signal CLK1 supplied to the thinning circuit 22 is thinned when the first clock signal passes, so that the subsequent 49 clock signals are thinned, so that one clock signal CLK2 is thinned every 50th clock signal. Output from the circuit 22 is applied to the digitizer 13. Therefore, the digitizer 13 outputs 1 of the high-speed repetition signal HRS.
Only the first and 51st sampling data are taken in every 00 samplings, and the remaining 98 sampling data are not taken. Therefore, digitizer 1
3, data is taken in at a sampling rate (50 × T1) that is 50 times the sampling rate T1 of the low-speed data signal SMPD.

When the thinning number m = 9 is set in the thinning circuit 22, the clock signal CLK1 supplied to the thinning circuit 22 is such that when the first clock signal passes, the subsequent nine clock signals are thinned. Because it is 1
One clock signal CLK 2 for each 0 is output from the thinning circuit 22 and applied to the digitizer 13. Therefore, the digitizer 13 takes in only the first, eleventh, twenty-first,..., And 91st tenth sampled data every 100 samplings of the high-speed repetitive signal HRS. Is not captured. Therefore, the digitizer 13 receives data at a sampling rate (10 × T1) that is ten times the sampling rate T1 of the low-speed data signal SMPD.

On the other hand, if the decimation number m = 0 is set in the decimation circuit 22, the clock signal CLK1 supplied to the decimation circuit 22 is directly supplied to the digitizer 13 (in this case, CLK1 = CLK2). Data can be taken into the digitizer 13 at the same sampling rate as the sampling rate T1 of the data signal SMPD. The sampling rate for capturing a low-speed data signal into the digitizer 13 is generally expressed as a numerical value as follows:
(M + 1) × T1. Therefore, the thinning number m of the thinning circuit 22 may be set based on this equation.

As described above, according to the first embodiment, without changing the sampling rate of the sampling head 11 for a high-speed repetitive signal at all,
Since the sampling rate of the low-speed data signal taken into the digitizer 13 can be freely changed, the data sampled by the sampling head 11 is taken into the digitizer 13 at a low sampling rate by one sampling digitizer and observed at a high resolution. Measuring and / or analyzing the data sampled by the sampling head 11 at medium speed sampling by the digitizer 1
The data sampled by the sampling head 11 can be taken into the digitizer 13 by high-speed sampling and observed, measured and / or analyzed at low resolution. In other words, there is an advantage that the sampled data can be taken into the digitizer 13 at a sampling rate suitable for the use or at the user's request, and can be observed, measured and / or analyzed.

FIG. 6 is a block diagram showing the configuration of a second embodiment of a sampling digitizer according to the present invention.
In the first embodiment shown in FIG. 4, an analog multiplexer 23 is inserted between the sampling head 11 and the digitizer 13, and the low-speed data signal SMPD output from the sampling head 11 is converted into a first signal by the multiplexer 23. Second and third digitizers 13-
1, 13-2, and 13-3. In the second embodiment, the first digitizer 13-1 is a high-resolution digitizer configured to capture the data signal SMPD at a low sampling rate, and the second digitizer 13-2 is a high-resolution sampling rate. Is a low-resolution digitizer configured to capture the data signal SMPD, and the third digitizer 13-3 is a medium-resolution digitizer configured to capture the data signal SMPD at the medium-speed sampling rate. Thus, one sampling head 1
Three digitizers 13-1, 13-2, 13 for one
If -3 is prepared, the data signal SMPD is taken into the digitizer at a desired sampling rate simply by switching the output terminal of the multiplexer 23 in accordance with the setting of the thinning number m of the thinning circuit 22, and the high-speed repetition signal is reproduced. There is the advantage that the waveform can be observed, measured and / or analyzed. Furthermore, since only one sampling head is installed as a front end, it is possible to cope with various kinds of digitizers, so that there is an advantage that a space can be reduced and a cost can be reduced. It should be noted that the number of digitizers is not limited to three as in this embodiment, but may be increased or decreased as needed.

In the above embodiment, the case where the high-speed repetitive signal is converted into the low-speed data signal by the equivalent sampling method and the waveform of the high-speed repetitive signal is observed, measured and / or analyzed has been described.
2, the sampling rate T1 = 1 ns × (1 GHz
/ 1 MHz) = 1 μs to generate a clock signal with a frequency of 1 MHz, and the sampling head 11 and the thinning circuit 2
2, the jitter at a certain point of the waveform of the high-speed repetitive signal (for example, a certain point near the half-value point of a rapidly changing rising edge) can be measured by the digitizer 13 at a desired capturing speed (resolution). it can.

FIG. 3 shows the sampling digitizer having the above configuration.
The test pattern signal is written to the IC under test 300 at high speed and mounted on the pin card housed in the test head 200 of the IC tester shown in FIG. Can be observed, measured and / or analyzed at various acquisition rates (resolutions) with this sampling digitizer. Since the quality of the IC under test can be correctly determined by observing, measuring, and analyzing the waveform, the IC test can be executed for various test items, and a useful IC
A test device can be provided.

It is needless to say that a device having a similar function such as an oscilloscope may be used as a device (digitizer) for observing, measuring, and / or analyzing a signal waveform. While the present invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes, modifications and improvements can be made to the embodiments described above without departing from the spirit and scope of the invention. It will be clear to you. Accordingly, the invention is not limited to the illustrated embodiments, but rather all such modifications that fall within the scope of the invention as defined by the appended claims.
It also includes changes and improvements.

[0036]

As is apparent from the above description, according to the present invention, the sampling rate of the low-speed data signal to be taken into the digitizer can be freely changed without changing the sampling rate of the clock signal at all. In addition, there is an advantage that a low-speed data signal can be captured, digitized, and observed, measured, and / or analyzed at a sampling rate according to an application or a user's request. Further, since only one sampling head is installed as a front end, it is possible to cope with various kinds of digitizers, so that there is an advantage that a space can be reduced and a cost can be reduced.

In addition, if the sampling digitizer according to the present invention is mounted on a pin card accommodated in a test head of an IC tester, the waveform of a test pattern signal read from each pin of the IC under test at a high speed can be obtained by the sampling digitizer. It can be observed, measured and / or analyzed at various uptake rates (resolutions). Therefore, since IC tests can be executed for various test items, it is possible to provide a useful IC test apparatus according to an application or a user's request.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a conventional sampling digitizer.

FIG. 2 is a timing chart illustrating an equivalent sampling method applied to the sampling digitizer shown in FIG.

FIG. 3 is a block diagram showing an example of a conventional IC test apparatus.

FIG. 4 shows a first example of a sampling digitizer according to the present invention.
It is a block diagram showing an embodiment.

FIG. 5 is a timing chart for explaining the operation of the sampling digitizer shown in FIG.

FIG. 6 shows a second example of the sampling digitizer according to the present invention.
It is a block diagram showing an embodiment.

[Explanation of symbols]

 11: Sampling head 12: Clock generator 13: Digitizer 22: Thinning circuit 23: Multiplexer 100: IC tester main body 200: Test head

Claims (7)

[Claims] 1. A clock generating means for generating a clock signal at a predetermined sampling rate, and a high-speed repetitive signal inputted is sampled by a clock signal supplied from the clock generating means and converted into a low-speed data signal. A sampling unit, a signal waveform observation, measurement, or analysis device to which a low-speed data signal output from the sampling unit is supplied; and a clock signal supply path from the clock generation unit to the signal waveform observation, measurement, or analysis device. A sampling digitizer which is inserted and selectively thins out a clock signal applied to the signal waveform observation, measurement or analysis device. 2. A plurality of signal waveform observation, measurement or analysis devices, and a multiplexer for selectively supplying a low-speed data signal output from the sampling unit to the plurality of signal waveform observation, measurement or analysis devices. The sampling digitizer according to claim 1, further comprising: 3. The one multiplexer that supplies the low-speed data signal from among the plurality of signal waveform observation, measurement or analysis devices according to a decimation number set in the decimation means. The sampling digitizer according to claim 2, wherein an observation, measurement or analysis device is selected. 4. A decimation number set in the decimation means is m, and a sampling rate of the clock signal for sampling the high-speed repetitive signal is T1.
The sampling digitizer according to claim 1, wherein the low-speed data signal is read into the signal waveform observation, measurement, or analysis device at a sampling rate of (m + 1) × T1. 5. The sampling digitizer according to claim 1, wherein the signal waveform observation, measurement or analysis device is constituted by an oscilloscope. 6. A semiconductor which applies a test pattern signal to a semiconductor integrated circuit under test, logically compares response signals read out from the semiconductor integrated circuit under test, and judges pass / fail of the semiconductor integrated circuit under test based on the comparison result. An integrated circuit test apparatus, comprising: the sampling digitizer according to any one of claims 1 to 3. 7. The semiconductor integrated circuit test apparatus according to claim 6, wherein said sampling digitizer is mounted on a pin card housed in a test head of the semiconductor integrated circuit test apparatus.