JPH11190761A - Semiconductor test apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a waveform diagram similar to a shmoo plot diagram by connecting a test signal output from a plurality of drivers, a response signal input from a comparator to an input terminal of a signal selector via a relay and providing a waveform observation terminal which outputs an output signal of the signal selector out of a semiconductor-testing apparatus. SOLUTION: Signals of relays 21, 22 are connected to an input terminal 11h (h=1-m) of a signal selector 10 with the use of the relays 21, 22 provided for obtaining a shmoo plot diagram. In observing a signal output from a driver 35, the relay 21 is turned on and a signal of the relay is selected by the signal selector 10. An output terminal of the signal selector 10 is connected to a waveform observation terminal 13 of a semiconductor-testing apparatus body 30. An analog signal from the waveform observation terminal 13 is input to an external waveform observation apparatus 15. In observing a response signal from a DUT 39, the relay 21 is turned off and a relay 23 is turned on to send a test signal to the DUT 39, and relays 24, 22 are turned on to send the response signal to the signal selector 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention observes a test signal waveform output from a driver of a semiconductor test apparatus to a DUT (Device Under Test: semiconductor IC under test) and a response signal waveform output from the DUT, thereby quickly analyzing a failure. The present invention relates to a semiconductor test device to be performed.

[0002]

2. Description of the Related Art First, an outline of a semiconductor test apparatus will be described. FIG. 3 shows a basic configuration diagram of the semiconductor test apparatus. The tester processor 31 controls the entire apparatus, and supplies a control signal to each unit via a tester bus. The pattern generator 32 generates an application pattern given to the DUT 39 and an expected value pattern given to the pattern comparator 37. The timing generator 33 generates a test pulse signal for obtaining a test period signal and a test timing of the entire apparatus, and generates a waveform shaper 34 and a comparator 36.
And a pattern comparator 37, etc., and a strobe signal to the comparator 36, so as to take a test timing.

The waveform shaper 34 shapes the applied pattern from the pattern generator 32 into a test signal waveform, and forms a test signal waveform.
After 5, a test signal is given to the DUT 39. DUT3
9 from the comparator 3 at the time of the strobe signal.
The voltage is compared at 6 and the resulting logic signal is provided to the pattern comparator 37. The pattern comparator 37 is a comparator 3
6 and logical pattern of test result from pattern generator 32
, A logical comparison with the expected value pattern is performed to detect a match / mismatch, and the quality of the DUT 39 is determined. In the case of a failure, information is given to the fail memory 38 and the pattern generator 32
The information is stored together with the information from the server, and the failure analysis is performed later.

The DUT 39 is a semiconductor integrated circuit. When a test signal is applied to an input terminal, the DUT 39 propagates through an electronic circuit in the semiconductor IC and outputs a response signal from an output terminal. Therefore, the output response signal is output with a delay from the input test signal. Accordingly, in the semiconductor test apparatus, when the comparator 36 compares the voltage with the threshold voltage, a strobe signal (pulse) having a delay in the rise time of the test signal is given to the comparator 36, and the voltage is compared at the time of the strobe signal. Since the delay time of the strobe signal differs for each type of DUT 39, different types of DUT 3
It is necessary to check the delay time in advance every nine. The relationship between the delay time and the pass and fail due to the change in the comparison voltage is shown in the figure below.
ot) FIG.

FIG. 4 shows a detailed configuration diagram from the driver 35 to the comparator 36 in the pin electronics section of the semiconductor test apparatus main body 30. The driver 35 receives the test signal from the waveform shaper 34, converts the test signal into a test signal voltage suitable for the DUT 39, and supplies the test signal voltage to the DUT 39 via the input / output terminal 40i (i = 1 to n) of the semiconductor test apparatus main body. Here, n is the maximum number of pins of the DUT 39. Driver 3
5, VIH is a high level voltage, and VIL is a low level voltage. Therefore, by changing VIH and VIL, it is possible to convert to a test signal voltage suitable for the DUT 39. The response signal from the DUT 39 is provided to the comparator 36 via the input / output terminal 40i. VOH of the comparator 36 is a high-level threshold voltage for comparing a voltage with a response signal from the DUT 39. VOL is a low-level threshold voltage. The threshold voltage is a reference voltage for determining good or bad, and is determined by various DUT39 standards (specifications). Therefore, VOH and V
Any DUT of different types by changing OL
39 can also be converted into a logic signal with a threshold voltage suitable for it.

A test signal from a driver 35 is supplied to a DUT 39 via a relay 23 which is turned on and off, and the DUT 39
The response signal from 39 passes through the relay 24 to the comparator 3
6 given. Also, as shown in FIG.
The test signal from 5 is branched before the relay 23, and a circuit is provided for connection to the comparator 36 via the relay 21 and the relay 22. One purpose of this circuit was provided to obtain a Shmoo plot.

FIG. 5 shows a Shmoo Plot.
FIG. The horizontal axis represents the delay time from the test signal rise time of the strobe signal (STRB), and is generally 100 ps (100 picosec: 100 × 10
^-12 seconds) expressed in units of about one unit. The vertical axis is in units of mV (millivolt) from the threshold voltage of the DUT standard of VOH or VOL. Here, for simplicity of description, only VOH will be described, and description in VOL will be omitted. The * mark is a plot of a pass mark when VOH or STRB is changed, and the blank mark is a fail (Fa)
il). The test signal and the response signal can be observed with this shmoo plot. The unit of the horizontal axis and the vertical axis is
It differs depending on the type and standard of the DUT 39.

In order to observe a test signal, in FIG. 4, the relay 21 and the relay 22 are turned on (connected), the relays 23 and 24 are turned off (cut off), and the test signal from the driver 35 is directly compared with the comparator. To make a Shmoo plot. The Shmoo plot is VO
Until the value of H becomes the value of VIH, * is marked on all, and VI
When the value of H is exceeded, there is no mark.

In order to observe the response signal, in FIG. 4, the relay 23 and the relay 24 are turned on, the relay 21 and the relay 22 are turned off, a test signal from the driver 35 is supplied to the DUT 39, and the response signal is compared with the comparator. And a Shmoo plot is obtained in the same manner as described above. In conventional semiconductor test equipment, if the driver 35 or comparator 36 is defective or defective, the serviceman of the manufacturer repairs the inside of the housing, so the means by which the user can observe the waveform of the test signal and response signal is smooth. -There was only a plot.

[0010]

When the DUT 39 is a mass-produced product and GO-NOGO determination is made, a conventional semiconductor test apparatus is sufficient. However, the development of semiconductor ICs as DUTs has been remarkable, and the internal structure of VLSIs that have been increasingly integrated has a complicated circuit configuration. In the case of a developed product or a prototype, the test is not only a mere judgment of quality, but in the case of a defect, it is necessary to perform a defect analysis by any means. As one of the means, there has been a demand for a semiconductor test apparatus to observe and analyze a test signal and an analog signal of a response signal in real time.

Although a conventional Shmoo plot diagram can satisfy a considerable demand, since the VOH and STRB are moved and plotted before the Shmoo plot diagram is obtained, a considerable amount of time is required before the response signal waveform is obtained. take time. Also, real-time analog signals cannot be measured.

According to the present invention, in a failure analysis of a DUT,
The objective is to realize a semiconductor test device that can observe the input and output analog signals of any terminal of the DUT in real time even during measurement, and can obtain a waveform diagram similar to a Shmoo plot diagram by performing automatic measurement. I do.

[0013]

In order to achieve the above object, the present invention provides a semiconductor test apparatus main body 30 having a plurality of input / output terminals 40i (i = 1 to n), that is, all drivers 35.
Of the output test signal and the input response signal of the comparator 36, an arbitrary analog signal waveform can be taken out from a waveform observation terminal through a signal selector, and an analog signal required in real time can be obtained by an external waveform observation device. To observe. A signal selector such as a multiplexer is used to extract an arbitrary analog signal waveform.
Further, automatic measurement can be performed by using a programmable signal selector.

The externally used waveform observation device is, for example, a digital sampling oscilloscope, which is preferably capable of observing an analog waveform and simultaneously obtaining digital waveform data. The digital data is subjected to arithmetic processing to perform a diagram equivalent to a Shmoo plot diagram or more advanced arithmetic processing. Note that a configuration may be provided in which a trigger signal for synchronizing from the semiconductor test device to the waveform observation device 15 is provided. Next, the configuration will be described.

The structure of the first invention is as follows. DU
A semiconductor test apparatus comprising: a plurality of drivers for applying test signals to a plurality of input pins of T; and a plurality of comparators for inputting response signals from a plurality of output pins of a DUT. Through each relay, selected a response signal of multiple comparator inputs, via each relay, a signal selector to select any of the analog signals connected to each input terminal, and selected an arbitrary waveform And a waveform observation terminal for outputting an output signal of the signal selector from the semiconductor test apparatus main body to the outside.

The structure of the second invention is as follows. A signal selector according to a first aspect of the present invention selects an input signal by synchronizing operation timings of a plurality of relays associated with a plurality of drivers and a plurality of relays associated with a plurality of comparators, and generates a synchronization signal together with an analog signal. This is a programmable signal selector that supplies a waveform observation device via a waveform observation terminal and performs automatic measurement.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 shows a configuration diagram of an embodiment of the present invention, and FIG. 2 shows a waveform diagram of an example of a real-time analog signal observed in the present invention. 3 and 4 are denoted by the same reference numerals. First, FIG. 1 will be described.

FIG. 1 is a block diagram of an embodiment of the present invention. The relay 21 and the relay 22 for obtaining the Shmoo plot diagram in FIG.
To the input terminal 11h (h = 1 to m). The signal selector 10 is an analog multiplexer. FIG.
Shows only one signal selector 10, but it goes without saying that if the input terminal 11h is insufficient, a plurality of signal selectors are arranged in parallel, and their output signals are further selected by the signal selector.

The operation of the configuration shown in FIG. 1 will be described. When observing the analog waveform of the test signal output from the driver, the relay 21 is turned on, and the signal selector 10 selects the signal. The output terminal of the signal selector 10 is connected to the waveform observation terminal 13 of the semiconductor test apparatus main body 30. Therefore, when an analog signal from the waveform observation terminal 13 is input to the external waveform observation device 15, the test signal can be observed in real time.

To observe the response signal from the DUT 39, the relay 21 on the driver 35 side is turned off and the relay 23
Is turned on to supply a test signal to the DUT 39. On the comparator 36 side, the relay 24 is turned on to input the response signal from the DUT 39, and the relay 22 is also turned on to supply the response signal to the signal selector 10. Signal selector 1
0 selects the response signal and supplies it to the external waveform observation device 15 via the waveform observation terminal 13 to thereby provide the DUT 3
9 can be observed in real time.

The waveform observation device 15 may be a commercially available digital sampling oscilloscope. Since analog signals are converted into digital signals by analog-to-digital conversion, signal processing can be performed in any manner. Since the amplitude voltage of the response signal can be known,
Data equivalent to the plot can also be obtained. Further, the user can perform advanced signal processing by using a program created by the user. This is the first invention.

Further, when the sweep measurement is performed in synchronization with the switching timing of the relay of the semiconductor test apparatus main body 30, the switching timing of the signal selector 10, and the data acquisition timing of the waveform observation apparatus, all the input and output of the semiconductor test apparatus main body 30 are obtained. An analog signal at the output terminal 40i can be automatically measured in a short time. That is, the input signal is selected in synchronization with the operation timing of the relays 21 on the plurality of drivers 35 and the relays 22 on the plurality of comparators, and the programmable signal selection that supplies the synchronization signal together with the analog signal to the waveform observation device 15. The use of the device 10 enables automatic measurement. This is the second invention.

FIG. 2 shows an example of an analog signal waveform diagram observed in the present invention. The rising waveform and the falling waveform are superimposed and displayed. The horizontal axis is the time axis, 500ps / div
Displayed with. The vertical axis represents the voltage axis at 100 mV / div. When driven by an external trigger signal, the delay time can be determined. The rise time of 10-90% from the waveform is 48
2 ps and the fall time is 509 ps. You can also ask for data automatically.

[0024]

As described above in detail, the present invention provides an analog waveform of a test signal output from all the drivers 35 in the semiconductor test apparatus main body 30 and a response from the DUT 39 input to all the comparators 36. An analog waveform of a signal can be observed in real time, data can be processed in a short time, and information more than a conventional Shmoo plot can be obtained.

A user of a semiconductor test apparatus, particularly a developer or a designer of a semiconductor IC, can exert its power in failure analysis and characteristic analysis of a newly manufactured semiconductor IC. Furthermore, various characteristics can be analyzed by the program created by the user himself,
Automated measurements are possible, and semiconductor test equipment is more valuable. The technical effects of the present invention are significant.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is an example of a real-time analog signal waveform diagram observed in the present invention.

FIG. 3 is a basic configuration diagram of a semiconductor test apparatus.

FIG. 4 is a detailed configuration diagram of a conventional example from a driver 35 to a comparator 36 of the semiconductor test apparatus.

FIG. 5 is an example of a diagram of a conventional Shmoo plot.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 signal selector 11 i (i = 1 to m) signal selector input terminal 13 waveform observation terminal 15 waveform observation device 21, 22, 23, 24 relay 30 semiconductor test equipment main body 31 tester processor 32 pattern generator 33 timing Generator 34 Waveform shaper 35 Driver 36 Comparator 37 Pattern comparator 38 Fail memory 39 DUT (Semiconductor IC under test) 40i (i = 1 to n) Input / output terminal 41 Strobe signal (STRB) input terminal

Claims (2)

[Claims] A plurality of drivers for applying a test signal to a plurality of input pins of the DUT;
(39) In a semiconductor test apparatus having a plurality of comparators (36) for inputting response signals from a plurality of output pins, a plurality of test signals output from a plurality of drivers (35) are relayed through respective relays (21). Comparator (36)
The response signal of the input is transmitted via each relay (22),
A signal selector (10) for selecting an analog signal connected to each input terminal (11h), and an output signal of the signal selector (10) for selecting an arbitrary waveform is output from the semiconductor test apparatus main body (30) to the outside. A semiconductor test apparatus comprising: a waveform observation terminal (13) for outputting. 2. The semiconductor test apparatus according to claim 1, wherein the automatic measurement is performed by controlling the pin electronics, the signal selector (10), and the waveform observation device (15).