JPH0627195A - Lsi test device - Google Patents

Abstract

PURPOSE:To collectively test numerous LSIs having many pins. CONSTITUTION:A measured board 25 provided with multiple LSIs and a standard IC module 23 whose functional operability has been confirmed are supplied with a test signal by a pulse generating part 21 through an input control part 22, based upon the predetermined test specification. The output signal from the standard IC module 23 is supplied to a measured output control part 26 through on output control part 24. Respective input signals from the pulse generating part 21 are supplied to respective LSIs an a measured board 25 in a time division manner. These output signals from LSIs are supplied to the measured output control part 26 in a time division manner. The measured output control part 26 compares/discriminates the output signal from LSIs on the measured board 25 supplied in a time division manner with that from the standard IC module 23, and the obtained result is supplied to a tester main unit 20. The tester main unit 20 displays the result on a display device 3 or an output device 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI testing apparatus, and more particularly to an apparatus for testing a large number of LSIs.

[0002]

2. Description of the Related Art Conventionally, as an LSI test apparatus, for example, there is one as shown in FIG. This test apparatus tests a large number of LSIs connected to the terminal 10 to be measured. The terminal 10 to be measured is connected to the test station 9 via a large number of wirings 13, and the test station 9 is connected to the format control unit 8 via a large number of wirings 12.
It is connected to the.

The format controller 8 is supplied with a test input signal from the test pattern generator 6, a timing signal from the timing generator 7, and a power supply 5 to each LSI to be measured. The proper power supply voltage is also supplied. The format control unit 8
These timing signal, test input signal, and power supply voltage are adjusted to a prescribed test pattern signal, and are simultaneously supplied to each LSI to be measured via the wiring 12, the test station 9, the wiring 13, and the terminal to be measured 10.

The output signal generated by each LSI to be measured in response to the test pattern signal is compared with expected value data for each of these output signals in the test station 9, and the comparison result is fetched into the test computer 2. Then, it is processed here and output to the display device 3 configured by a CRT or the like or the output device 4 configured by a printer or the like.

Power source device 5, test pattern generator 6,
The timing generator 7 is controlled by the test computer 2, and the test computer 2 is based on the test data designated by the input unit 1 among the various test data stored in the test data file 11. , The test pattern generator 6 and the timing generator 7 are controlled. Also, test station 9
However, expected value data to be compared with the output signal of each LSI to be measured is also generated based on this test data. In addition,
Each test data stored in the test data file 11 is created based on a simulation or the like performed by another computer.

[0006]

As described above, in the conventional test apparatus, the test input signals are simultaneously supplied to the LSIs to be measured, and the output signals from the LSIs to be measured are supplied to the test station 9. Supply is taking place at the same time.
Therefore, the number of LSIs under test that can be tested at the same time is the number of wirings 12 between the format controller 8 and the test station 9 and the number of wirings 13 between the test station 9 and the terminal for measurement 10. Limited by Therefore, when the scale of the LSI to be measured increases or the number of pins increases, it is necessary to newly develop a test apparatus that can simultaneously test a large number of such LSIs to be measured. is necessary. Moreover, in order to test mass-produced LSIs, it is a large investment to improve the test capability because many such test devices are required.

[0007]

In order to solve the above problems, according to the present invention, a board provided with a plurality of LSIs to be measured, a standard module whose functional operation has been confirmed, and a predetermined test standard. And a test signal supply means for supplying a test signal to the standard module and each LSI to be measured on the board, and output signals of the standard module and each LSI to be measured for the test signal. The comparing / determining means and the test signal from the test signal supplying means are sequentially supplied to the LSI to be measured, and the LS to be measured is synchronized with the switching.
And a switching control means for sequentially switching the output signal from I and supplying it to the comparison / determination means.

[0008]

According to the present invention, the test signal is supplied to the standard module, and the output signal generated by the standard module in response thereto is supplied to the comparing and determining means. In addition, the switching control means sequentially switches the test signals, so that each L to be measured is measured.
Supply to SI sequentially. In response to this, each LSI to be measured sequentially generates output signals, which are sequentially supplied to the comparison / determination means. Therefore, the comparison / determination means sequentially compares and determines the output signal of the standard module and the output signal of each LSI to be measured.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS This embodiment has a tester main body 20 as shown in FIG. 1, which is composed of a CPU, a memory and the like. The tester main body 20 is provided with an input unit 1, a display device 3, an output device 4, a power supply device 5, and a test data file 11 as in the test device shown in FIG. A description of these is omitted.

The tester main body 20 is also provided with a pulse generator 21, which generates a pulse signal based on the data read by the tester main body 20 from the test data file 11 in response to a command from the input unit 1. To do. This pulse signal is supplied to the input control unit 22. Input control unit 2
2 adjusts the electrical characteristics of the pulse signal from the pulse generator 21 based on the control from the tester main body 20, and supplies various pulse signals described later to the standard IC module 23 and the board under test 25.

The standard IC module 23 is an LSI chip which has been confirmed to operate correctly, a circuit composed of an IC or a transistor, or a programmable LSI such as PLD, FPGA, EPROM or the like. The power supply device 5 supplies the power supply voltage VDD, the input control unit 22 supplies the clock signal CLK, and the input control unit 22 supplies various input signals. Each output signal corresponding to these input signals is supplied to the output control unit 24. The output control section 24 supplies these output signals to the tester main body 20 and the output control section 26 to be measured.

The board 25 to be measured, as shown in FIG.
The objects to be measured S1, S2 ... (These correspond to the standard IC module 23), and the objects to be measured S1, S2 ... The clock signal CLK is supplied via the power supply terminal 59 and the clock terminal 58, respectively. Input control gates G1, G2, G7, G8, are provided on the input side and the output side of the measured objects S1, S2, ...
G9, G10, ... and output control gates G3, G4, G
5, G6, G11, G12 ... Are provided. Each of these control gates incorporates a flip-flop and an AND gate.

A test control signal, which will be described later, is supplied to each of these control gates from the input control section 22 through the control terminal 51. The input / output control gates G1 and G3 of the measured object S1 are supplied with the measurement cycle signal T1 from the input control section 22, and the input / output control gates G2 and G4 of the measured object S2 are input. The measurement cycle signal T2 is supplied from the control unit 22, and the measured object S3 is measured.
The input / output control gates G5 and G7 are supplied with the measurement cycle signal T3 from the input controller 22. Similarly, the corresponding measurement cycle signal is also supplied to the input / output control gates of the other objects to be measured. This measurement cycle signal is generated in the same number as the number of each measured object.

Each input control gate G1, G2, G7,
Various input signals are supplied to the G8, G9, G10, ... From the input control section 22 via the input terminal 56, and these input signals are input to the respective input control gates G1, G2, G7, G8, G.
9, G10 ... In accordance with the test control signal and the measurement cycle signal supplied to each of the measured objects S1, S2.
・ Supplied to The output signals corresponding to these input signals are output to the output control gates G3, G4, G5, G6, G1.
1, G12 is supplied to the output control unit 26 to be measured via the output terminal 57.

The output control unit 26 to be measured has a built-in comparison circuit, compares the output signal from the standard IC module 23 with the output signal supplied from the measured board 25, and outputs the comparison result. It is supplied to the tester main body 20 based on the test control signal and the measurement cycle signal.

In this test apparatus, as shown in FIG. 3, first, when the data of the test standard specification is designated and input from the input section 1, the data designated from the test data file 11 is introduced into the tester main body 20 (step S40). ). At this time, for example, the standard IC module 23, the measured board 2
5, the frequency of the clock signal, the voltage level, the duty ratio, the test cycle signals T1, T2,
.... Time charts of the input signals I1, I2, ...
When a delay or the like is designated from the input section 1, the tester main body 20 processes the data corresponding to the delay, and the processing result is sent to the pulse generating section 21, where the clock signal CLK and the input signals I1, I2. .. is generated in accordance with the test standard (step S41).

At this time, a voltage corresponding to the control signal having the value designated by the tester main body 20 is generated from the power supply section 5.
The clock signal generated by the pulse generator 21 and the input signal I
1, I2, ... Are supplied to the standard IC module 23 via the input control unit 22 (step S42). As will be described later, these signals are also supplied to the board under test 25.

Clock signal CLK, input signals I1, I
2 ... is supplied to the standard IC module 23, the standard IC module 23 operates, and these input signals and each output signal generated in response to these input signals are output via the output control unit 24. It is sent to the memory standard file of the tester main body 20 or the output control unit 26 of the measured object (step S43).

In such a state, as shown in FIG. 4, the test control signal CON and each test cycle signal T1,
T2 ... Is supplied to the tester main body 20 and the measured board 25 from the pulse generator 21 via the input controller 22 (step S44). In accordance with this, each measured object S
1, S2 ... Controls the measurement cycle (step S
45).

That is, the test control signal CON is supplied to each input / output gate, and T1 of each test cycle signal is supplied.
Is supplied to the AND gate in the I / O control gates G1 and G3 via the flip-flops in the gate.
Since the measurement cycle signal T1 is also supplied to the AND gate in synchronization with this, each input / output control gate of the measured object S1 is opened. The clock terminal 58 and the input terminal 5 are connected to the measured object S1 through the opened input control gate G1.
6 to the clock signal CLK, each input signal I1, I2 ...
・ Is supplied. As a result, output signals O1, O2 ... Are generated from the measured object S1. An output control gate G in which each of these output signals O1, O2 ... Is opened.
3, and is supplied to the output control unit 26 of the measured object via the output terminal 57.

Next, the test cycle signal T1 disappears and T
2 also occurs, the input / output control gate G2,
G4 is simultaneously opened, and each clock signal CLK, each input signal I1, I2, ... Is supplied to the measured object S2 via the input control gate G2. The output control gate G in which the output signals O1, O2, ...
4 through the output terminal 57, the output control unit 26 to be measured.
Is supplied to. Thereafter, similarly, the input / output signals of each measured object are supplied to the output control unit 26 of the measured object under the control of the test cycle signal (step S46).
That is, the output signals O1, O2, ... Of the objects S1, S2, ...

In this way, the output signals O1, O2, ... Of the measured objects S1, S2, ...
It is compared and determined with the corresponding one of the output signals obtained from the above, and the comparison result is supplied to the tester main body 20 (step S47). The tester main body 20 displays the comparison result on the output device 4 or the display device 3 (step S4).
8). As a result, the quality of each measured object is determined.
Note that when a mass-produced product is used as the measurement target, the mass-produced product is sorted using the determination result.

Each measurement cycle signal T1, T2 ...
Is performed as a very short cycle time, and the pass / fail judgment is performed in this short cycle.

In this way, each measured object S is time-divided.
Since each input signal is supplied to 1, S2, ... And each output signal is output, the number of wirings required on the measured board 25 is the number of input signals input to one measured object. And the number of output signals output from one measured object, the number of power supply lines, and the number of clock signal supply lines,
It is only the total number of lines supplying test control signals and the number of test lines supplying each test cycle signal equal to the number of measured objects. This can be handled simply by increasing the number of signal supply lines.

In the above embodiment, the standard IC module 2
Although 3 is a chip such as an LSI, a chip or a board such as a PLD or FPGA that can be easily rewritten can be used as the standard IC module 23. In this case, LS
Since it is easy to change the specifications of the I-chip and debug the development,
Prototype development time is shortened. If the result of the trial production is good, the trial product can be used as it is as the standard IC module 23.

In the above embodiment, the standard IC module 2
The output signal of 3 and the output signal from the measured object are configured to be compared and determined by the output control unit 26 of the measured object. However, the tester main body 20 stores each output signal of the standard IC module 23. Alternatively, the tester main body 20 may be configured to compare and determine with the output signal from the measured object.

[0027]

As described above, according to the present invention, the switching control means supplies time-divisionally input signals to a plurality of LSIs, which are the objects to be measured, and outputs the signals from the objects to be measured. Since it is configured to output signals in a time division manner,
It is possible to test the quality of many LSIs to be measured in a short time. Further, according to the present invention, input gate means and output gate means are provided on the input side and the output side of each object to be measured, and these gate means are sequentially opened by a gate open signal. Therefore, even if it is necessary to increase the number of objects to be measured, it is only necessary to increase the number of signals to be supplied to the gate opening means, and wiring for newly supplying an input signal and outputting an output signal are required. It is not necessary to increase the number of wirings, and the number of objects to be measured collectively measured can be easily increased, and the processing capacity can be easily improved. When a chip or board, such as PLD or FPGA, which can be easily rewritten, is used as the standard module, the development and trial production is easy, and when the development is completed, the prototype can be directly used as the standard module. Therefore, the work of editing the test pattern is unnecessary, and the labor can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an LSI test apparatus according to the present invention.

FIG. 2 is a block diagram of a measured board used in the same embodiment.

FIG. 3 is a flowchart of the same embodiment.

FIG. 4 is a timing chart of the same embodiment.

FIG. 5 is a block diagram of a conventional LSI test apparatus.

[Explanation of symbols]

 1 Input Unit 3 Display Device 4 Output Device 5 Power Supply Unit 20 Tester Main Body 21 Pulse Generation Unit 22 Input Control Unit 23 Standard IC Module 24 Output Control Unit 25 Measured Board 26 Measured Output Control Unit

Claims (2)

[Claims] 1. A board provided with a plurality of LSIs to be measured, a standard module whose functional operation is confirmed, and a test for each standard LSI and each LSI to be measured on the board based on a predetermined test standard. A test signal supplying means for supplying a signal, a means for taking in and comparing output signals of the standard module and the LSI under test for the test signal, and a test signal from the test signal supplying means. An LSI test apparatus comprising: a switching control means for sequentially switching and supplying to the LSI to be measured and, in synchronization with this switching, sequentially switching an output signal from the LSI to be measured and supplying it to the comparing and judging means. 2. A test signal generating means for generating a test signal based on a predetermined test standard, a standard module whose functional operation is confirmed and to which the test signal is supplied, and a plurality of LSIs to be measured. Input gate means respectively provided on the input side and supplied with the test signal; output gate means respectively provided on the output side of the LSI to be measured and supplied with the output signal of the LSI to be measured; Gate opening signal generating means for sequentially supplying a gate opening signal to the corresponding one of the input gate means and each of the output gate means, and the output signal from the LSI to be measured output through the opened output gate means. An LSI test apparatus comprising: a comparison / determination unit that compares and determines the output signal of the standard module.