JP3955708B2 - Built-in self-test circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit incorporating a self test circuit (BIST) for testing a RAM used in the integrated circuit, and more particularly to a data generator that generates and supplies a diagonal pattern as a self test pattern for the RAM. The present invention relates to an integrated circuit having a self-test circuit.
[0002]
[Prior art]
With the recent increase in scale and integration of integrated circuits, testing of integrated circuits has become an increasingly difficult problem, and reduction in test costs and improvement in test quality are required. For this reason, a self-test circuit is built in the integrated circuit in advance, and the integrated circuit has a self-test function. 2. Description of the Related Art Conventionally, in an integrated circuit having a self-test circuit for a RAM in the integrated circuit, the self-test circuit generates a diagonal pattern that changes the address by distinguishing the RAM address into an X address and a Y address. I was testing.
[0003]
[Problems to be solved by the invention]
However, since the number of bits of the X address and the Y address differs depending on the shape of the RAM, when a RAM having a different shape is arranged in the integrated circuit, a diagonal pattern is formed in the integrated circuit. The data generator to be generated has to be arranged for each RAM shape. For this reason, in the integrated circuit, the area occupied by the self-test circuit increases in proportion to the type of RAM shape, resulting in an increase in hardware overhead.
[0004]
The present invention has been made in order to solve the above-described problems, and can share a data generator for generating a diagonal pattern even when RAMs having different shapes are arranged in an integrated circuit. Thus, an object of the present invention is to obtain a built-in self-test circuit capable of reducing an increase in the area occupied in an integrated circuit.
[0005]
Although different from the present invention, Japanese Patent Application Laid-Open No. 5-241882 discloses a BIST circuit having a combined data generator and an LFSR.
[0006]
[Means for Solving the Problems]
A built-in self-test circuit according to the present invention is a built-in self-test circuit in an integrated circuit including a data generation circuit that supplies a diagonal pattern to a RAM that is a device under test in the integrated circuit. X address register unit that generates and outputs X addresses of all the RAMs that perform, Y address register unit that generates and outputs the Y addresses of all the RAMs that perform the test, X address register unit and Y address register unit The chip enable control unit that generates and outputs an enable signal to the RAM to be tested from the X address and the Y address output from, and generates and outputs test data for all the RAMs to be tested Data register unit composed of shift registers and X address register unit In which a control unit for controlling the operation of the Y address register and a data register unit.
[0007]
The chip enable control unit identifies a RAM shape to be tested from the X address and Y address output from the X address register unit and the Y address register unit, and an enable signal for the RAM of the identified shape. May be generated and output.
[0008]
Specifically, the chip enable control unit compares the number of bits of the X address and Y address output from the X address register unit and the Y address register unit with a corresponding comparison reference value, and performs a test. The shape of RAM to be performed is specified.
[0009]
Further, the X address register unit and the Y address register unit may be constituted by registers with an up counter.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described in detail based on the embodiments shown in the drawings.
FIG. 1 is a schematic block diagram showing a built-in self-test circuit example of an integrated circuit according to an embodiment of the present invention. Note that FIG. 1 shows only a data generation circuit of a self-test circuit (hereinafter referred to as a BIST circuit) incorporated in an integrated circuit in order to test a RAM used in the integrated circuit. The part is omitted.
The data generation circuit 1 in the RAM BIST circuit shown in FIG. 1 is a circuit that supplies a diagonal pattern, which is a self test pattern of the RAM, to the RAM, which is a device under test.
[0011]
In FIG. 1, a data generation circuit 1 includes an X address register 2 that generates and outputs X addresses of all RAMs to be tested, a Y address register 3 that similarly generates and outputs Y addresses, and an X address register. 2 and a chip enable control circuit unit 4 that generates and outputs an enable signal from the X address and Y address output from the Y and Y address registers 3 to the RAM to be tested. Further, the data generation circuit 1 includes a data register 5 that generates and outputs test data to the RAM to be tested, an X address register 2, a Y address register 3, and a data register in accordance with an external control signal. 5 and a sequencer 6 for performing operation control.
[0012]
The X address register 2 and the Y address register 3 are registers with an up counter. The register size of the X address register 2 is the maximum X address width in the RAM to be tested, and the register size of the Y address register 3 is the test target. Each of the RAMs has the maximum Y address width. The data register 5 is composed of a shift register, and the register size has the maximum data width in the RAM to be tested.
[0013]
When the sequencer 6 receives a test mode start signal GO, which is a signal for instructing the start of a test operation for the RAM, the sequencer 6 starts the test mode operation based on a preset sequence. At this time, a predetermined clock signal CK is input from the outside, and the clock signal CK is output to the X address register 2, the Y address register 3, and the data register 5, respectively. As described above, the X address register 2, the Y address register 3, the data register 5, and the sequencer 6 operate based on the clock signal CK input from the outside.
[0014]
The sequencer 6 further outputs a control signal CU for counting up to the X address register 2 and the Y address register 3, respectively, and each address output from the X address register 2 and the Y address register 3, respectively. For example, a low level reset signal RB for setting all data to 0 is output as necessary. The X address register 2 and the Y address register 3 count up the registers in synchronization with the clock signal CK when the control signal CU is at a high level, for example, and the generated X address and Y address are stored in the test target RAM. Output to the chip enable control circuit unit 4 as well.
[0015]
In addition, the sequencer 6 outputs shift-in data SIN, which is data to be shifted and stored in the shift register, to the data register 5 and outputs a control signal SE for controlling the shift operation of the shift register. . For example, when the high level control signal SE is input from the sequencer 6, the data register 5 shifts the shift-in data SIN stored in one register of the shift register in synchronization with the clock signal CK. Further, the sequencer 6 outputs a write enable signal WE to the RAM of each shape to be tested, and at the same time, for example, a low level reset signal RB for setting all data output from the data register 5 to “0”. For example, a low level reset signal SB for setting all to “1” is output as necessary.
[0016]
Here, the data register 5 generates a plurality of bits of test data. That is, when the control signal SE is at a high level, when the input shift-in data SIN is “1”, the data register 5 is stored in the first register of the shift register. The data “1” is stored and the data “0” is stored in the other registers. The data “1” is sequentially transferred to the next register in synchronization with the clock signal CK while the control signal SE is at the high level. Shift and output each. On the other hand, when the input shift-in data SIN is “0”, the data register 5 stores “0” data in the first register of the shift register and “1” data in the other registers. Stored, and in synchronization with the clock signal CK while the control signal SE is at a high level, the data of “0” is sequentially shifted to the next register and output.
[0017]
For example, when the test data is 8 bits and the shift-in data SIN is “1”, the first output data is “00000001”, and the data output at the next timing is “00000010”. Next, it becomes “00000100”. On the other hand, when the shift-in data SIN is “0”, the data output first is “11111110”, the data output at the next timing is “11111101”, and then “11111011”. It will become.
[0018]
On the other hand, the chip enable control circuit unit 4 specifies the RAM shape from the input X address and Y address, and outputs an enable signal to the RAM of the specified shape. Here, normally, the X address and the Y address indicating the RAM address differ in the number of bits depending on the shape of the RAM. From this, the chip enable control circuit unit 4 detects the number of bits of the inputted X address and Y address, and specifies the shape of the RAM indicated by the address from the detected number of bits. Further, the chip enable control circuit unit 4 outputs an enable signal to the RAM having the specified shape.
[0019]
FIG. 2 is a schematic diagram illustrating a circuit example of the chip enable control circuit unit 4. The operation of the chip enable control circuit unit 4 will be described in more detail with reference to FIG.
In FIG. 2, if the shape of the RAM is k (k is a natural number of k> 0), the chip enable control circuit unit 4 detects X address comparators X1 to Xk, Y that detect the number of bits of the X address. Y address comparators Y1 to Yk for detecting the number of bits of the address, NOR circuits N1 to Nk, and corresponding reference reference values are output to the X address comparators X1 to Xk and the Y address comparators Y1 to Yk, respectively. The comparison reference value generating circuit 11 is configured.
[0020]
The output terminals of the corresponding X address comparators X1 to Xk are connected to one input terminals of the NOR circuits N1 to Nk, respectively, and the corresponding Y address comparison is connected to the other input terminals of the NOR circuits N1 to Nk. The output ends of the devices Y1 to Yk are connected to each other. From the outputs of the NOR circuits N1 to Nk, enable signals CE1 to CEk are output to the RAM of the corresponding shape. Further, each X reference comparator X1 to Xk and each Y address comparator Y1 to Yk are input with respective comparison reference values set in advance for each shape correspondingly from the comparison reference value generating circuit 11, respectively. The X address from the X address register 2 is input to each X address comparator X1 to Xk, and the Y address from the Y address register 3 is input to each Y address comparator Y1 to Yk.
[0021]
The X address comparator Xm (m = 1 to k) compares the number of bits of the input X address value with the comparison reference value input from the comparison reference value generation circuit 11, and the number of bits of the X address value is If it is equal to or lower than the comparison reference value, a low level signal is output from the output terminal to one input terminal of the corresponding NOR circuit Nm. If the comparison reference value is exceeded, a high level signal is output.
[0022]
Similarly, the Y address comparator Ym (m = 1 to k) compares the number of bits of the input Y address value with the comparison reference value input from the comparison reference value generation circuit 11, and determines the Y address value. When the number of bits is equal to or smaller than the comparison reference value, a Low level signal is output from the output terminal to the other input terminal of the corresponding NOR circuit Nm. When the number of bits exceeds the comparison reference value, a High level signal is output. When a low level signal is output from each of the X address comparator Xm and the Y address comparator Ym, the NOR circuit Nm outputs a high level enable signal CEm that enables the RAM of the corresponding shape.
[0023]
3 and 4 are flowcharts showing an example of the operation of the sequencer 6 shown in FIG. 1. The operation of the sequencer 6 will be described in more detail with reference to FIGS. In FIG. 3 and FIG. 4, processing performed in each flow is performed by the sequencer 6 unless otherwise specified.
[0024]
In FIG. 3, first, when an externally input test mode start signal GO rises, the test mode operation starts (step S1). As an initialization process, the reset signal RB is set to the low level, and the reset signal SB is set. The control signals SE and CU are set to the low level at the high level, and the output of the write enable signal WE is stopped (step S2). By doing so, the initial values of the X address and Y address, that is, the X address and Y address of all “0” are output from the X address register 2 and the Y address register 3, and also output from the data register 5. All the test data is “0”. Further, the data chip enable control circuit unit 4 outputs an enable signal to the RAM having a shape corresponding to the input X address and Y address.
[0025]
Next, in the state where the control signal SE is at the low level, the shift-in data SIN of “1” is output, the data of “1” is stored only in the first register in the shift register of the data register 6 and the initial test data is stored After that, the shift-in data SIN is set to “0” and the initial test data setting is completed (step S4). Next, the test data set by outputting the write enable signal WE is written into the RAM of the corresponding shape (step S5), the output of the write enable signal WE is stopped again, and the data is written into the RAM of the corresponding shape. Ends (step S6).
[0026]
Next, the control signal CU is raised and the X address register 2 counts up and outputs the X address, and the Y address register 3 counts up and outputs the Y address (step S7). Thereafter, the control signal CU is lowered to complete counting up of the X address and the Y address (step S8). Next, it is checked whether or not the Y address has been counted up to the maximum Y address value (step S9). If the Y address has not been counted up (NO), the control signal SE is raised to the data register 5 On the other hand, the test data is sequentially shifted and the data is supplied to the RAM (step S10). Thereafter, the control signal SE is again lowered to complete the shift of the test data (step S11), and the process returns to step S5.
[0027]
On the other hand, if it is counted up to the maximum Y address value in step S9 (YES), the process proceeds to step S12 in FIG. 4, the reset signal RB is set to the high level, the reset signal SB is set to the low level, and the control signals SE and CU Are set to the Low level, and the output of the write enable signal WE is stopped (step S12). In this way, all the test data output from the data register 5 is reset to “1” data.
[0028]
Next, in the state where the control signal SE is at the low level, the shift-in data SIN of “0” is output, the data of “0” is stored only in the first register in the shift register of the data register 6 and the test data is set. Thereafter, the shift-in data SIN is set to “1” to complete the test data setting (step S14). Next, the process of step S15 to step S18 which is the same process as step S5 to step S8 is performed.
[0029]
Thereafter, it is checked whether or not the X address has been counted up to the maximum X address value (step S19). If the X address has not been counted up to the maximum X address value (NO), the processing is the same as in steps S10 and S11. After performing steps S20 and S21, the process returns to step S15. If the count has been counted up to the maximum X address value in step S19 (YES), this flow ends. In the above flow, the RAM whose X address or Y address exceeds the valid value is deactivated by the chip enable control circuit unit 4.
[0030]
As described above, the built-in self-test circuit according to the present embodiment generates the X address of all the RAMs to be tested and generates and outputs the X address register 2 composed of the registers with the up counter, and all the tests to be performed. A Y address register 3 composed of a register with an up-counter that generates and outputs a Y address of the RAM, and a RAM to be tested from the X address and the Y address output from the X address register 2 and the Y address register 3 And a chip enable control circuit unit 4 for generating and outputting an enable signal. As a result, the RAM under test can be tested in parallel with the diagonal pattern, and even when RAMs of different shapes are arranged, the data generation circuit for generating the diagonal pattern can be shared, and the integrated circuit The increase in the area of the BIST circuit occupying the inside can be reduced.
[0031]
【The invention's effect】
As is apparent from the above description, according to the built-in self-test circuit of the present invention, the X address register unit that generates and outputs the X addresses of all the RAMs to be tested and the data generation circuit are tested. Generate and output an enable signal for the RAM to be tested from the Y address register unit that generates and outputs the Y address of all the RAMs, and the X address and Y address output from the X address register unit and the Y address register unit And a chip enable controller for outputting. As a result, the RAM under test can be tested in parallel with the diagonal pattern, and even when RAMs of different shapes are arranged, the data generation circuit for generating the diagonal pattern can be shared, and the integrated circuit The increase in the area of the built-in self-test circuit occupying the inside can be reduced.
[0032]
In addition, since the chip enable control unit outputs a chip enable signal to the RAM of the shape to be tested specified from the input X address and Y address, the RAMs of different shapes are arranged. Even in such a case, the data generation circuit can be shared.
[0033]
Specifically, since the chip enable control unit specifies the shape of the RAM to be tested from the number of bits of the input X address and Y address, it accurately specifies the shape of the RAM to be tested. be able to.
[0034]
In addition, since the X address register unit and the Y address register unit are constituted by registers with an up counter, it is possible to generate an X address and a Y address for a RAM under test having a different configuration with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing an example of a built-in self-test for an integrated circuit according to an embodiment of the present invention.
FIG. 2 is a schematic diagram showing a circuit example of a chip enable control circuit unit 4 in FIG. 1;
FIG. 3 is a flowchart showing an operation example of the sequencer 6 shown in FIG. 1;
4 is a flowchart showing an operation example of the sequencer 6 shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Data generation circuit 2 X address register 3 Y address register 4 Chip enable control circuit part 5 Data register 6 Sequencer 11 Comparison reference value generation circuit X1-Xk X address comparator Y1-Yk Y address comparator N1-Nk NOR circuit

Claims (2)

In a built-in self-test circuit in an integrated circuit, comprising a data generation circuit for supplying a diagonal pattern to a RAM, which is a device under test in the integrated circuit,
The data generation circuit
An X address register unit for generating and outputting X addresses of all RAMs to be tested;
A Y address register unit for generating and outputting Y addresses of all RAMs to be tested;
A chip enable control unit that generates and outputs an enable signal to the RAM to be tested from the X address and the Y address output from the X address register unit and the Y address register unit;
A data register section composed of a shift register that generates and outputs test data for all RAMs to be tested;
A control unit for controlling operations of the X address register unit, the Y address register unit, and the data register unit;
Equipped with a,
The chip enable control unit compares the number of bits of the X address and Y address output from the X address register unit and the Y address register unit with a corresponding comparison reference value set in advance, and performs a test of the RAM for performing the test. A built-in self-test circuit characterized by specifying a shape and generating and outputting an enable signal to the RAM of the specified shape . 2. The built-in self-test circuit according to claim 1, wherein each of the X address register unit and the Y address register unit includes a register with an up counter .

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