JPH05151017A - Microcomputer - Google Patents

Abstract

PURPOSE:To properly perform a function test of unit such as each macro block in the microcomputer with simple control without increasing the number of external terminals exclusive for test. CONSTITUTION:At the time of test, a macro selection signal is outputted from a test circuit 60, and one of a CPU core 31, peripheral function macro 32 to 34, or RAM macro 35 is selected for test. The test pattern is supplied from the test circuit 60 to the block for test through a test bus 70. through which the block for test executes tests according to the test pattern. The result of the test is returned through the test bus 70 to the test circuit 60. In the text circuit 60, the test result and the expected valve sent from the test bus 70 are compared to be discriminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer having a CPU core inside, and more particularly to a test circuit therefor.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there is one described in JP-A-2-289999. Conventionally, by connecting each layout data of a functional block including a central processing unit (CPU) and various peripheral hardware, a memory block, and a functional block including a user-defined circuit on a computer, a microcomputer is developed. , A technology for shortening the development period has been proposed. In this case, it is a serious problem to test the microcomputer promptly and accurately. An example of the configuration of such a microcomputer is shown in FIG.

FIG. 2 is a block diagram showing the configuration of the conventional microcomputer described in the above document. This microcomputer 10 is composed of one chip,
CPU for program control of the entire microcomputer
And CPU core 11 having a bus interface circuit
And peripheral function macro 1 for controlling various external devices
2 to 14 and a random access memory macro (RAM macro) 15 capable of reading and writing data, which are connected to each other via an upper address bus 16, a lower address bus 17, and a data bus 18. ing. The CPU core 11 supplies a memory read signal 19 and a memory write signal 20 to the RAM micro 15 in order to test the RAM macro 15. Each of the peripheral function macros 12 to 14 has external first, second, and second interfaces for interfacing with external devices.
It is connected to the third terminal groups 21 to 23.

The microcomputer 1 having such a configuration
0, for example, when testing a RAM cell in the RAM macro 15, the bus interface circuit in the CPU core 11 is activated using an instruction included in the CPU core 11,
Do the test. That is, when performing the data read test of the RAM macro 15, the CPU core 11 outputs a predetermined address to the upper address bus 16 and the lower address bus 17 to make the data bus 18 high impedance. Then, the memory read signal 19 is output to output the RAM macro 15
Read the data in. When performing a data write test on the RAM macro 15, the CPU core 11 outputs a predetermined address to the upper address bus 16 and the lower address bus 17, and outputs write data to the data bus 18. Then, the memory write signal 20 is sent to the RAM macro 1
It outputs to 5 and the writing test is done.

In this type of microcomputer 10,
Since the RAM macro 15 is tested using the CPU function, if the function of the CPU core 11 is broken, the function of the RAM macro 15 is not confirmed or the CPU core 11 is broken. There is a drawback that it cannot be determined whether or not the RAM macro 15 has failed.

Therefore, in the technique of the above-mentioned document, a test terminal dedicated to the RAM macro is provided outside, and a read signal and a write signal are input to the test terminal to perform a read operation and a write operation to the RAM macro 15. address,
Data and control signals are sent to the first, second, and third terminal groups 21 to 21.
23 and the peripheral function macros 12 to 14 through the upper address bus 16, the lower address bus 17, and the data bus 18.
The RAM macro 15 is tested without operating the CPU core 11 by inputting and outputting the RAM macro 15. As a result, the RAM macro 15 can be tested regardless of whether the operation of the CPU core 11 is normal.

[0007]

However, in the microcomputer 10 having the above-described structure, an external test terminal dedicated to the RAM macro is provided, and the test terminal is used for the R test.
Since the AM macro 15 can be tested, the RAM
Although the test of the macro 15 is easy, the test of the other CPU cores 11 and the peripheral function macros 12 to 14 is not considered at all. Therefore, C
When performing a test on the PU core 11 and the peripheral function macros 12 to 14, it is conceivable to provide an external terminal dedicated to the test for them and input a test signal from the external terminal to perform the test. But in this way,
There is a drawback that the number of external terminals dedicated to testing increases.
Therefore, it is possible to test the CPU core 11 and the peripheral device macros 12 to 14 by inputting a test signal by using the first to third terminal groups 21 to 23. Control becomes complicated. Therefore, the CPU can be easily controlled without increasing the number of external terminals dedicated to the test.
It was difficult to perform a complete functional test of the core 11 and each macro block.

The present invention has the problem that the above-mentioned conventional technique has a function test of each microblock in a microcomputer completely by simple control without increasing the number of external terminals dedicated to the test. The present invention provides a microcomputer that solves the above problems.

[0009]

In order to solve the above-mentioned problems, a first invention is a CPU core having a CPU for program-controlling the entire microcomputer, and the above-mentioned CPU.
A plurality of macroblocks controlled by the above and executing the above-mentioned program are provided in a microcomputer mounted in one chip, and the following means are provided. That is, in the first aspect of the invention, a plurality of input / output control means for controlling the input / output of each of the CPU core and the plurality of macroblocks based on the macro selection signal, and the above-mentioned A test bus commonly connected to the CPU core and the plurality of macro blocks;
A test circuit which is connected to the test bus, outputs the macro selection signal, selects one of the CPU core and the macro block, and supplies a test pattern to the test target to execute the test; It is provided in the one chip.

According to a second aspect of the invention, the input / output control means of the first aspect comprises a multiplexer for selecting an input by the macro selection signal and an output gate for controlling the output. Further, the test circuit includes a macro selection signal generating means for generating the macro selection signal, a test pattern generator for generating the test pattern, and a determination means for comparing and determining a test result from the test target and an expected value. Have

[0011]

According to the first aspect of the invention, since the microcomputer is configured as described above, the test circuit outputs the macro selection signal during the test, and the CP is sent via the test bus.
It is given to each input / output control means in the U core and the macro block. Then, one of the CPU cores or macro blocks to be tested is selected by these input / output control means. Then, a test pattern is generated from the test circuit, and the test pattern is sent to the block to be tested via the test bus. The block to be tested executes a test based on the test pattern and returns the test result to the test circuit via the test bus. The test circuit determines whether the sent test result matches the expected value or not, and determines whether the test target is good or bad.

In the second invention, the macro selection signal is output from the macro selection signal generating means in the test circuit, and the test is performed by the multiplexer and the output gate in the input / output means provided for the test subject by the macro selection signal. Input / output of the target test is controlled. When a test pattern is generated from the test pattern generator in the test circuit, the test pattern is sent to the block to be tested through the multiplexer in the input / output control means, the block is tested, and the test is performed. The result is sent to the test bus via the output gate. The test result sent from the test bus is compared and judged with the expected value by the judging means in the test circuit. As a result, the functional test of each block can be accurately performed with simple control without increasing the number of external terminals dedicated to the test. Therefore, the above problem can be solved.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a microcomputer showing an embodiment of the present invention. This microcomputer 30 is composed of one chip as in the conventional case, and has a CPU and a bus interface circuit.
The core 31 and a plurality of macro blocks having various functions, for example, peripheral function macros 32 to 34 for controlling external devices.
And a RAM macro 35 for storing data, which are connected to each other by an upper address bus 36, a lower address bus 37 and a data bus 38.

Each of the peripheral function macros 32 to 34 has a different function for controlling an external device, and each of them has an external first and an external function for interfacing with an external device.
The second and third terminal groups 41 to 43 are connected to each other. Each of these peripheral function macros 32 to 34 has a mode register, a latch, etc., which are mapped to a predetermined address, and the CP via the lower address bus 37.
An address is given from the U core 31, and data is exchanged with the CPU core 31 via the data bus 38. The RAM macro 35 is connected to the CPU core 31 via an upper address bus 36, a lower address bus 37, and a data bus 38, and the CPU core 31 controls writing and reading of data.

In the microcomputer 30 of the present embodiment, a control signal input terminal 51 for starting and a test result output terminal 52 for testing the CPU core 31, the peripheral function macros 32 to 34, and the RAM macro 35 are provided. , And a test circuit 60 are provided. External input terminal 51
The test circuit 60 connected to the output terminal 52 is connected to the CPU core 31 and the peripheral function macro 3 via the test bus 70.
2 to 34 and the RAM macro 35, respectively. In this test circuit 60, when a control signal for starting a test is input from the input terminal 51, the test bus 70
It has a function of selecting a macro block to be tested via the, and supplying a test pattern to the selected macro block to execute the test.

FIG. 3 is a block diagram showing a configuration example of the test circuit shown in FIG. The test circuit 60 has a control circuit 61 that generates various control signals for controlling the entire test circuit when a control signal for activation or the like is input from the input terminal 51. The control circuit 6
On the output side of 1, a macro selection signal generating means (for example, an encoder) 62 for selecting a macro block to be tested, a test pattern generator 63 for generating a test pattern of each macro block, and a test target A determination unit (for example, a comparator) 64 that compares the test result with the expected value and outputs the determination result from the output terminal 52 is connected.

Further, the output side of the control circuit 61 is connected to gates 65 to 67 whose opening / closing is controlled by the output of the control circuit 61. Gate 65
Is a macro selection signal BS output from the encoder 62.
Is output to the test bus 70 via the macro selection output terminal 68. The gate 66 has a function of outputting the test pattern generated from the test pattern generator 63 to the test bus 70 via the data output terminal 69. Further, the gate 67 has a data output terminal 69.
It has a function of sending the input from the comparator to the comparator 64.

The CPU core 31, the peripheral function macros 32 to 34, and the RA in the microcomputer 30 shown in FIG.
Input / output control means for controlling the input / output of each of these macro blocks based on the macro selection signal BS output from the test circuit 60 is provided on the input / output side of the M macro 35. Is shown in FIG.

FIG. 4 is a configuration block diagram of the input / output control means provided in, for example, the CPU core 31 in FIG.
The multiplexer 81 is connected to the input side and the output gate 82 is connected to the output side of the CPU core body 80 in the CPU core 31, and the multiplexer 81 and the output gate 82 are connected.
The input / output control means is constituted by. The multiplexer 81 is connected to the data bus 38 and the test bus 70 on its input side, and is further connected to the input side of the CPU core body 80 on its output side. The multiplexer 81 outputs the multiplexer based on the macro selection signal BS sent from the test bus 70. It has a function of selecting an input of the test bus 70 and giving it to the CPU core body 80. The output gate 82 is connected between the output side of the CPU core body 80 and the test bus 70.
0 based on the macro selection signal BS sent from 0
It has a function of outputting the output of the U core body 80 to the test bus 70.

Such input / output control means is provided on each input / output side of the peripheral function macros 32 to 34 and the RAM macro 35 shown in FIG. The operation of the microcomputer 30 configured as above will be described. First, in normal operation of the microcomputer 30 of FIG.
The U core 31 decodes the program, performs arithmetic processing and the like using the RAM macro 35 based on the decoding result, and gives the arithmetic result and the like to the peripheral function macros 32 to 34. Then, in the peripheral function macros 32 to 34, based on the control from the CPU core 31, the first to third terminal groups 41 to 41.
An external device is controlled via 43.

Next, the test operation for each macroblock in the microcomputer 30 will be described. For example,
When testing the CPU core 31, a control signal for activating a test circuit is input from an external input terminal 51 of the microcomputer 30. Then, the test circuit 60 of FIG.
The control circuit 61 therein operates to generate various control signals for controlling the entire test circuit. The encoder 62 encodes the control signal from the control circuit 61 and generates a macro selection signal BS for selecting the CPU core 31. This macro selection signal BS is applied to the gate 6
5 and the macro selection output terminal 68
To the macro selection signal BS on the test bus 70.
Is a CPU core 31, peripheral function macros 32 to 34, and R
It is sent to the AM macro 35.

In the CPU core 31 of FIG. 4, since the multiplexer 81 selects the test bus 70 side, it is possible to input to the CPU core body 80 through the test bus 70. Other peripheral function macros 32 to 34 and RAM macro 3
In 5, the input from the test bus 70 becomes impossible.

Next, in the test circuit 60 of FIG. 3, the test pattern generator 63 generates a test pattern for the CPU core 31. This test pattern is output to the test bus 70 via the gate 66 and the data output terminal 69 and sent to the CPU core 31. CPU core 31 of FIG.
Then, the test pattern sent from the test bus 70 is input to the CPU core body 80 via the multiplexer 81 to execute the test. The test result of the CPU core body 80 is transferred to the test bus 70 via the output gate 82.
Is output to the test circuit 60.

In the test circuit 60 of FIG. 3, the test bus 7
The test result sent from 0 through the data input terminal 69 and the gate 67 is input to the comparator 64, and the comparator 6
In step 4, the test result and the expected value are compared / unmatched, and the judgment result is output from the output terminal 52 to the outside of the microcomputer. By repeating such a sequence, the test for the CPU core 31 is completed.

Other peripheral function macros 32 to 34 and RAM
The test for the macro 35 is performed in the same manner as described above. As described above, in this embodiment, the microcomputer 30 is provided with the test input terminal 51 and the output terminal 52 outside, and the test circuit 60, the test bus 70, and the input / output control means are provided inside the microcomputer 30. Since the control signal for activation is input from the input terminal 51, the CPU core 31 and the peripheral function macro 3 are provided.
2-34, or test the RAM macro 35,
The test result can be output from the output terminal 52 to the outside. Therefore, the control for the test is simple, and the external terminals dedicated to the test are the input terminal 51 and the output terminal 5.
There are only two, and the CPU core 31 can be easily controlled without increasing the number of external terminals dedicated to the test so much.
It is possible to accurately perform a functional test of each of the macroblocks and to improve the failure detection rate of the microcomputer 30.

Further, as in the conventional case, a test signal is externally input into the microcomputer 30 using the first to third terminal groups 41 to 43 and the like, and the peripheral function macro is used by using the CPU function of the CPU core 31. 32-34 and RAM macro 3
It is also possible to perform the test of 5.

The present invention is not limited to the above embodiment, but various modifications can be made. Examples of such modifications include the following. (A) In FIG. 1, the test input terminal 51 and the output terminal 52 are provided outside the microcomputer 30.
If there is an existing terminal for starting the PU core 31, etc.,
It is also possible to use them. Although the test input terminal 51 is provided outside the microcomputer 30, the test input terminal 51 may be omitted and the test circuit 60 may be activated by a control signal from the CPU core 31.

(B) In FIG. 1, the test input bus and the test result bus are constituted by one test bus 70, but two test input buses and test result buses may be provided.

(C) The test circuit 60 shown in FIG. 3 can be changed to another circuit configuration, for example, by configuring the encoder 62 with another macro selection signal generating means. (D) The input / output control means shown in FIG.
1. The peripheral function macros 32 to 34 and the RAM macro 35 are provided inside, but they may be provided outside thereof, and the multiplexer 31 and the output gate 82 are provided in advance in these macro blocks. However, it is possible to use them. Further, the input / output control means can be configured by circuits other than the multiplexer 81 and the output gate 82.

(E) In the microcomputer 30 shown in FIG. 1, it is possible to provide other macroblocks or the like as needed.

[0031]

As described in detail above, according to the first invention, a plurality of input / output control means, a test bus, and a test circuit are provided inside the microcomputer.
The test circuit allows the C in the microcomputer to
A PU core or an arbitrary block of a plurality of macroblocks can be tested. Therefore, the function test of the single unit in the microcomputer can be accurately performed with simple control without increasing the number of external terminals dedicated to the test so much, and the failure detection rate of the microcomputer can be improved.

According to the second aspect of the invention, since the input / output control means is composed of the multiplexer and the output gate, the test input / output of the block to be tested can be easily performed by the macro selection signal. Further, since the test circuit has the macro selection signal generating means, the test pattern generating circuit, and the judging means, the macro selection signal generating means outputs the macro selection signal by activating the test circuit. A block to be tested is selected by the macro selection signal, a test pattern is supplied to the block from the test pattern generator, the test of the test target is performed, and the test results are compared and judged by the judging means. Therefore, the test of each block can be accurately executed with simple control.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a microcomputer showing an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional microcomputer.

3 is a configuration block diagram of a test circuit in FIG.

4 is a configuration block diagram of an input / output control unit provided in a microcomputer 30 in FIG.

[Explanation of symbols]

 30 Microcomputer 31 CPU Core 32-34 Peripheral Function Macro 35 RAM Macro 51 Input Terminal 52 Output Terminal 60 Test Circuit 61 Control Circuit 62 Encoder 63 Test Pattern Generator 64 Comparator 70 Test Bus 81 Multiplexer 82 Output Gate

Claims (2)

[Claims] 1. A microcomputer in which a CPU core having a central processing unit for program controlling the entire microcomputer and a plurality of macroblocks controlled by the central processing unit to execute the program are mounted in one chip. A plurality of input / output control means for controlling the input / output of each of the CPU core and the plurality of macro blocks based on a macro selection signal, and the CPU core and the plurality of macros via the respective input / output control means. A test bus that is commonly connected to each block and a test bus that is connected to the test bus and outputs the macro selection signal to select one of the CPU core and the macro block and supply a test pattern to the test target. And a test circuit for executing a test are provided in the one chip. The microcomputer according to claim. 2. The microcomputer according to claim 1, wherein the input / output control unit includes a multiplexer that selects an input according to the macro selection signal and an output gate that controls an output, and the test circuit includes: A micro selection signal generating means for generating the macro selection signal, a test pattern generator for generating the test pattern, and a determination means for comparing and determining a test result from the test target and an expected value. Computer.