JP2002365337A - Test circuit and digital circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test circuit capable of ensuring the safety of confidential data within a digital circuit, even when boundary scan is used. SOLUTION: The boundary scan is formed by scan resistors CEL- 11-14. Selectors SEL- 1-4 are interposed between scan resistors CEL- 11-CEL- 14 and internal resistors REG- A1, B1, C1, 11, 12, and 13, respectively. The selectors SEL-1 1-4 switch the connecting state between the scan resistors and the internal resistors, on the basis of a switching control signal S72 from a switching control circuit 72.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a test circuit using a boundary scan which can prevent confidential internal data from being illegally monitored and tampered with, and a digital circuit including the test circuit.

[0002]

2. Description of the Related Art JTAG (Joint Tes
t Action Group). In a digital circuit employing such a JTAG, a test method called a boundary scan is used at the time of system development or failure point diagnosis. This test method uses CSP (Chip Size
This is effective for digital circuits having a package that is difficult to inspect with a probe such as a package.

FIG. 5 is an example of a configuration diagram of a conventional digital circuit 51 employing JTAG. As shown in FIG.
The digital circuit 51 includes TDI (Test Data In), TDO (Test Data Out), called TAP (Test Access Port).
It has five terminals: TMS (Test Mode Select), TCK (Test Clock) and TRST (Test ReSeT).

In the digital circuit 51, for example,
External terminals ET_1 and ET_2 and an internal register REG
_A, REG_B, and REG_C are respectively provided with scan registers CEL_1 and CER_2 called boundary scan cells, which function equivalently to a test probe. In the digital circuit 51, for example, between the external terminals ET_3 and ET_4 and the internal registers REG_1, REG_2 and REG_3,
Scan registers CEL_3 and CEL_ which are the above cells
4 are provided respectively. The scan registers CEL_1 to CEL_4 are connected in series to form a shift register that performs boundary scan.

[0005] In the digital circuit 51, a TAP controller 60 is provided. The TAP controller 60 determines whether the TMS signal input from the TMS terminal
Scan registers CEL_1 to CEL_1 forming a boundary scan in accordance with the TCK signal input from the K terminal
This is a 16-state machine (sequential circuit) that controls EL_4. The TAP controller 60 executes a test in response to a test code input and a corresponding response. A digital processing circuit 61 is provided in the digital circuit 51. The digital processing circuit 61 includes a register R
Using EG_A to REG_C and REG_1 to REG_3, a predetermined process such as a personal authentication process is performed.

In the digital circuit 51, for example, at the time of system development or failure diagnosis, a test using the above-described boundary scan is performed.

[0007]

When the digital circuit 51 performs processing such as personal authentication processing, for example, the internal registers REG_A and REG are used.
_B, REG_C, REG_1, REG_2, REG_
3 stores confidential data such as personal ID information and passwords. However, in the above-described digital circuit 51, if the test operation using the boundary scan is illegally started after shipment, the external terminal ET_1
There is a problem that confidential data stored in a register in the digital circuit 51 may be illegally acquired and falsified from outside the digital circuit 51 through ＥＴET_4.

[0008] The present invention has been made in view of the above-mentioned problems of the prior art, and even when a boundary scan is used,
It is an object of the present invention to provide a test circuit capable of securing the security of confidential data in a digital circuit, and a digital circuit using the test circuit.

[0009]

In order to solve the above-mentioned problems of the prior art and to achieve the above-mentioned object, a test circuit according to the first invention is provided in a digital circuit for performing predetermined digital processing. A first register for storing data used for the digital processing;
A plurality of second registers interposed between a first external terminal for inputting or outputting data related to the digital processing and connected in series to form a shift register; and a plurality of second registers connected to one end of the shift register. A second external terminal for inputting test data to a second register, a third external terminal for outputting test result data from the second register located at the other end of the shift register, and an operation of the shift register Test control means for controlling the first register and the second register, and connecting and disconnecting the first register and the second register based on a switching signal. There are switching means for setting any one of the states, and switching control means for generating the switching signal.

The operation of the test circuit according to the first invention is as follows. In the test circuit according to the first invention, when the first register and the second register are connected by the switch based on the switching signal generated by the switching controller, the second external Via the terminal and the third external terminal, access and monitoring of the second register is enabled. The state can be set only by a user having a predetermined authority, and is used by a user having a predetermined authority, for example, at the time of system development or failure diagnosis. In the test circuit according to the first aspect of the present invention, when the first register and the second register are set to a non-connection state by a switch, access to the second register from outside the digital circuit is performed. And monitoring becomes possible. Such a state is set, for example, when the end user uses the test circuit after shipping the test circuit.

Further, in the test circuit according to the first invention, preferably, the switching control means includes a switch switching control data stored in a storage means in the digital circuit.
The switching signal is generated.

Further, in the test circuit according to the first aspect of the present invention, preferably, the digital processing is processing with confidentiality.
The storage unit stores confidential data.

In the test circuit according to the first aspect of the present invention, preferably, the switch means includes:
When a person having a predetermined authority uses the digital circuit, the first register and the second register are set to a connection state. Otherwise, the first register and the second register are connected to each other. The register is set to a non-connection state.

Further, a digital circuit according to a second aspect of the present invention includes a digital processing circuit for performing predetermined digital processing, a first register for storing data used in the digital processing, A digital circuit having a first external terminal for outputting and a test circuit for performing a test process of the digital processing circuit, wherein the test circuit includes the first register and the first register.
And a plurality of second registers connected in series to form a shift register, and a second register for inputting test data to the second register located at one end of the shift register. An external terminal, a third external terminal for outputting test result data from the second register located at the other end of the shift register, test control means for controlling an operation of the shift register, and the first register A switch unit interposed between the first register and the second register to set the first register and the second register to one of a connected state and a non-connected state based on a switching signal; Switching control means for generating a switching signal.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an example of a configuration diagram of a digital circuit 1 of the present embodiment employing JTAG. As shown in FIG. 1, the digital circuit 1 has an external terminal ET_1.
1, ET_12, ET_13, ET_14 (first external terminal of the present invention). In addition, digital circuit 1
Are TDI (second external terminal of the present invention), TDO (third external terminal of the present invention), TMS, T
It has five terminals CK and TRST. TDI
The terminal serially inputs a TDI signal indicating an instruction or data to a test logic circuit such as a boundary scan, and samples the TDI signal at a rising edge of the TCK signal. The TDO terminal outputs a TDO signal indicating test result data from the test logic circuit.
The value indicated by the O signal is updated at the falling edge of the TCK signal. The TCK terminal inputs a clock signal to be supplied to the test logic circuit. The TMS terminal inputs a TMS signal that defines a mode for controlling the test operation. The TMS
The signal is supplied to the TAP controller 70 and decoded by the TAP controller 70. TRST terminal is T
A TRST signal for asynchronously initializing the AP controller 70 (test control circuit of the present invention) is input.

In the digital circuit 1, for example, external terminals ET_11 and ET_12 and an internal register RE
A scan register CEL called a boundary scan cell which functions equivalently to a test probe between G_A1 and REG_C1 (first register of the present invention).
_11 and CEL_12 (the second register of the present invention) are provided. In the digital circuit 1,
For example, between the external terminals ET_13 and ET_14 and the internal registers REG_11 and REG_13 (the first register of the present invention), the scan register C, which is the above cell, is provided.
EL_13, CEL_14 (second register of the present invention)
Are arranged respectively. The scan registers CEL_ <b> 11 to CEL_ <b> 14 are connected in series to constitute a shift register that performs a boundary scan. The operation of the scan registers CEL_1 to CEL_14 is controlled by a test control signal generated by the TAP controller 70 based on the TMS signal.

In the digital circuit 1, a TAP controller 70 is provided. TAP controller 7
0 is the TMS signal input from the TMS terminal and TCK
The TCK signal input from the terminal
Scan registers CEL11-CE constituting scan
It is a 16-state machine (sequential circuit) that controls L_14. The TAP controller 70 generates a test control signal based on the TMS signal input via the TMS terminal,
The test control signal is transmitted to the scan registers CEL_11 to CEL_11.
Output to CEL_14 and scan register CEL_11
To CEL_14.

The TAP controller 70 performs a test operation at the time of system development, failure diagnosis, or the like, and converts test input data defined by a TDI signal input via a TDI terminal into a scan register CEL_11 at one end of a boundary scan. And serially outputs the test result data that has reached the scan register CEL_14 at the other end of the boundary scan as a TDO signal from the TDO terminal by the shift operation of the boundary scan. The TAP controller 70 does not perform, for example, the shift operation of the boundary scan during the normal operation.

In the digital circuit 1, the selector SEL_1 is interposed between the scan register CEL_11 and the register REG_C1, the selector SEL_2 is interposed between the scan register CEL_12 and the register REG_A1, and the scan register CEL_13 and the register REG are interposed.
The selector SEL_3 intervenes between the scan register CEL_14 and the register REG_13. Here, the selectors SEL_1 to SEL_4 correspond to the switch means of the present invention.

The selector SEL_1 includes a switching control circuit 72
Switching control signal S72 from (switching control means of the present invention)
When the (switching signal of the present invention) indicates a logical value “1”, the data of the scan register CEL_11 is stored in the register REG.
_C1 is set to be writable. Further, when the switching control signal S72 from the switching control circuit 72 indicates the logical value “0”, the selector SEL_1 can write fixed-value data of the logical value “1” or “0” to the register REG_C1. It is set as follows. Selector SEL_2
Indicates that the scan register CEL_12 is set when the switching control signal S72 from the switching control circuit 72 indicates a logical value “1”.
Is set to be able to write the data in the register REG_A1. When the switching control signal S72 from the switching control circuit 72 indicates a logical value “0”, the selector SEL_2 can write fixed-value data of a logical value “1” or “0” to the register REG_A1. It is set as follows.

The selector SEL_3 includes a switching control circuit 72
Is set so that the data of the register REG_11 can be read out to the scan register CEL_13 when the switching control signal S72 from the CPU 1 indicates the logical value “1”.
Further, when the switching control signal S72 from the switching control circuit 72 indicates the logical value “0”, the selector SEL_3 can read data of a fixed value of the logical value “1” or “0” into the scan register CEL_13. It is set as follows. The selector SEL_4 converts the data in the register REG_13 into the scan register CEL_1 when the switching control signal S72 from the switching control circuit 72 indicates a logical value “1”.
4 is set to be readable. In addition, when the switching control signal S72 from the switching control circuit 72 indicates a logical value “0”, the selector SEL_4 outputs the fixed value data of the logical value “1” or “0” to the scan register CEL.
_14 is set to be readable.

The switching control circuit 72 includes, for example, a register R
When the switching control data stored in EG_SET indicates a logical value “1” (first logical value), a switching control signal S72 indicating a logical value “1” is generated, and this is selected by a selector SE.
Output to L_1 to SEL_4. Further, the switching control circuit 7
For example, when the switching control data stored in the register REG_SET indicates the logical value “0” (second logical value), the switching control signal S72 indicating the logical value “0” is generated, and this is selected by the selector. Output to SEL_1 to SEL_4.

Register REG_SET, Register REG
_A1, REG_B1, REG_C1, REG_11,
REG_12 and REG_13 are registers whose access is restricted by a predetermined security function, and can be accessed only by a user having a predetermined authority at a system development stage or at the time of failure diagnosis. Further, the switching control data may be written in the register REG_SET in an initial sequence after the power of the digital circuit 1 is turned on.

In the digital circuit 1, a digital processing circuit 71 (digital processing circuit of the present invention) is provided. The digital processing circuit 71 includes a register REG_A1
Using REG_C1 and REG_11 to REG_13, predetermined processing such as personal authentication processing and charging processing is performed.

Hereinafter, the operation of the digital circuit 1 shown in FIG. 1 will be described separately for a test operation and a normal operation. [Action During Valid Test Operation] The test operation is performed at the system development stage or at the time of failure diagnosis. FIG. 2 is a flowchart for explaining the operation of the digital circuit 1 shown in FIG. 1 during a valid test operation. Step ST1: A user having a predetermined authority such as a system developer or a failure diagnosis person sets the switching control data of the register REG_SET to a logical value “1”, for example, through a predetermined authentication process.

Step ST2: The switching control circuit 72 outputs a switching control signal S72 indicating a logical value “1” based on the switching control data stored in the register REG_SET.
Is generated, and the switching control signal S72 is supplied to the selector SEL.
_1 to SEL_4. Thereby, the selectors SEL_1 to SEL_4 respectively change the scan registers CEL_1 to CEL_11 based on the switching control signal S72.
The path of _14 is set to the connected state (selected).

Step ST3: TAP controller 70
Performs a test operation, and receives the T input through the TDI terminal.
The test input data defined by the DI signal is transferred to the scan register CEL_1 at one end of the boundary scan.
1 is serially supplied, and by a boundary scan shift operation, control is performed to serially output test result data as a TDO signal from a TDO terminal to a scan register CEL_14 at the other end of the boundary scan. This makes it possible to access the register inside the digital circuit 1 using the boundary scan at the time of system development or the like.

[Operation in Normal Operation] The normal operation is performed, for example, when the digital circuit 1 is provided to an end user. FIG. 3 is a flowchart for explaining the operation of the digital circuit shown in FIG. 1 during normal operation. Step ST11: Before providing the digital circuit 1 to the end user, a user having a predetermined authority sets the switching control data of the register REG_SET to a logical value “0” through, for example, a predetermined authentication process. Then, the digital circuit 1 is provided to the end user.

Step ST12: The switching control circuit 72 outputs a switching control signal S72 indicating a logical value "0" based on the switching control data stored in the register REG_SET.
Is generated, and the switching control signal S72 is supplied to the selector SEL.
_1 to SEL_4. As a result, the selectors SEL_1 to SEL_4 select data indicating a fixed value of the logical value “1” or “0”, respectively, based on the switching control signal S72. Thereby, the external terminal ET_11
ET_14 and registers REG_C1, REG_A
1, REG_11 and REG_13 are in a disconnected state.

Step ST3: TAP controller 70
Does not perform the boundary scan shift operation, for example. Further, the digital processing circuit 71 includes a register REG.
_A1, REG_B1, REG_C1, REG_11,
A predetermined authentication process is performed using REG_12 and REG_13.

In the digital circuit 1 described above, after shipment, the switching control data of the register REG_SET is set to the logical value “0”, and the selectors SEL_1 to SEL_SEL are set.
_4 selects a fixed value, the scan registers CEL_11, CEL_12, CEL_13, CE
L_14 and registers REG_C1, REG_A1, R
EG_11 and REG_13 are disconnected. Therefore, the end user can use the external terminals ET_1 to ET_1.
4, registers REG_C1, REG_A1, R
EG_11 and REG_13 cannot be illegally accessed. Therefore, according to the digital circuit 1, even when boundary scanning is used, the security of confidential data in the digital circuit can be ensured, and the digital circuit 1
Can improve the security of processing using.

The present invention is not limited to the above embodiment. In the embodiment described above, as shown in FIG. 1, the scan registers CEL_11, CEL_12, CEL_1
3, CEL_14 and registers REG_C1, REG_
Although the case where the selectors SEL_1, SEL_2, SEL_3, and SEL_4 are provided between A1, REG_11, and REG_13 has been exemplified, the selectors SEL_1 and SEL_
2, SEL_3, SEL_4, switches SW_1, SW_2, SW_3, SW_3 as shown in FIG.
4 may be provided.

In this case, the switch SW_1 connects the scan register CEL_11 and the register REG_C1 when the switching control signal S72 from the switching control circuit 72 indicates a logical value “1”. The switch SW_1 is connected to a switching control signal S7 from the switching control circuit 72.
2 indicates a logical value “0”, the scan register CE
A connection state is established between L_11 and the register REG_C1. In addition, the switch SW_2 sets a connection state between the scan register CEL_12 and the register REG_A1 when the switching control signal S72 from the switching control circuit 72 indicates a logical value “1”. The switch SW_2 sets a connection state between the scan register CEL_12 and the register REG_A1 when the switching control signal S72 from the switching control circuit 72 indicates a logical value “0”.

The switch SW_3 sets the scan register CEL_13 and the register REG when the switching control signal S72 from the switching control circuit 72 indicates a logical value “1”.
_11 is connected. Also, the switch SW_
3 indicates that when the switching control signal S72 from the switching control circuit 72 indicates a logical value “0”, the scan register CEL_1
3 and the register REG_11 are connected. The switch SW_4 sets the connection state between the scan register CEL_14 and the register REG_13 when the switching control signal S72 from the switching control circuit 72 indicates a logical value “1”. The switch SW_4 switches the scan register CEL_14 and the register R when the switching control signal S72 from the switching control circuit 72 indicates a logical value “0”.
A connection state is established with EG_13.

[0035]

As described above, according to the present invention,
A test circuit capable of ensuring the security of confidential data in a digital circuit even when boundary scan is used, and a digital circuit using the test circuit can be provided.

[Brief description of the drawings]

FIG. 1 is an example of a configuration diagram of a digital circuit according to an embodiment of the present invention employing JTAG.

FIG. 2 is a flowchart for explaining the operation of the digital circuit shown in FIG. 1 during a valid test operation;

FIG. 3 is a flowchart for explaining an operation of the digital circuit shown in FIG. 1 during a normal operation;

FIG. 4 is an example of a configuration diagram of a digital circuit according to a modification of the embodiment of the present invention employing JTAG.

FIG. 5 is an example of a configuration diagram of a conventional digital circuit employing JTAG.

[Explanation of symbols]

ET_11, ET_12, ET_13, ET_14 ... external terminals, CEL_11, CEL_12, CEL_13,
CEL_14: scan register, SEL_1, SEL
_2, SEL_3, SEL_4 ... selector, REG_A
1, REG_B1, REG_C1, REG_11, RE
G_12, REG_13, REG_SET ... register,
70: TAP controller, 71: digital processing circuit,
72 switching control circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/16 330 G01R 31/28 G

Claims (8)

[Claims] 1. A test circuit provided in a digital circuit for performing a predetermined digital process, comprising: a first register for storing data used for the digital process; and inputting or outputting data related to the digital process. A plurality of second registers interposed between the first external terminals and connected in series to form a shift register; and inputting test data to the second register located at one end of the shift register. A second external terminal; a third external terminal that outputs test result data from the second register located at the other end of the shift register; a test control unit that controls an operation of the shift register; 1 register and the second register, and connects the first register and the second register to each other based on a switching signal. Test circuit having a switch means for setting either one of the non-connected state, and a switching control means for generating said switching signal. 2. The test circuit according to claim 1, wherein said switching control means generates said switching signal based on switch switching control data stored in a storage means in said digital circuit. 3. The test circuit according to claim 2, wherein the digital processing is confidential processing, and wherein the storage unit stores confidential data. 4. The switch means sets a connection state between the first register and the second register based on the switching signal when a person having a predetermined authority uses the digital circuit. 2. The test circuit according to claim 1, wherein the first register and the second register are set in a disconnected state in other cases. 5. A digital processing circuit for performing predetermined digital processing, a first register for storing data used for the digital processing, a first external terminal for inputting or outputting data related to the digital processing, A test circuit for performing a test process of the digital processing circuit, wherein the test circuit is interposed between the first register and the first external terminal, connected in series, and shifted. A plurality of second registers constituting a register; a second external terminal for inputting test data to the second register located at one end of the shift register; and a second external terminal located at the other end of the shift register. A third external terminal for outputting test result data from a register of the first register, test control means for controlling an operation of the shift register, Switch means interposed between the first register and the second register for setting the first register and the second register to one of a connected state and a non-connected state based on a switching signal; A switching control means for generating the switching signal. 6. The digital circuit according to claim 5, wherein said switching control means generates said switching signal based on switch switching control data stored in storage means in said digital circuit. 7. The digital circuit according to claim 6, wherein said digital processing circuit performs confidential processing, and said storage means stores confidential data. 8. The switch means sets a connection state between the first register and the second register based on the switching signal when a person having predetermined authority uses the digital circuit. 6. The digital circuit according to claim 5, wherein the first register and the second register are set to a non-connection state in other cases.