JP2001141791A - Semiconductor circuit with scan path circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor circuit capable of inspecting a circuit to diagnose a fault by a scan path circuit and preventing estimation of the configuration of a combination logic circuit through the input/output, by compressing or encrypting output data of the scan path circuit. SOLUTION: In this semiconductor circuit, input data are inputted to the scan path circuit with a prescribed mode key data mixed in the input data in scan mode operation, and the mode key data are taken into a mode key circuit embedded in the scan path circuit. In a system mode operation, the mode key data are taken into a mode hold circuit from the mode key circuit, and a mode signal BE is generated according to the mode key data. When the mode key data have a prescribed pattern, the mode signal BE becomes a prescribed set value, and an output signal of the scan path circuit is outputted as it is, in response to the set value. When the mode key data don't have the prescribed pattern, the output signal of the scan path circuit is encrypted and outputted to conceal the output of the scan path circuit, if necessary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit including a digital logic circuit and a scan path circuit, and using the scan path circuit to perform inspection and failure diagnosis of the digital logic circuit.

[0002]

2. Description of the Related Art A scan path circuit is mainly used in a semiconductor circuit for the purpose of facilitating the production of a test pattern for production / shipment inspection of a digital logic circuit and further facilitating a fault diagnosis of a logic circuit. ing. The scan path circuit allows complex circuits to be separated and handled as flip-flops and combinational circuits, facilitating circuit inspection and failure diagnosis. It is widely used in LSIs (Large Scale Integrated Circuits) including large scale sequential circuits.

FIG. 8 shows an example of a semiconductor circuit including a scan path circuit. As shown, this semiconductor circuit includes a combinational logic circuit C81 and a scan path circuit F8.
1, F82. Combination circuit C81
Performs predetermined digital signal processing and logical operation in accordance with input data N _in, and outputs the processing result N _out.

The scan path circuits F81 and F82 are each composed of a plurality of flip-flops, for example. Each of the flip-flops has a scan path enable signal SE and a clock signal CK which are input in common.
Is controlled by The scan path circuit F81 sequentially shifts the input data S _in1 to the output side and outputs an output signal S _out1 . In order to inspect the operation of the combinational logic circuit C81, the scan path circuit F8 is operated in accordance with the input data S _in1.
1, a test pattern is formed, and data of each bit of the test pattern, that is, the scan path circuit F8
1 is transferred to the combinational logic circuit C81, and the data held in each flip-flop constituting
1 is transferred to the scan path circuit F81 and sequentially output to the output side by the scan path circuit F81. The scan path circuit F82 is
It operates in much the same way as 81. Although the number of scan path circuits provided in the combinational logic circuit C81 is two in this example, only one or more scan path circuits can be provided as necessary.

As described above, scan path circuits F81 and F82 are provided in addition to a combinational logic circuit C81 having a predetermined processing function in a semiconductor circuit, and a test pattern is formed by these scan path circuits. Supplied to the combinational logic circuit C81 or
The processing results of 81 are fetched and sequentially output as serial data. For this reason, it is easy to perform a function test and a failure diagnosis of the combinational logic circuit C81 performed before shipment.
Inspection and diagnosis of an LSI having complicated processing functions can be efficiently performed.

[0006]

By the way, in the above-mentioned conventional semiconductor circuit, it is easy to perform reverse engineering using a scan path circuit. Reverse engineering refers to exploring the configuration of a logic circuit inside an LSI based on a real or simulation model of the LSI, which may lead to infringement of intellectual property rights such as imitating a product of another person. For example, in an LSI using a scan path circuit, an arbitrary value can be set in a flip-flop, and the value of the flip-flop can be read freely. Having a configuration, it is possible to easily estimate how it functions. Therefore, in order to prevent reverse engineering, manufacturers who manufacture semiconductor circuits have stopped using scan path circuits or built-in self-tests (BIST:
The disadvantage is that you have to take measures such as relying on Built-in self-test).

FIG. 9 shows an example of a semiconductor circuit having a built-in self-test function. As shown, this semiconductor circuit includes a combinational logic circuit C91 and a pseudo random number generation circuit B.
91, data compression circuit B92 and scan path circuit F9
1, F92. Here, the combinational logic circuit C91 and the scan path circuits F91 and F92 are
It is almost the same as each circuit of the semiconductor circuit shown in FIG. Hereinafter, the pseudo random number generation circuit B91 and the data compression circuit B92 will be described.

The pseudo-random number generation circuit B91 receives the input signal S
_A pseudo-random number sequence is generated according to _in1 and S _in2 , and the generated pseudo-random number sequence is input to scan path circuits F91 and F92. FIG. 10 shows a configuration example of the pseudo random number generation circuit B91. As shown, the pseudo-random number generation circuit B91 includes
It is composed of n (n is a natural number) flip-flops and logic gates connected in series.
The exclusive OR of the output data of the predetermined flip-flop is fed back to the first flip-flop. The pseudo random number generation circuit B91 having such a configuration generates a pseudo random number sequence having a period of (2 ⁿ -1). Data S _in1 and S _in2 input from the outside are input to first and second stage flip-flops F101 and F102 via exclusive OR circuits XOR1 and XOR2, respectively.
In response to these input data, a pseudo random number generation circuit B91
The initial value of the pseudo-random number sequence in which is generated is set. further,
Exclusive OR circuit XOR1, data from the output terminal of XOR2 B _in1, B _in2 are outputted and supplied to the scan path circuits F91, F92, respectively.

The scan path circuits F91 and F92 correspond to the scan path circuits F81 and F81 in the semiconductor circuit of FIG.
As in the case of 82, it is constituted by a plurality of flip-flops each connected in series. The input data is sequentially shifted to the output side by these scan path circuits. The data B _in1 and B _in2 input from the pseudo random number generation circuit B91 are sequentially shifted by the scan path circuits F91 and F92 to form a test pattern. Then, the scan path circuit F91 or F92
Are transferred to the combinational logic circuit C91, predetermined processing is performed in accordance with the test pattern input in the combinational logic circuit C91, and the processing result is transferred to the scan path circuit F91 or F92.

The data compression circuit B92 compresses data input from the scan path circuits F91 and F92,
The compressed data series B _out1 and B _out2 are output. Therefore, an arbitrary value cannot be set in the combinational logic circuit C91 via the scan path circuits F91 and F92, or data cannot be freely read from the scan path circuits F91 and F92, making reverse engineering difficult.

However, the semiconductor circuit having the built-in self-test function has the following problems. First, the test data sequence input to the combinational logic circuit is
Since this is a pseudo-random pattern generated from a pseudo-random number sequence, the failure detection rate is often low. Next, since the output response data series is compressed and output by the data compression circuit, it is difficult to estimate the location of the failure even when the failure is detected. Further, it is difficult to test the peripheral circuit of the core cell. With the progress of the LSI miniaturization process, it has been frequently performed to design a new LSI by combining the former LSI as an existing block called a core cell and combining the core cells. When the built-in self-test circuit is used, a signal input to the core cell is ignored, and thus cannot be used for testing the core cell peripheral circuit. Although a built-in self-inspection circuit can be provided with a scan path mode and the core cell peripheral circuit can be tested in the scan path mode, this cannot be adopted from the viewpoint of preventing reverse engineering.

The present invention has been made in view of the above circumstances, and an object of the present invention is to compress or encrypt output data of a scan path circuit so that circuit inspection and failure diagnosis can be realized by the scan path circuit. Another object of the present invention is to provide a semiconductor circuit capable of preventing the configuration of a combinational logic circuit from being estimated based on its input / output.

[0013]

In order to achieve the above object, a semiconductor circuit according to the present invention comprises a scan path circuit for sequentially shifting input data to an output side, and a test circuit for inputting data from the input data or the scan path circuit. A semiconductor circuit having a functional circuit that performs a predetermined process according to data and outputs a processing result to the scan path circuit, and is incorporated in a predetermined position of the scan path circuit and input to the scan path circuit. A mode key circuit that outputs serial data in parallel, a mode signal generation circuit that performs a predetermined logical operation on output data from the mode key circuit, and outputs a mode signal according to the operation result; In one state, the output data of the scan path circuit is output as it is, and the mode signal is different from the one state. When in the state, performs predetermined processing on the output data of said scan path circuit, and a data conversion circuit that outputs different from input data data.

In the present invention, preferably, the scan path circuit is connected in series between an input terminal and an output terminal, and sequentially transmits data input to the input terminal in response to a common clock signal. The mode key circuit includes a plurality of flip-flops that shift to the output terminal, and the mode key circuit includes a plurality of flip-flops incorporated at predetermined positions of the scan path circuit.

In the present invention, preferably, the mode signal generating circuit includes a data holding circuit for holding output data of the mode key circuit, and a predetermined logical operation on the data held by the data holding circuit. And a logical operation circuit for outputting an operation result as the mode signal. The data holding circuit has a flip-flop for holding output data of the mode key circuit, and operates in the first operation mode. Then, each of the flip-flops holds the output data as it is, and when operating in the second operation mode, each of the flip-flops takes in the output data of the mode key circuit.

Further, in the present invention, preferably, the data conversion circuit performs a logical operation on a plurality of flip-flops connected in series and output data of a predetermined one of the plurality of flip-flops. Do
A feedback circuit for inputting the operation result to the first-stage flip-flop; and when the mode signal is in the one state, the output data of the scan path circuit is output as it is, and the mode signal is different from the one state. An output circuit that outputs a logical operation result of the output data of the scan path circuit and the output data of one of the plurality of flip-flops when in the state.

According to the present invention, a mode key circuit is constituted by a plurality of flip-flops incorporated at predetermined positions of the scan path circuit, and data input to the scan path circuit is taken into the mode key circuit. Input to the mode signal generation circuit. For this reason, the mode key data having a predetermined pattern is input to the mode signal generation circuit by inputting the predetermined mode key data in a mixed manner with the input data of the scan path circuit. The mode signal generation circuit generates a mode signal based on a predetermined logical operation according to data input from the mode key circuit. When the mode key data has a predetermined pattern,
A mode signal in a predetermined state is output by the mode signal generation circuit. The data conversion circuit controls whether to output the output data of the scan path circuit as it is or to output the data converted therefrom in accordance with the mode signal. By the data conversion, for example, data encrypted by exclusive OR of the output data of the scan path circuit and the random number sequence is output.

Therefore, in the semiconductor circuit of the present invention,
Since the output signal of the scan path circuit is converted by the data conversion circuit and, for example, encrypted and output, the output data can be concealed, and it is difficult to estimate the structure of the combinational logic circuit based on the output data. Become. On the other hand, by inputting mode key data having a predetermined pattern to the scan path circuit, the mode signal is set to a predetermined state, and the output data of the scan path circuit is output as it is without being converted. The combinational logic circuit can be inspected based on the output data to diagnose a failure.

[0019]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor circuit according to the present invention. As illustrated, the semiconductor circuit according to the present embodiment includes a combinational logic circuit C11, scan path circuits F11 and F12, an encryption circuit B11, and a mode holding circuit M11.

The combinational logic circuit C11 receives the input data N _in
Performs a predetermined digital signal processing and a logical operation according to, and outputs a processing result N _out . Further, the combinational logic circuit C11 inputs test data from the scan path circuits F11 and F12, performs predetermined processing according to the input test data, and transfers the processing results to the scan path circuits F11 and F12, respectively.

The scan path circuits F11 and F12 are composed of, for example, a plurality of flip-flops connected in series, and sequentially shift input data toward the output side. A test pattern is formed in accordance with the data S _in1 and S _in2 input by these _{scan path} circuits, and the test pattern is transferred to the combinational logic circuit C11. Further, the processing result is input from the combinational logic circuit C11, the respective input data are sequentially shifted, and supplied to the encryption circuit B11 as output data S _out1 and S _out2 .

The scan path circuit F11 or F12
Since they have almost the same configuration, FIG. 2 shows an example of the configuration. As illustrated, the scan path circuit F11 or F12 includes n (n is a natural number) stages of flip-flops (for example, D flip-flops) F21, F22,..., F2n connected in series. . Each flip-flop has a clock signal CK
Controls the operation timing. Furthermore, F2
, F22,..., F2n are provided with selectors S21, S2 respectively.
, S2n are provided.

One input terminal of each selector is connected to the output terminal of the preceding flip-flop, and the other terminal is connected to the output terminal of the combinational logic circuit C11. Note that one input terminal of the first-stage selector S21 is connected to the input terminal of the data S _in. Each selector S2
, S2,..., S2n are scan enable signals S
According to E, any input signal is selected and output. For example, when the semiconductor circuit operates in the system operation mode (signal SE = 0), each selector selects output data from the combinational logic circuit C11 and outputs the data to the flip-flop. On the other hand, when the semiconductor circuit operates in the scan mode (signal SE = 1), each selector except the first stage selects the output data of the preceding flip-flop, and
Selector S21 of stage selects the input data S _in.

Each flip-flop F21, F22,.
The input terminals of F2n are selectors S21, S22,.
n output terminals. Further, the output terminals of the flip-flops F21, F22,..., F2n are respectively connected to the input terminals of the combinational logic circuit C11.

[0025] When operating in scan mode, the scan path circuit F11 or F12 is sequentially input data S _in1 or S _in2 input from the input terminal, shifts the output side. Therefore, the input data S _in1 or S _in2
, A test pattern is formed by the scan path circuit F11 or F12, respectively. When operating in the system mode, the scan path circuits F11 and F12
Is transmitted and received with the combinational logic circuit C11. That is, the test pattern formed in the scan path circuit F12 or F12 is input to the combinational logic circuit C11, and predetermined processing is performed in accordance with the test pattern input by the combinational logic circuit C11. The data is transferred to the circuit F11 or F12. After the system mode operation, when the semiconductor circuit operates again in the scan mode, the data input to the scan path circuits F11 and F12 are sequentially shifted to the output side and supplied to the encryption circuit B11.

As shown in FIG. 3, the encryption circuit B11
N-stage flip-flops F31 and F3 connected in series
, F3n. The input terminal of the first stage flip-flop F31 is an exclusive OR circuit XOR
The input terminal of the flip-flop F32 of the second stage is connected to the output terminal of the exclusive OR circuit XOR32. The data S _out1 from the scan path circuit F11 is input to one input terminal of the exclusive OR circuit XOR31, and the AND gate AN is input to the other input terminal.
The output signal of D31 is input. AND gate AND3
1, a feedback signal is input to one input terminal, and a mode signal BE is input to the other input terminal. Note that the feedback signal input to the AND gate AND31 is generated by an exclusive OR of output signals of a predetermined flip-flop.
The data S _out2 from the scan path circuit F12 is input to one input terminal of the exclusive OR circuit XOR32, and the output signal of the AND gate AND32 is input to the other input terminal. The output signal of the first-stage flip-flop F31 is input to one input terminal of the AND gate AND32, and the mode signal BE is input to the other input terminal.

Exclusive OR circuits XOR31 and XOR3
2 from the output terminal of each of the encrypted signals (hereinafter, referred to as “encrypted signals”).
B _out1 and B _{out2 (} referred to simply as encrypted signals for convenience) are output. Therefore, the encrypted signals B _out1 and B _out2 are output from the _{scan path} circuits F11 and F12 by the output signals S _out1 and S _out2.
Are the results of the exclusive OR operation with the pseudo-random number sequence, respectively.

The output signals B _out1 and B _out2 are controlled by the encryption circuit B11 according to the mode signal BE. For example, when the mode signal BE = 0, the signal B _out1
Are the output signal S _{out1 of the scan path} circuit F11 and the signal B
_out2 is the output signal _Sout2 of the _{scan path} circuit F12 is output as it is. On the other hand, mode signal BE = 1
, F3, F32,..., F3n
A signal obtained by encrypting the output signals S _out1 and S _{out2 of the scan path} circuits F11 and F12 is output by an LFSR (linear feedback shift register) configured by an exclusive OR circuit.

Next, a circuit for generating the mode signal BE will be described. The mode signal BE is supplied to the scan path circuit F1.
1, a mode key circuit MK11 incorporated in F12
And a mode holding circuit M11 shown in FIG. 4 and 5 show the mode key circuit MK, respectively.
11 and the configuration of a mode holding circuit M11.

As shown in FIG. 4, the mode key circuit MK1
Reference numeral 1 denotes a plurality of flip-flops and a selector provided on the input side of each flip-flop. Here, a mode key circuit MK11 including six flip-flops F41, F42,..., F46 will be described as an example for convenience of description.

The flip-flops F41, F42, F43
Are embedded in arbitrary portions of the scan path circuit F11 shown in FIG.
5 and F46 are embedded in arbitrary portions of the scan path circuit F12. One input terminal of the selector S41 is connected to the output terminal of the preceding flip-flop, and the other input terminal (inverting input terminal) is connected to the output terminal of the flip-flop F41. Selector S41
Is connected to the data input terminal of the flip-flop F41.

The selector S41 selects an input signal according to the scan enable signal SE and outputs it to the flip-flop F41. For example, when the semiconductor circuit operates in the scan operation mode (SE = 1), the selector S41
Selects the output signal of the previous stage and selects the flip-flop F41
To supply. On the other hand, when the semiconductor circuit operates in the system mode (SE = 0), the selector S41 selects data obtained by inverting the data held in the flip-flop F41,
This is supplied to the flip-flop F41.

The selectors S42, S43,..., S46 and the flip-flops F42, F43,.
41 and the flip-flop F41. These selectors select an input signal according to the scan enable signal SE and supply it to each flip-flop. Therefore, the mode key circuit MK
11, when operating in the scan mode, the flip-flops F41 to F46 are connected to the scan path circuit F11.
And F12, the input signals S _in1 and S _in2 are sequentially shifted to the output side. When operating in system mode, flip-flops F41-F
The inverted value of each of the held values of 46 is taken from the data input. Output data of flip-flops F41 to F46, that is, key data key41 and key4
2,..., Key 46 are supplied to the mode holding circuit M11.

As shown in FIG. 5, the mode holding circuit M11
, F56, selectors S51, S52,..., S56, exclusive OR circuits XOR51, XOR52,.
It is constituted by a gate NAND51.

One input terminal of the selector S51 is connected to the output terminal of the key data key41, and the other input terminal is connected to the output terminal of the flip-flop F51. The data input terminal of the flip-flop F51 is connected to the output terminal of the selector S51. Selector S51
Selects an input signal according to the scan enable signal SE and outputs the selected signal to the flip-flop F51. For example,
When the semiconductor circuit operates in the system mode (SE =
0), the selector S51 selects the key data key41 and outputs it to the flip-flop F51. On the other hand, in the scan mode (SE = 1), the selector S51 selects the output data of the flip-flop F51 and supplies it to the flip-flop F51. That is, in this case, the flip-flop F51 continues to hold the data captured when operating in the system mode.

The other selectors S52-S56 and flip-flops F52-F56 are
The connection is almost the same as that of the flip-flop F51. With these selectors and flip-flops,
At the time of the system operation, key data keys 42 to 46 output from the mode key circuit MK11 are taken into the flip-flops. When in scan mode,
Each flip-flop holds data captured in the system mode.

One input terminal of the exclusive OR circuit XOR51 is connected to the output terminal of the flip-flop F51, and the other input terminal is connected to the output terminal of the flip-flop F52. Almost in the same manner, an exclusive OR circuit X
The input terminals of OR52, XOR53,..., XOR55 are respectively connected to the output terminals of two adjacent flip-flops. The input terminals of the NAND gate NAND51 are connected to the output terminals of the exclusive OR circuits XOR51 to XOR55, respectively.
Is output.

In the mode holding circuit M11 described above,
When the data held in the flip-flops F51 to F56 is "01"
0101 "or" 101010 ", the mode signal BE = 0 is output. Otherwise, the mode signal BE is output.
E = 1 is output.

The mode signal BE generated by the mode holding circuit M11 is input to the encryption circuit B11 shown in FIG. When the mode signal BE = 0, the scan path circuit F
11 and F12, the output signals _Sout1 and _Sout2 are output as they are, and when the mode signal BE = 1, the output signals _Sout1 and _{Sout2 of the scan path} circuits F11 and F12 are respectively encrypted, and the encrypted signals _Bout1 and _Sout2 are output. B _out2 is output.
That is, in the semiconductor circuit of the present embodiment, the mode key is set via the scan path circuit, and it is determined whether the output data of the scan path circuit is output as it is or is encrypted and output according to the value of the mode key. Controlled.

FIGS. 6 and 7 are waveform diagrams showing the operation of the semiconductor circuit of the present embodiment. Hereinafter, the operation of the semiconductor circuit of the present embodiment will be described in detail with reference to these waveform diagrams. As shown in FIG. 6, when operating in the scan mode (SE = 1), in synchronization with the clock signal CK,
By the _scan path circuits F11 and F12, the input data S _in1 and S _{in2 of} each _scan path circuit are sequentially taken into the _scan path circuit and shifted to the output side.
At this time, as shown in FIG. 6, it is mixed with a test pattern for testing the combinational logic circuit C11 of the semiconductor circuit.
The mode key data K41, K42,..., K46 are respectively scanned in and taken into the mode key circuit MK11. And when the scan mode operation ends,
The key data keys 41 to 46 output by the mode key circuit MK11 are K41 to K46, respectively.

Next, the scan enable signal SE is set to 0, and the semiconductor circuit operates in the system mode. At this time, the mode holding circuit M11 shown in FIG.
K46 is held. Then, a mode signal BE is output according to the held data. At the same time, the flip-flop other than the flip-flop constituting the mode key circuit M11 in the scan path circuit receives the output data of the combinational logic circuit C11.

Finally, the scan enable signal SE is set to 1 again, and the semiconductor circuit operates in the scan mode. At this time, in synchronization with the clock signal CK, the values of the flip-flops in the _scan path circuits F11 and F12 are sequentially shifted to the output sides of the respective _scan path circuits and output as output data S _out1 and S _out2. .
Output data S _out1 and S _out2 of the scan path circuit are input to the encryption circuit B11, and as a result, encrypted data V11 to V13 and V21 to V23 are sequentially output from the encryption circuit B11.

FIG. 7 shows that the mode key data inputted to the mode key circuit MK11 has a specific value "010101".
FIG. 7 is a waveform diagram showing an operation in the case of having. As shown in the figure, at the time of the scan mode operation (SE = 1), the input data K41, K42, K43 of the specific location of the input data S _in1 of the scan _path circuit F11 is “010”, and the input data of the scan path circuit F12 is The input data K44, K45, K46 of the specific location of S _in2 is “101”. Therefore, data “010101” is held in each flip-flop of the mode key circuit MK11.

During the system mode operation (SE = 0), the input data of the mode key circuit MK11 is
11, the data held in the mode holding circuit M11 becomes "010101". Mode holding circuit M1
1, the mode signal BE is generated in accordance with the held data "010101".
E = 0 is output. Then, even when the mode returns to the scan mode again (SE = 1), the mode signal BE = 0 is held by the mode holding circuit M11, so that the data S _out1 and S _out2 input to the encryption circuit B11 are encrypted. Output without any change.

As described above, according to the present embodiment, predetermined mode key data is mixed with input data to the scan path circuit during the scan mode operation, so that the mode key data is input to the scan path circuit. It is taken into the embedded mode key circuit. During the system mode operation, the mode key data is taken into the mode holding circuit from the mode key circuit, and the mode signal BE is generated according to the mode key data. When the mode key data has a predetermined pattern, the mode signal BE becomes a predetermined set value, and the output signal of the scan path circuit is output as it is. In other cases, since the mode signal BE is different from the predetermined set value, the output signal of the scan path circuit is encrypted and output by the encryption circuit connected to the output side. The output of the campus circuit can be kept secret, it is difficult to estimate the configuration of the combinational logic circuit based on the output of the scan path circuit, and reverse engineering can be prevented.

In the present invention, the number of scan path circuits, the number of flip-flops constituting the scan path circuit, the location and order of each flip-flop of the mode key circuit embedded in the scan path circuit, the mode key The number of data bits and the number of encryption circuit bits are all variable. Further, it is possible to arbitrarily set the encryption method of the encryption circuit and the method of passing the scan output signal when the mode key data matches. Further, a compression circuit can be used instead of the encryption circuit for encrypting the output signal of the scan path circuit.

[0047]

As described above, according to the semiconductor circuit of the present invention, since the output signal of the scan path circuit is compressed or encrypted, the structure of the combinational logic circuit can be estimated from the output of the scan path circuit. And reverse engineering can be prevented. In addition, by inputting specific mode key data in an embedded mode key circuit to the scan path circuit, an output signal of the scan path circuit can be output in series without passing through a compression circuit or an encryption circuit. The scan path circuit can be used for estimating the position of a fault at the time of testing a combinational logic circuit and diagnosing a fault. further,
Mode key data can be inserted at an arbitrary position in the scan path with a variable length, and the procedure for setting the mode data is performed during the scan-in operation. There is an advantage that it is extremely difficult to estimate both even if both are compared.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a scan path circuit.

FIG. 3 is a circuit diagram illustrating a configuration example of an encryption circuit.

FIG. 4 is a circuit diagram showing a configuration example of a mode key circuit.

FIG. 5 is a circuit diagram illustrating a configuration example of a mode holding circuit.

FIG. 6 is a waveform chart showing the operation of the semiconductor circuit of the present embodiment.

FIG. 7 is a waveform chart showing an operation of the semiconductor circuit when specific mode key data is input.

FIG. 8 is a circuit diagram showing an example of a conventional semiconductor circuit having a scan path circuit.

FIG. 9 is a circuit diagram illustrating an example of a semiconductor circuit having a self-test function.

FIG. 10 is a circuit diagram illustrating an example of a pseudo random number generation circuit.

[Explanation of symbols]

C11, C81, C91: combinational logic circuit, F11, F12, F81, F82, F91, F92: scan path circuit, B11: encryption circuit, B91: pseudorandom number generation circuit, B92: data compression circuit, MK11: mode key circuit , M11: Mode holding circuit.

Claims (10)

[Claims] A scan path circuit for sequentially shifting input data to an output side; and performing predetermined processing in accordance with the input data or test data input from the scan path circuit, and transmitting a processing result to the scan path circuit. A mode key circuit that is incorporated at a predetermined position of the scan path circuit and outputs serial data input to the scan path circuit in parallel; A mode signal generating circuit that performs a predetermined logical operation on the output data and outputs a mode signal according to the operation result; and when the mode signal is in one state, outputs the output data of the scan path circuit as it is. When the mode signal is in a state different from the one state, a predetermined value is applied to the output data of the scan path circuit. Performs processing, semiconductor circuit having a data conversion circuit that outputs different from input data data. A plurality of scan path circuits connected in series between an input terminal and an output terminal for sequentially shifting data input to the input terminal to the output terminal in response to a common clock signal; 2. The semiconductor circuit according to claim 1, further comprising a flip-flop. 3. The semiconductor circuit according to claim 2, wherein said mode key circuit is constituted by a plurality of flip-flops incorporated at predetermined positions of said scan path circuit. 4. When operating in the first operation mode, each flip-flop constituting the mode key circuit holds an input signal and outputs it to the output side, and when operating in the second operation mode, 4. The semiconductor circuit according to claim 3, wherein each flip-flop constituting the mode key circuit outputs logically inverted data of the held data. 5. A mode signal generating circuit, comprising: a data holding circuit for holding output data of the mode key circuit; performing a predetermined logical operation on data held by the data holding circuit; 2. The semiconductor circuit according to claim 1, further comprising: a logic operation circuit that outputs the result as a logical operation circuit. 6. The data holding circuit has flip-flops each holding output data of the mode key circuit, and when operating in the first operation mode, each flip-flop holds output data as it is. 6. The semiconductor circuit according to claim 5, wherein when operating in the second operation mode, each of the flip-flops takes in output data of the mode key circuit. 7. The logical operation circuit, comprising: a plurality of exclusive OR circuits for obtaining exclusive OR of data held in the data holding circuit; and a logical product of output data of each of the exclusive OR circuits. 6. The semiconductor circuit according to claim 5, further comprising a logical product circuit to be obtained. 8. The data conversion circuit performs a logical operation on a plurality of flip-flops connected in series and output data of a predetermined one of the plurality of flip-flops, and outputs the operation result to one stage. A feedback circuit to be input to the second flip-flop, when the mode signal is in the one state, the output data of the scan path circuit is output as it is, and when the mode signal is in a state different from the one state, 2. The semiconductor circuit according to claim 1, further comprising: an output circuit that outputs a logical operation result of output data of the scan path circuit and output data of one of the plurality of flip-flops. 9. The semiconductor circuit according to claim 8, wherein said feedback circuit includes an exclusive OR circuit for obtaining an exclusive OR of output data of said predetermined flip-flop. 10. The semiconductor circuit according to claim 8, wherein said output circuit includes an exclusive OR circuit for obtaining an exclusive OR of output data of said scan path circuit and output data of any one of said flip-flops.