JP2003256493A - Tester simulation apparatus and tester simulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a tester simulation apparatus and a tester simulation method capable of shortening the simulation time. <P>SOLUTION: The present invention implements improvements on the tester simulation apparatus performing the simulation by a DUT model simulating the operation of an object under test and a tester model simulating the operation of a tester in testing the object under test by the tester. This apparatus includes a status storage section for at least storing node status data indicating the status of each section of the DUT model, an acquisition means for at least acquiring the node status data from the DUT model to store it in the status storage section, and a setting means for at least setting desired node status data of the status storage section to the DUT model. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tester simulation apparatus and a tester simulation method for simulating a test by a tester of an object to be tested, such as IC and LSI, and more particularly to a tester simulation apparatus and a tester simulation method for reducing the simulation time. It is a thing.

[0002]

2. Description of the Related Art A tester (IC tester) gives an input pattern to an object to be tested (hereinafter abbreviated as DUT) based on a test program, compares an output from the DUT with an expected value pattern, and judges whether the DUT is good or bad. The judgment is made. In recent years, before actually testing the DUT with a tester, the D
The test program is simulated using the UT and tester as a model to confirm the operation of the test program. Such an apparatus is described, for example, in "Chapter 1 SOC
Basic knowledge of test 1 ", Design Wave
Magazine, No. 49, December 2001, pp. 86-93, CQ Publishing Company, etc. This will be described below with reference to FIG.

In FIG. 3, a storage unit 1 stores a test program including a test pattern including an input pattern, an expected value pattern, and the like. Simulation means 2
Is a DUT, based on the test program in the storage unit 1,
Perform a tester operation simulation. Then, the simulation means 2 includes a DUT model 3 and a tester model 4
Have.

The DUT model 3 simulates the circuit operation of a DUT such as an IC or LSI. The tester model 4 simulates the tester operation based on the test program in the storage unit 1. The tester model 4 includes a sequencer model 41 and a pattern memory model 4
2, a signal generation model 43, a plurality of pin electronics models (hereinafter PE models) 44, and the like.

The sequencer model 41 generates an address based on the test program. The pattern memory model 42 uses the address of the sequencer model 41 to
The pattern data set by the test program is output. The signal generator model 43 outputs a signal after timing generation and waveform shaping, that is, an input pattern, an expected value pattern, and a strobe according to the pattern data of the pattern memory model 42.

The PE model 44 is a signal generator model 43.
The input of the output of is input and the signal is exchanged with the DUT model 3.
The PE model 44 includes a driver model 45 and a comparator model 46. The driver model 45 inputs the input pattern from the signal generator model 43 and outputs the DU
Output to T model 3. The comparator model 46 is D
The output of the UT 3 and the expected value pattern of the signal generator model 43 are compared at the strobe timing.

The operation of such a device will be described below.
The simulation unit 2 reads the test program from the storage unit 1 and operates the test program by the tester model 4. The tester model 4 sets the sequencer model 41 and the pattern memory model 42 based on the test program. And the sequencer model 41
Outputs an address based on the setting, and the pattern memory model 42 outputs the set pattern data according to this address. Based on this pattern data, the signal generator model 43 outputs the input pattern, the expected value pattern, and the strobe to the PE model 44.

The driver model 45 then outputs the input pattern from the signal generator model 43 to the DUT model 3. The DUT model 3 outputs according to this input pattern. The comparator model 46 compares this output with the expected value pattern of the signal generator model 43 at the strobe timing of the signal generator model 43.

[0009]

In the tester, the number of test patterns (test items) is not one, and the test is performed by executing test patterns of more than 100 types. Execution of these test patterns depends on the DUT
In some cases, the order of applying the patterns is defined, such as a pattern for setting the mode of the internal circuit of 1 and a pattern to be executed after the mode setting.

Therefore, even if confirmation of the test program is completed halfway, the test pattern must be repeatedly executed from the beginning in order to keep the order of applying the test patterns.

Further, the circuit scale of the DUT is increasing,
The simulation calculation time for logic circuits has become extremely long. At the same time, the number of test patterns has increased and the DU
The simulation time of the T model 3 is also increasing. Similarly, because the number of DUT pins has increased, the tester model 4 has also become large in quantity, and the simulation time of the tester model 4 has also increased. As a result,
The simulation time is increasing more and more, and even when it is desired to confirm the operation of only the DUT model 3, the tester model 4 must be operated, and the simulation takes time.

Therefore, an object of the present invention is to realize a tester simulation apparatus and a tester simulation method for reducing the simulation time.

[0013]

According to a first aspect of the present invention, a test by a tester to be tested is simulated by a DUT model for simulating operation of the test target and a tester model for simulating operation of the tester. In the tester simulation device that performs, a state storage unit that stores at least node state data indicating each state of the DUT model, and an acquisition unit that acquires at least node state data from the DUT model and stores the node state data in the state storage unit. Setting means for setting at least desired node state data of the state storage unit in the DUT model is provided.

The present invention according to claim 2 is characterized in that, in the present invention according to claim 1, the acquisition means acquires at least from the DUT model every time a plurality of test items are completed.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the obtaining means obtains the node state data of the tester model at the same time as the DUT model, stores the node state data in the state storage unit, and sets the setting means. Is characterized in that desired node state data in the state storage section is set in the tester model at the same time as the DUT model.

According to a fourth aspect of the present invention, there is provided a tester simulation apparatus for performing a test by a tester to be tested with a DUT model for simulating the operation of the test target and a tester model for simulating the operation of the tester. A waveform storage unit that stores the waveform data of the tester model, a storage unit that acquires the waveform data from the tester model and stores the waveform data in the waveform storage unit, and based on the waveform data of the waveform storage unit,
A signal generating means for generating a signal is provided at the acquisition position of the waveform data.

According to a fifth aspect of the present invention, there is provided a tester simulation device for simulating a test by a tester to be tested with a DUT model for simulating the operation of the test target and a tester model for simulating the operation of the tester. A waveform storage unit that stores the waveform data of the tester model, a storage unit that acquires the waveform data from the output of the tester model and stores the waveform data in the waveform storage unit, and based on the waveform data of the waveform storage unit, The DUT model is provided with signal generating means for generating a signal.

According to a sixth aspect of the present invention, in a test by a tester to be tested, a DUT model for simulating the operation of the test target and a pin electronics for simulating the operation of the tester and exchanging signals with the DUT model. In a tester simulation device for performing simulation with a tester model having at least a model and a signal generation model for giving a signal to this pin electronics model, a waveform storage section for storing waveform data of the signal generation section model, and this waveform storage section The signal generating means for generating a signal based on the waveform data of the above, and the output of the signal generating means and the output of the signal generating section model are switched to output to the pin electronics model and the output of the signal generating section model. And a switching means for storing the It is characterized in that the digits.

According to a seventh aspect of the present invention, there is provided a tester simulation device for simulating a test by a tester to be tested with a DUT model for simulating the operation of the test target and a tester model for simulating the operation of the tester. A waveform storage unit for storing the waveform data of the tester model, a signal generation unit for generating a signal based on the waveform data of the waveform storage unit, and an output of the signal generation unit and an output of the tester model. And output to the DUT model,
Switching means for storing the output of the tester model in the waveform storage section is provided.

The present invention according to claim 8 is characterized in that, in the present invention according to any one of claims 4 to 7, the signal generating means changes the timing of the signal and outputs it.

According to a ninth aspect of the present invention, there is provided a tester simulation method for simulating a test by a tester under test with a DUT model for simulating the operation of the test under test and a tester model for simulating the operation of the tester. , At least node state data indicating a state of each part from the DUT model is acquired, stored in a state storage part, and desired node state data in the state storage part is at least set in the DUT model. is there.

According to a tenth aspect of the present invention, there is provided a tester simulation method in which a test by a tester to be tested is simulated by a DUT model for simulating the operation of the test target and a tester model for simulating the operation of the tester. The waveform data is acquired from the tester model, stored in the waveform storage unit, and a signal is generated at the acquisition position of the waveform data based on the waveform data in the waveform storage unit.

In the present invention according to claim 11, in a tester simulation method, a test by a tester to be tested is simulated by a DUT model for simulating the operation of the test target and a tester model for simulating the operation of the tester. Waveform data is obtained from the output of the tester model, stored in the waveform storage unit, and based on the waveform data in the waveform storage unit, the DU
It is characterized in that a signal is generated in the T model.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Here, the same parts as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 1, the state storage unit 5 stores node state data indicating the state of each part of the DUT model 3 and the tester model 4 of the simulation means 2. Acquisition means 6
Acquires the node state data from the DUT model 3 and the tester model 4 and stores it in the state storage unit 5. Setting means 7
Sets desired node state data in the state storage unit 5 in the DUT model 3 and the tester model 4.

The waveform storage section 8 has a simulation means 2
The waveform data of the tester model 4 (signal generation unit model 43) is stored. The signal generating means 9 generates a signal for the tester model 4 based on the waveform data in the waveform storage section 8.
Further, the signal generation means 9 changes the timing of the signal and outputs it. The switching unit 47 is provided between the signal generation unit model 43 and the PE model 44 of the tester model 4, switches the output of the signal generation unit model 43 and the output of the signal generation unit 9, and outputs the output to the PE model 44. The waveform generator 8 stores the output of the signal generator model 43. That is,
The switching means 47 is also a storage means. The acquisition means 6,
The setting means 7 and the signal generating means 9 are controlled by the simulation means 2.

The operation of such an apparatus will be described below by dividing it into a normal simulation operation, a skip simulation operation, and a simple simulation operation.

(1) Normal simulation operation. The switching means 47 switches to the output of the signal generator model 43. Then, the simulation unit 2 reads the test program (first test pattern) from the storage unit 1 and causes the tester model 4 to operate the test program. The tester model 4 includes a sequencer model 41 and a pattern memory model 42 based on the test program.
Set to. Then, the sequencer model 41 outputs an address based on the setting, and the pattern memory model 42 outputs the set pattern data by this address. Based on this pattern data, the signal generator model 43 outputs the input pattern, the expected value pattern, and the strobe to the switching means 47. The switching means 47 outputs each waveform data to the PE model 44 and stores it in the waveform storage unit 8 as event driven data.

Then, the driver model 45 outputs the input pattern from the switching means 47 to the DUT model 3.
The DUT model 3 outputs according to this input pattern. The comparator model 46 compares this output with the expected value pattern from the switching means 47 at the timing of the strobe from the switching means 47.

When the simulation of the first test pattern is completed, the acquisition unit 6 acquires the node state data of each state of the DUT model 3 and the tester model 4 according to the instruction of the simulation unit 2 and stores it in the state storage unit 5. To do. Next, the simulation unit 2 starts the storage unit 1 from the simulation end state of the previous test pattern.
Of the test program (second test pattern) is read, and the test program is operated by the tester model 4. Even after the simulation of the second test pattern is completed, the acquisition unit 6 acquires the node state data of the DUT model 3 and the tester model 4 according to the instruction of the simulation unit 2, and stores the node state data in the state storage unit 5. Repeat this operation for all test patterns (test items)
To simulate.

(2) Skip simulation operation. When the debug confirmation has been completed up to the second test pattern by the normal simulation operation, the setting unit 7 is instructed by the simulation unit 2 from the state storage unit 5, that is, the node at the end of the second test pattern. The state data is read out and set in the DUT model 3 and the tester model 4. The switching means 47 switches to the output of the signal generator model 43. Then, the simulation means 2 reads the test program (third test pattern) from the storage unit 1 and causes the tester model 4 to operate the test program.

The tester model 4 sets the sequencer model 41 and the pattern memory model 42 based on the test program. Then, the sequencer model 41 outputs an address based on the setting, and with this address,
The pattern memory model 42 outputs the set pattern data. Based on this pattern data, the signal generator model 43 outputs the input pattern, the expected value pattern, and the strobe to the switching means 47. The switching unit 47 outputs each waveform data to the PE model 44 and stores the waveform data in the waveform storage unit 8.

Then, the driver model 45 outputs the input pattern from the switching means 47 to the DUT model 3.
The DUT model 3 outputs according to this input pattern. The comparator model 46 compares this output with the expected value pattern of the switching means 47 at the strobe timing of the switching means 47.

When the simulation of the third test pattern is completed, the acquisition means 6 acquires the node status data of the respective statuses of the DUT model 3 and the tester model 4 according to the instruction of the simulation means 2 and stores them in the status storage unit 5. To do. Next, the simulation means 2 uses the storage unit 1.
The test program (4th test pattern) is read and the test program is operated by the tester model 4. A simulation is performed by repeating such operations.

Thus, in the desired test item,
The node state data acquired by the acquisition unit 6 is set in the setting unit 7
Since the DUT model 3 and the tester model 4 are set by, the simulation can be executed from the test items in the middle. Therefore, only the test item to be confirmed can be simulated, and the simulation time can be shortened.

(3) Simple simulation operation. When the waveform data is stored in the waveform storage unit 8 by the normal simulation operation, the switching unit 47 switches to the output of the signal generating unit 9. Then, according to an instruction from the simulation means 2, the signal generation means 9 causes the waveform storage section 8 to
The waveform data is read from and the input pattern, expected value pattern, and strobe are output to the switching means 47. The switching means 47 outputs each signal to the PE model 44. At this time, the simulation means 2 does not operate the sequencer model 41, the pattern memory model 42, and the signal generator model 43 of the tester model 4.

Then, the driver model 45 outputs the input pattern from the switching means 47 to the DUT model 3.
The DUT model 3 outputs according to this input pattern. The comparator model 46 compares this output with the expected value pattern of the switching means 47 at the strobe timing of the switching means 47. Thereby, the operation simulation of the DUT model 3 by the output of the tester model 4 can be performed to confirm the operation of the DUT model 3.

Next, a simple simulation operation of a test called shmoo or margin will be described. Here, the shmoo is such that the two or three parameters, for example, the voltage level of the input pattern, the timing, etc. are changed stepwise, and the pass and the fail at each parameter are plotted using a certain symbol, and the DUT The operation limit and the margin for the set value are tested. On the other hand, the margin means that the same test is performed with one parameter, usually, the timing. In addition, here, only the simulation in which the timing is changed stepwise will be described.

When the waveform data is stored in the waveform storage section 8 by the normal simulation operation, the switching means 47
Switch to the output of the signal generating means 9. Then, according to the instruction of the simulation means 2, the signal generation means 9
The waveform data is read from the waveform storage unit 8, the input pattern, the expected value pattern, and the strobe timing are changed and output to the switching means 47. The switching means 47 outputs each signal to the PE model 44. At this time, the simulation means 2 uses the sequencer model 4 of the tester model 4.
1, pattern memory model 42, signal generator model 43
Does not work.

Then, the driver model 45 outputs the input pattern from the switching means 47 to the DUT model 3.
The DUT model 3 outputs according to this input pattern. The comparator model 46 compares this output with the expected value pattern of the switching means 47 at the strobe timing of the switching means 47, and determines pass / fail.

Again, the simulation means 2 instructs the signal generation means 9 to change the timing different from the last time, and the signal generation means 9 reads the waveform data from the waveform storage section 8 and reads the input pattern, the expected value pattern and the strobe. The timing is changed and output to the switching means 47. By repeating such an operation, the signal generating means 9 changes the timing of the signal stepwise and outputs the signal to perform a simulation of shmoo and margin.

As described above, since the switching means 47 stores the output of the signal generating section model 43 in the waveform storing section 8 and the signal generating section 9 generates a signal by the waveform data of the waveform storing section 8, the sequencer model 41, Pattern memory model 4
2. It is not necessary to perform the operation simulation of the signal generator model 43. Therefore, the tester model 4 and the signal generating means 9 can be switched and used by the switching means 47 according to the simulation content to be confirmed, and the simulation time can be shortened.

Further, since the signal generating means 9 changes and outputs the signal timing, the sequencer model 41, the pattern memory model 42, and the signal generating unit model 43 do not need to repeat similar simulations, and the simulation time can be reduced. It can be shortened.

The present invention is not limited to this, and the switching means 47 is provided at the latter stage of the PE model 44, that is,
The configuration may be provided between the PE model 44 and the DUT model 3. That is, the configuration is as shown in FIG.

In FIG. 2, the switching means 10 switches between the output of the signal generating means 9 and the output of the tester model 4,
The output of the tester model 4 is stored in the waveform storage unit 8 while being output to the DUT model 3. Such a device is shown in FIG.
The operation is almost the same as that of the device shown in FIG.
Only the input pattern is stored in the waveform storage unit 8, and the DUT
The output from model 3 is passed and given to PE model 44. When the switching means 10 switches to the output of the signal generating means 9, the simulation means 2 does not operate the entire tester model 4.

Storage means is provided in place of the switching means 10, and the storage means stores the output of the tester model 4 in the waveform storage section 8, and the waveform generation means 9 causes the waveform storage section 8 to be stored.
The input pattern may be read from and the input pattern may be directly applied to the DUT model 3.

Further, although the acquisition means 6 has been described as having a configuration in which the acquisition timing of the node state data of the DUT model 3 and the tester model 4 is performed every time the test item is completed, any timing may be used. Although the acquisition unit 6 has been described as having a configuration for acquiring the node state data during the normal simulation operation and the skip simulation operation, it may have a configuration for acquiring the node state data even during the simple simulation operation. That is, the configuration may be such that it is acquired at any operation.

Although the acquisition means 6, the setting means 7, and the signal generation means 9 are controlled by the simulation means 2, they may be controlled by the external control means including the simulation means 2.

Further, the acquisition means 6 acquires the node state data of the respective states of the DUT model 3 and the tester model 4,
Although the setting means 7 has shown the configuration for setting the node state data in the DUT model 3 and the tester model 4, the configuration is not limited to this. Normally, the test program does not define the same settings as long as the test items have the same settings as the previous test items. Therefore, when the simulation is performed from the middle of the test program, it is necessary to set the node state data in the tester model 4 as in the DUT model 3. But,
If the test program specifies the same setting as the previous test item, the setting of the node state data of the tester model 4 becomes unnecessary. That is, the acquisition means 6 is D
The node state data may be acquired only from the UT model 3, stored in the state storage unit 5, the node state data may be read from the state storage unit 5, and the setting unit 7 may set only the DUT model 3.

[0050]

According to the first to third aspects of the present invention, the node state data obtained by the obtaining means is set in the DUT model by the setting means, so that the simulation can be executed halfway. Therefore, it is possible to perform a simulation from a place to be confirmed, and it is possible to shorten the simulation time.

According to the fourth and fifth aspects, since the storing means stores the waveform data of the tester model in the waveform storage section and the signal generating means generates the signal by the waveform data of the waveform storage section, most of the tester model is stored. Or, it is not necessary to perform the whole operation simulation. Therefore, the simulation time can be shortened.

According to the sixth aspect, since the switching means stores the waveform data of the signal generating section model in the waveform storing section and the signal generating section generates the signal by the waveform data of the waveform storing section, most of the tester model is obtained. Or, it is not necessary to perform the whole operation simulation. Therefore, the simulation time can be shortened.

According to the seventh aspect, since the switching means stores the waveform data of the tester model in the waveform storage section and the signal generating means generates the signal by the waveform data in the waveform storage section, most or all of the tester model is generated. It is not necessary to perform the operation simulation of. Therefore, the simulation time can be shortened.

According to the eighth aspect, since the signal generating means changes the timing of the signal and outputs the signal, it is not necessary to repeat the similar simulation, and the simulation time can be shortened.

According to the ninth aspect, the node state data is obtained from the DUT model and the obtained desired node state data is set in the DUT model, so that the simulation can be executed halfway. Therefore, it is possible to perform a simulation from a place to be confirmed, and it is possible to shorten the simulation time.

According to the tenth and eleventh aspects, since the waveform data of the tester model is stored in the waveform storage unit and the signal is given to the DUT model or the tester model based on the waveform data of the waveform storage unit, most of the tester model is stored. Or, it is not necessary to perform the whole operation simulation. Therefore, the simulation time can be shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional tester simulation device.

[Explanation of symbols]

1 memory 2 Simulation means 3 DUT model 4 tester model 5 State storage 6 acquisition means 7 Setting means 8 Waveform memory 9 Signal generation means 10,47 Switching means 43 Signal generation model 44-pin electronics model

Claims (11)

[Claims] 1. A DUT model for simulating an operation of an object to be tested in a test by a tester to be tested.
In a tester simulation device that performs a simulation with a tester model that simulates the operation of a tester, a state storage unit that stores at least node state data indicating the state of each part of the DUT model, and obtain at least node state data from the DUT model, Acquisition means for storing in the state storage unit, and desired node state data in the state storage unit for the DUT
A tester simulation device characterized in that a setting means for setting at least a model is provided. 2. The tester simulation apparatus according to claim 1, wherein the acquisition means acquires at least a DUT model each time a plurality of test items are completed. 3. The acquisition means acquires the node state data of the tester model at the same time as the DUT model and stores it in the state storage section, and the setting means sets the desired node state data in the state storage section to D.
The tester simulation device according to claim 1, wherein the tester model is set simultaneously with the UT model. 4. A DUT model for simulating an operation of a test object, which is a test by a tester of the test object,
In a tester simulation device that performs simulation with a tester model that simulates the operation of a tester, a waveform storage unit that stores the waveform data of the tester model, and a waveform storage unit that acquires the waveform data from the tester model and stores the waveform data in the waveform storage unit. A tester simulation apparatus comprising: a means and a signal generation means for generating a signal at a waveform data acquisition position based on the waveform data in the waveform storage section. 5. A DUT model for simulating an operation of an object to be tested in a test by a tester to be tested.
In a tester simulation device that performs simulation with a tester model that simulates the operation of a tester, a waveform storage unit that stores the waveform data of the tester model, and waveform data is acquired from the output of the tester model and stored in the waveform storage unit. A tester simulation device, comprising: a storage unit for storing the signal; and a signal generation unit for generating a signal in the DUT model based on the waveform data in the waveform storage unit. 6. A DUT model for simulating an operation of an object to be tested in a test by a tester to be tested,
In the tester simulation device, the operation of the tester is simulated, and a simulation is performed by a tester model having at least a pin electronics model for exchanging signals with the DUT model and a signal generator model for giving signals to the pin electronics model. Waveform storage section for storing the waveform data of the partial model, signal generating means for generating a signal based on the waveform data of the waveform storage section, and switching between the output of the signal generating means and the output of the signal generating section model And a switching unit for storing the output of the signal generation unit model in the storage unit while outputting the output to the pin electronics model. 7. A DUT model for simulating an operation of an object to be tested for a test by a tester to be tested,
In a tester simulation device for performing simulation with a tester model for simulating the operation of a tester, a waveform storage section for storing the waveform data of the tester model, and a signal generating means for generating a signal based on the waveform data in the waveform storage section. And switching means for switching between the output of the signal generating means and the output of the tester model to output to the DUT model and to store the output of the tester model in the waveform storage section. Tester simulation device. 8. The tester simulation apparatus according to claim 4, wherein the signal generating means changes the timing of the signal and outputs it. 9. A DUT model for simulating an operation of an object to be tested for a test by a tester to be tested,
In a tester simulation method for performing simulation with a tester model for simulating the operation of a tester, at least node status data indicating the status of each part is acquired from the DUT model and stored in a status storage part, and a desired node of this status storage part is stored. The status data is the DUT
A tester simulation method characterized by setting at least a model. 10. A tester simulation method for simulating a test by a tester under test with a DUT model for simulating the operation of the test under test and a tester model for simulating the operation of the tester, wherein waveform data is output from the tester model. Is acquired and stored in the waveform storage unit, and a signal is generated at the acquisition position of the waveform data based on the waveform data in the waveform storage unit. 11. A tester simulation method in which a test by a tester to be tested is simulated by a DUT model for simulating the operation of the test target and a tester model for simulating the operation of the tester. A tester simulation method characterized in that waveform data is acquired, stored in a waveform storage unit, and a signal is generated in a DUT model based on the waveform data in the waveform storage unit.