JP3697171B2 - Pattern generation method and pattern generation apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pattern generation method and a pattern generation apparatus for generating a test pattern for a semiconductor test apparatus, and more particularly to a pattern generation method and a pattern generation apparatus suitable for generating a scan pattern.
[0002]
[Prior art]
A semiconductor test apparatus for inspecting the electrical characteristics of a semiconductor integrated circuit (IC device) gives a predetermined test pattern to the device under test, reads the output data of the device under test, and compares it with expected value data prepared in advance. By doing this, it is an apparatus for inspecting whether there is no problem in the basic operation and function of the device under measurement. A pattern generator in a semiconductor test apparatus stores test pattern data in a memory such as a DRAM, and reads the stored data from the memory to generate a test pattern.
[0003]
The test pattern is usually a random pattern according to the basic operation and function for testing the device under test, and is supplied to all pins of the device under test simultaneously. The random pattern data must be created by the IC device developer according to the basic operation and function for testing the IC device. On the other hand, some logic ICs having a logic circuit have a dedicated test pin so that a test of a single logic element inside the IC device can be performed in addition to a test using a random pattern. Such a test pattern supplied to the test-dedicated pins is called a scan pattern. The scan pattern data can be automatically created by software from the information of the circuit structure inside the IC device. The scan pattern data has a feature that the number of target pins is small but the data is long compared to the random pattern data. During the execution of the scan pattern, the random pattern data supplied to the pins other than the test dedicated pins hardly changes.
[0004]
Conventional pattern generators for generating random patterns and scan patterns either prepare a memory for random pattern data and a memory for scan pattern data separately, or combine scan pattern data in a memory for storing random pattern data together. I remembered.
[0005]
[Problems to be solved by the invention]
If the memory for random pattern data and the memory for scan pattern data are prepared separately, there is a problem that the memory control circuit becomes complicated because each memory control circuit must be provided. In particular, when a DRAM is used for speeding up and capacity increase, since the memory control circuit needs a refresh function of the DRAM, complication of the memory control circuit becomes a big problem.
[0006]
On the other hand, if random pattern data and scan pattern data are stored in the same memory, the memory control circuit is not complicated. However, if the scan pattern data is stored in the random pattern data memory as it is, the random pattern data to be supplied to pins other than the test dedicated pins during the execution of the scan pattern must be stored in the same address as the scan pattern data. There is a problem that the required memory capacity increases.
[0007]
An object of the present invention is to provide a pattern generation method and a pattern generation apparatus capable of suppressing the complexity of the memory control circuit and the increase in the memory capacity.
[0008]
[Means for Solving the Problems]
In the pattern generation method according to the present invention, data excluding repetitive data from test pattern data including scan pattern data is stored in a first memory, and a repeat signal for instructing data repetition and control for instructing a scan pattern are stored. The signal is stored in the second memory, and when the repetition of data is instructed by the repetition signal, the data read from the first memory and the control signal read from the second memory are repeated, and the control signal When the scan pattern is commanded by the above, the data read from the first memory before the command is held, the scan pattern data is detected from the repeated data, and the data of the scan pattern target pin among the held data Is replaced with the detected scan pattern data.
[0009]
A pattern generator according to the present invention includes a first memory for storing data excluding repeated data from test pattern data including scan pattern data, a repeat signal for instructing data repetition, and a control for instructing a scan pattern. A second memory for storing the signal, and a repeating means for repeating the data read from the first memory and the control signal read from the second memory when data repetition is commanded by the repetition signal. , When a scan pattern is commanded by the control signal, a holding unit that holds data read from the first memory before the command, a detection unit that detects scan pattern data from data repeated by the repeating unit, When a scan pattern is instructed by a control signal, the scan pattern target pin of the data held by the holding means is It is obtained by a selection means for replacing the detected scan pattern data detecting means motor.
[0010]
In the pattern generation method and pattern generation apparatus according to the present invention, random pattern data and scan pattern data are stored in the same memory, so that the complexity of the memory control apparatus is suppressed. At this time, since data excluding repetitive data from the test pattern data is stored in the memory, an increase in necessary memory capacity is suppressed. When the scan pattern is commanded by the control signal, the data read from the first memory before the command includes data that repeats during the execution of the scan pattern, and the data repeated by the repeat signal includes the scan pattern data Is included. Accordingly, the data read from the first memory before the command is held, the scan pattern data is detected from the repeated data, and the scan pattern target pin data is detected from the held data. To generate test pattern data composed of scan pattern data and data repeated during execution of the scan pattern.
[0011]
In the pattern generation method and the pattern generation apparatus of the present invention, the repetition signal instructs the number of repetitions of data, and the data read from the first memory and the control signal read from the second memory are the repetition signal. It repeats the number of times specified in. When test pattern data includes data that repeats multiple times in succession, you can exclude all data that repeats multiple times in succession from the data stored in the memory by commanding the number of data repetitions with the repeat signal. The increase in the required memory capacity is further suppressed.
[0012]
Furthermore, the pattern generation method and pattern generation apparatus of the present invention detects scan pattern data by parallel / serial conversion of repeated data. Thereby, the scan pattern data can be detected with a simple configuration.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a pattern generator according to an embodiment of the present invention. The pattern generator 20 according to the present embodiment includes a control pattern memory 21, a random pattern memory 22, a repeat control circuit 23, a data hold circuit 24, a parallel / serial converter 25, and a multiplexer 26. FIG. 2 is a diagram illustrating an example of signals stored in the control pattern memory 21 and data stored in the random pattern memory 22 of the pattern generation apparatus 20 according to the embodiment of the present invention.
[0014]
The control pattern memory 21 stores an address repeat signal RPT for instructing data repetition and a scan control signal SPM for instructing a scan pattern. When the address repeat signal RPT is “0”, no repetition is commanded. When it is “1”, one repetition is commanded. When it is “2”, two repetitions are commanded. 3 ”,“ 4 ”,... When the scan control signal SPM is “0”, a random pattern is commanded, and when it is “1”, a scan pattern is commanded.
[0015]
In the present embodiment, when a scan pattern is commanded by the scan control signal SPM, data repetition is always commanded by the address repeat signal RPT. In the example of FIG. 2, the address repeat signal RPT “3” and the scan control signal SPM “1” are stored in the address “4” of the control pattern memory 21, and the address repeat signal RPT “1” is scanned in the address “5”. The control signal SPM “1” is stored.
[0016]
In this embodiment, even when a random pattern is commanded by the scan control signal SPM, data repetition may be commanded by the address repeat signal RPT. This is performed when the test pattern data includes random pattern data that repeats independently of the scan pattern. In the example of FIG. 2, the address repeat signal RPT “2” and the scan control signal SPM “0” are stored at the address “2” of the control pattern memory 21.
[0017]
The random pattern memory 22 stores random pattern data and scan pattern data of test pattern data. However, repetitive data is excluded from the test pattern data and is not stored. The example of FIG. 2 shows only the test pattern data given to the four pins of the device under test. P1, P2, P3, and P4 are the first pin, the second pin, and the third pin of the device under test, respectively. , Corresponding to the fourth pin. In this example, the first pin P1 is a scan pattern target pin, and the scan pattern data “A4”, “B4”, “C4”, “D4”, “A5”, “ B5 "is sequentially supplied, and the random pattern data" B3 "," C3 ", and" D3 "are sequentially and repeatedly supplied to the second pin P2, the third pin P3, and the fourth pin P4, respectively. Show. In this case, scan pattern data “A4”, “B4”, “C4”, and “D4” are stored at address “4” of the random pattern memory 22, and scan pattern data “A5”, “D4” are stored at address “5”. B5 "and random pattern data" C5 "and" D5 "are stored. Random pattern data “B3”, “C3”, and “D3” that are continuously repeated during the execution of the scan pattern are stored only once at address “3”.
[0018]
First, the operation of the pattern generator 20 will be described. In FIG. 1, an address signal is input to a control pattern memory 21 and a random pattern memory 22 of a pattern generator 20 from a sequence pattern generator 10 that controls the flow (sequence) of a pattern program. The control pattern memory 21 outputs the address repeat signal RPT and the scan control signal SPM stored at the address specified by the address signal. The random pattern memory 22 outputs test pattern data PTD stored at the address specified by the address signal.
[0019]
The address repeat signal RPT and scan control signal SPM from the control pattern memory 21 and the test pattern data PTD from the random pattern memory 22 are input to the repeat control circuit 23. When the repetition of data is not instructed by the address repeat signal RPT, the repeat control circuit 23 outputs the test pattern data PTD and the scan control signal SPM as they are as the test pattern data PTX and the scan control signal SPMX. When data repetition is instructed by the address repeat signal RPT, the test pattern data PTD and the scan control signal SPM are repeated as many times as specified by the repetition signal, and are output as the test pattern data PTX and the scan control signal SPMX. .
[0020]
The test pattern data PTX and the scan control signal SPMX from the repeat control circuit 23 are input to the data hold circuit 24. When a random pattern is instructed by the scan control signal SPMX, the data hold circuit 24 outputs the test pattern data PTX as it is as the test pattern data RPD. When a scan pattern is commanded by the scan control signal SPMX, the test pattern data PTX before command is held and output as test pattern data RPD. At this time, the held test pattern data RPD includes data that repeats during the execution of the scan pattern.
[0021]
The test pattern data PTX from the repeat control circuit 23 is input to the parallel / serial converter 25. The parallel / serial converter 25 performs parallel / serial conversion on the test pattern data PTX and outputs it as serial data SSP, and is reset when a different address signal is input to the pattern generator 20. Accordingly, when different test pattern data PTX is continuously input, the parallel / serial converter 25 outputs only the head data of the test pattern data PTX, and the same test pattern data PTX is continuously input. When this occurs, the subsequent number of data is output in order from the beginning of the test pattern data PTX. When a scan pattern is commanded by the scan control signal SPM, the test pattern data PTD includes scan pattern data, and the repeat control circuit 23 is commanded by the repetitive signal the test pattern data PTD including the scan pattern data. The parallel / serial converter 25 can detect the scan pattern data from the test pattern data PTX repeated by the repeat control circuit 23.
[0022]
The scan control signal SPMX from the repeat control circuit 23, the test pattern data RPD from the data hold circuit 24, and the serial data SSP from the parallel / serial converter 25 are input to the multiplexer 26. When a random pattern is commanded by the scan control signal SPMX, the multiplexer 26 outputs the test pattern data RPD as it is as the test pattern data TPD. When the scan pattern is instructed by the scan control signal SPMX, the data of the scan pattern target pin selected by the pin select signal input from the control means 50 via the register 40 from the test pattern data RPD is converted into the serial data. Replace with SSP and output as test pattern data TPD. The test pattern data TPD from the multiplexer 26 is input to the applied waveform generating means 30, and the applied waveform generating means 30 generates an applied waveform to be supplied to the device under measurement.
[0023]
Next, an example of each signal and data of the pattern generator 20 in the case of the example of FIG. 2 will be described. FIG. 3 is a diagram illustrating an example of each signal and data of the pattern generation apparatus 20 according to the embodiment of the present invention. The example of FIG. 3 shows only the test pattern data applied to the four pins of the device under test corresponding to the example of FIG. 2, and P1, P2, P3, and P4 are the first pins of the device under test, respectively. , Second pin, third pin, and fourth pin, and the first pin P1 is a scan pattern target pin.
[0024]
First, in step 0, an address signal “0” is input. The scan control signal SPM read from the address “0” of the control pattern memory 21 of FIG. 2 is “0”, and the test pattern data PTD read from the address “0” of the random pattern memory 22 of FIG. (“A0”, “B0”, “C0”, “D0”) becomes the test pattern data PTX, RPD, TPD as they are. At this time, the address repeat signal RPT read from the address “0” of the control pattern memory 21 in FIG. 2 is “0”, and data is not repeated in the next step. In step 1, an address signal “1” is input, which is the same as in step 0.
[0025]
In step 2, the address signal “2” is input. The scan control signal SPM read from the address “2” of the control pattern memory 21 of FIG. 2 is “0”, and the test pattern data PTD read from the address “2” of the random pattern memory 22 of FIG. (“A2”, “B2”, “C2”, “D2”) becomes the test pattern data PTX, RPD, TPD as they are. Since the address repeat signal RPT read from the address “2” of the control pattern memory 21 in FIG. 2 is “2”, data is repeated in the next two steps 3 and 4. This is a case where random pattern data “A2”, “B2”, “C2”, and “D2” are repeated twice regardless of the scan pattern. In step 5, the address signal “3” is input, which is the same as step 0.
[0026]
In step 6, the address signal “4” is input. Since the scan control signal SPM read from the address “4” of the control pattern memory 21 in FIG. 2 is “1”, the test pattern data RPD is the data “A3”, “B3”, “ C3 "and" D3 "are held. On the other hand, the test pattern data PTX is the test pattern data PTD (“A4”, “B4”, “C4”, “D4”) read from the address “4” of the random pattern memory 22 of FIG. The serial data SSP becomes scan pattern data “A4” detected from the test pattern data PTX. Therefore, in the test pattern data TPD, the data “A3” of the first pin P1 is replaced with the detected scan pattern data “A4” in the test pattern data RPD in which the data of step 5 is held. Since the address repeat signal RPT read from the address “4” in the control pattern memory 21 of FIG. 2 is “3”, data is repeated in the following three steps 7 to 9.
[0027]
In the next three steps 7 to 9, the test pattern data PTX repeats the data “A4”, “B4”, “C4”, and “D4” of step 6, and the test pattern data RPD is the data “step 5”. A3 "," B3 "," C3 ", and" D3 "are held. In step 7, the serial data SSP becomes the scan pattern data “B4” detected from the test pattern data PTX. Therefore, in the test pattern data TPD in step 7, the data “A3” of the first pin P1 in the test pattern data RPD in which the data in step 5 is held is replaced with the detected scan pattern data “B4”. . Similarly, in Step 8, the data “A3” of the first pin P1 is replaced with the scan pattern data “C4”, and in Step 9, the scan pattern data “D4” is replaced.
[0028]
In Step 10, the address signal “5” is input. Since the scan control signal SPM read from the address “5” of the control pattern memory 21 in FIG. 2 is “1”, the test pattern data RPD is the data “A3”, “B3”, “ C3 "and" D3 "are held. On the other hand, the test pattern data PTX is the test pattern data PTD (“A5”, “B5”, “C5”, “D5”) read from the address “5” of the random pattern memory 22 of FIG. The serial data SSP becomes scan pattern data “A5” detected from the test pattern data PTX. Accordingly, in the test pattern data TPD, the data “A3” of the first pin P1 is replaced with the detected scan pattern data “A5” in the test pattern data RPD in which the data of Step 9 is held. Then, since the address repeat signal RPT read from the address “5” of the control pattern memory 21 in FIG. 2 is “1”, data is repeated in the next one step 11.
[0029]
In step 11, the test pattern data PTX repeats the data “A5”, “B5”, “C5”, and “D5” in step 10, and the test pattern data RPD is the data “A3”, “B3” in step 9. , “C3”, “D3” are held. The serial data SSP becomes the scan pattern data “B5” detected from the test pattern data PTX. Accordingly, in the test pattern data TPD, the data “A3” of the first pin P1 is replaced with the detected scan pattern data “B5” in the test pattern data RPD in which the data of Step 9 is held. In steps 12 and 13, the address signals “6” and “7” are input, which is the same as step 0.
[0030]
As described above, when the test pattern data TPD of FIG. 3 is generated, all of the test pattern data TPD of FIG. 3 had to be stored in the past. It is only necessary to store the signals and data shown in FIG.
[0031]
【The invention's effect】
According to the pattern generation method and the pattern generation apparatus of the present invention, the random pattern data and the scan pattern data are stored in the same memory, so that the complexity of the memory control apparatus can be suppressed. Further, by storing data excluding repetitive data from the test pattern data in the memory, it is possible to suppress an increase in necessary memory capacity. When the scan pattern is generated, the data read from the first memory before the scan pattern command is held, the scan pattern data is detected from the repeated data, and the scan pattern target pin data among the held data By replacing the detected pattern data with the detected scan pattern data, it is possible to generate test pattern data including the scan pattern data and data repeated during the execution of the scan pattern.
[0032]
Furthermore, according to the pattern generation method and pattern generation apparatus of the present invention, it is possible to instruct the repetition of data by a repetition signal even when a random pattern is generated. Therefore, when the test pattern data includes random pattern data that repeats independently of the scan pattern, the required memory capacity can be reduced except for the repeated data from the test pattern data stored in the memory.
[0033]
Also, according to the pattern generation method and pattern generation apparatus of the present invention, when the test pattern data includes data that repeats a plurality of times in succession, it is stored in the memory by instructing the number of repetitions of the data with a repetition signal. Since it is possible to remove all the data that is repeatedly repeated a plurality of times from the data, it is possible to further suppress an increase in necessary memory capacity.
[0034]
Furthermore, according to the pattern generation method and pattern generation apparatus of the present invention, scan pattern data can be detected with a simple configuration by detecting scan pattern data by parallel / serial conversion of repeated data.
[Brief description of the drawings]
FIG. 1 is a block diagram of a pattern generator according to an embodiment of the present invention.
FIG. 2 is a diagram showing an example of a signal stored in a control pattern memory and data stored in a random pattern memory of the pattern generator according to the embodiment of the present invention.
FIG. 3 is a diagram illustrating an example of each signal and data of the pattern generation apparatus according to the embodiment of the present invention.
[Explanation of symbols]
10 ... Sequence pattern generator, 20 ... Pattern generator,
21 ... Control pattern memory, 22 ... Random pattern memory,
23 ... Repeat control circuit, 24 ... Data hold circuit,
25 ... Parallel / serial converter, 26 ... Multiplexer,
30 ... applied waveform generating means, 40 ... register, 50 ... control means

Claims (6)

Storing data in the first memory excluding repetitive data from test pattern data including scan pattern data;
Storing a repeat signal for commanding data repetition and a control signal for commanding a scan pattern in the second memory;
When data repetition is commanded by a repeat signal, the data read from the first memory and the control signal read from the second memory are repeated,
When a scan pattern is commanded by a control signal, the data read from the first memory before the command is held, the scan pattern data is detected from the repeated data, and the scan pattern target is included in the held data A pattern generation method characterized by replacing pin data with detected scan pattern data. The repeat signal instructs the number of data repetitions, and the data read from the first memory and the control signal read from the second memory are repeated the number of times specified by the repeat signal. The pattern generation method according to claim 1. 3. The pattern generation method according to claim 2, wherein scan pattern data is detected by parallel / serial conversion of the repeated data. A first memory for storing data excluding repetitive data from test pattern data including scan pattern data;
A second memory for storing a repeat signal for commanding data repetition and a control signal for commanding a scan pattern;
Repetitive means for repeating the data read from the first memory and the control signal read from the second memory when data repetition is instructed by a repetitive signal;
Holding means for holding data read from the first memory before the command when the scan pattern is commanded by the control signal;
Detecting means for detecting scan pattern data from data repeated by the repeating means;
And a selection unit that replaces the data of the scan pattern target pin among the data held by the holding unit with the scan pattern data detected by the detection unit when a scan pattern is instructed by the control signal. Pattern generator. The repetition signal instructs the number of times of data repetition, and the repetition means repeats the data read from the first memory and the control signal read from the second memory the number of times specified by the repetition signal. The pattern generator according to claim 4. 6. The pattern generating apparatus according to claim 5, wherein the detection means is a parallel / serial converter that performs parallel / serial conversion on the data repeated by the repetition means.

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