JP2000105781A - Logical simulator and logical simulate system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a logical simulator and a logical simulate system capable of largely reducing the work man-hours related to simulation execution, and capable of obtaining a highly reliable verified result with a simple constitution. SOLUTION: This system is provided with a portable measuring part 2 for generating an input pattern and a signal generation model, simulator main body 3 a circuit to be verified built in and for supplying the input pattern generated by the portable measuring part 2 to the circuit to be verified, and for outputting a result obtained by comparing the output with the signal generation model generated by the portable measuring part 2, a display device 5 for displaying the content of simulation information, and a console 4 for outputting an execution instruction for instruction an operation timing to the simulator main body 3. The portable measuring part 2 is constituted so as to be separatable, and this portable measuring part 2 is constituted so that a signal pattern such as the output of a circuit provided at the outside part can be stored as an input pattern and a signal generation model. The console 4 operates control at the time of storing the signal pattern of the portable measuring part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic simulator and a logic simulation system for verifying logic, and more particularly, to a logic simulator and a logic simulation system for verifying logic written in a programmable device.

[0002]

2. Description of the Related Art Conventionally, when simulating logic written in a programmable device, a simulation input pattern to a circuit to be verified and a signal generation model for comparison with an output of the circuit to be verified are required. Therefore, a great effort was required for a simulation executor to manually input such a simulation input pattern and to prepare a signal generation model. Further, in order to confirm the validity of the input pattern for simulation or the signal generation model prepared in such a case, debugging work is inevitable, and this also requires time and effort.

FIG. 5 shows an ASIC (Applicatio) using an actual operation pattern disclosed in Japanese Patent Application Laid-Open No. H8-292967.
2 is a functional block diagram illustrating a configuration of an (N Specific Integrated Circuit) emulation method and apparatus.

In this conventional example, an FPGA actual operation 113 that holds the actual operation timing of an FPGA (Field Programmable Grid Array) after the ASIC logic is written, and an AS that holds the operation timing that the designer expects from the ASIC.
An operation timing 111 expected from the IC, an operation timing comparison 112 for reading data from the FPGA actual operation 113 and the operation timing 111 expected from the ASIC and comparing operation timings, and a mismatched portion extracting a mismatched portion from the comparison result Extraction 114, mismatched portion correction 116 for correcting or correcting the extracted mismatched portion, correction information 117 for storing information necessary for correction in a library, and F in accordance with the design data and the content of the correction.
It is composed of write data creation 115 for creating write data for PGA, and mismatch information output 118 for outputting information on mismatched portions.

According to the conventional example configured as described above,
The operation timing of the programmable device and the designer
It is described that since the operation timing expected from the SIC is compared, the mismatch of the timing can be automatically detected, the design intention is easily reflected, and the number of preparation steps for the ASIC simulation is reduced.

[0006] Other logic verification methods such as FPGA and P
Emulation for configuring a circuit to be verified in an LD (Programmable Logic Device) and performing verification under actual machine conditions is also performed.

[0007]

As described above, the conventional logic simulator has a problem that it takes time to prepare a simulation input pattern and a signal generation model and to debug them.

Japanese Patent Application Laid-Open No. 8-292927 describes that the disclosed invention reduces the number of man-hours required for a simulation. However, it is not clear how to prepare an actual operation pattern in a simulator. It is not described, and in this respect, it is the same as the previous logic simulator, and again, it takes much time to perform the simulation.

Further, the processing speed of a simulator that has been put into practical use is very slow as compared with the actual machine, and it is difficult to link the actual machine and the simulator body. When trying to match the fast-acting real machine to the simulator speed,
The synchronization of each cycle not only complicates the configuration of the simulator, but also has a problem that the operation status of the actual machine cannot be often confirmed due to speed incompatibility with commercially available measuring instruments.

Further, even if there is a measuring instrument capable of confirming the operation status, the simulation is not performed at the actual operation speed, so that the reliability of the verification result is reduced.

Further, in emulation in which a circuit to be verified is configured in an FPGA or PLD and verification is performed under actual machine conditions, conversion to the FPGA or PLD is required every time the circuit to be verified is corrected, which is inefficient.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and can greatly reduce the number of work steps involved in executing a simulation, and has a simple configuration and high reliability. An object of the present invention is to realize a logic simulator and a logic simulation system capable of obtaining a verification result.

[0013]

A logic simulator according to the present invention provides a circuit under test with an input pattern for operating the circuit under test and compares the operation result with a predetermined signal generation model. A portable measurement unit that generates the input pattern and the signal generation model, and the circuit to be verified are built in, the input pattern generated by the portable measurement unit is supplied to the circuit to be verified, and the output is supplied to the circuit to be verified. A simulator body for outputting the result as simulation information in comparison with the signal generation model generated by the portable measurement unit, a display device for displaying the contents of the simulation information, and an execution instruction indicating operation timing for the simulator body. An output console, and the portable measuring unit is configured to be separable, It is configured to be able to store a signal pattern such as an output of a circuit provided in the input pattern and the signal generation model, the console is a control command for controlling the portable measurement unit when storing the signal pattern. It is characterized by outputting.

In this case, the portable measuring unit samples and inputs a signal pattern such as an output of an externally provided circuit as an input pattern and a signal generation model, and inputs the signal pattern.
A measurement signal sampler that outputs as a patterned signal of
The first patterning signal is temporarily stored, and when the data becomes full or when the data cannot be saved such as when the measurement is completed and the power is turned off, the stored pattern data is read out and the first patterning signal is read out. And a storage memory for storing the second patterned signal, and a storage memory for storing the second patterned signal.

The main memory may include a large-capacity RAM chip and a serial / parallel signal conversion circuit for reading a high-speed signal.

The storage memory may be constituted by a magnetic disk. In any of the above cases, the simulator body receives and distributes the input pattern and the signal generation model generated by the portable measurement unit in addition to the circuit to be verified, which is the object of the simulation. A signal distribution unit to be supplied to a verification circuit, an input of an output of a circuit to be verified to which an input pattern from the signal distribution unit is input, and a signal generation model distributed by the signal distribution unit are input, and the results are compared. And an output expectation value matching unit that outputs the simulation result as simulation information.

A logic simulation system according to the present invention is a logic simulation system comprising any one of the logic simulators described above and an experiment apparatus configured to be combined with a portable measurement unit. Has a prototype circuit with the same function as the circuit under test, and a pre-stage circuit and a post-stage circuit for realizing the same conditions as the usage status of the circuit under test.The portable measurement unit is combined with an experimental device. The output of each of the pre-stage circuit and the prototype circuit at the time of this is stored as an input pattern and a signal generation model.

[Operation] In the present invention configured as described above, the portable measurement unit can be separated from the simulator main body, so that the input / output signals of the prototype circuit configured on the experimental apparatus can be used by the logic simulator. The portable measurement unit can directly store the input test pattern and the output expected value in the portable measurement unit. The stored input test patterns and expected output values can be used as they are in the simulator itself during the execution of the simulation, so that the actual operation can be simulated more easily.

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of a logic simulator according to the present invention. The logic simulator 1 according to the present embodiment includes a portable measuring unit 2 which is a feature of the present invention.
And a simulator 3, a console 4, and a display unit 5. A control command 6 is output from the console 4 to the portable measuring unit 2, and an execution command 7 is output to the simulator body 3.

An input pattern / output expected value 9 for a circuit to be verified is output from the portable measuring section 2 to the simulator body 3, and monitoring information 10 is output to the display device 5. Simulation information 11 is output from the simulator body 3 to the display device 5.

The control command 6, the execution command 7, the read control signal 8, the input pattern / output expected value 9 for the circuit to be verified, the monitoring information 1
0, the simulation information 11 is transmitted by a wired or wireless communication means without being restricted by a distance.

The control command 6 and the execution command 7 output from the console 4 are based on the contents set directly by the apparatus user or indirectly set via storage means or the like. The main body 3 operates according to an execution command 7 output from the console 4. The simulator body 3 has a built-in circuit to be verified to be simulated, and is to be verified based on the operation result of the circuit to be verified and the input pattern / output expected value 9 for the circuit to be verified which is output from the portable measurement unit 2. Simulation information 11 indicating whether the operation result of the circuit is as expected is generated.

The portable measuring section 2 is configured to be separable from the simulator body 3. The method of use will be described. As shown in FIG. 4, a portable measuring unit 2 is connected to a prototype circuit 35 on an experimental device 34 having the same function as the circuit to be verified incorporated in the simulator body 3. First, an actual operation pattern is obtained from the measurement signal 15 of the experimental apparatus 34 and stored. After this,
As shown in FIG. 1, the portable measuring unit 2 is
The actual operation pattern saved by connecting to the portable measurement unit 2
And simulate using the actual operation pattern.

FIG. 2 shows the logic simulator 1 shown in FIG.
FIG. 3 is a block diagram showing in detail a configuration of a portable measurement unit 2 that is a part of the measurement unit.

The portable measuring section 2 comprises a measurement signal sampler 12 for sampling a measurement signal 15, a main memory 13, and a storage memory 14. A measurement signal 15 is input to the measurement signal sampler 12 from outside the logic simulator 1. The control command 6 from the console 4 is a composite of various control signals of each unit constituting the portable measuring unit 2, and the measurement signal sampler 1 is provided inside the portable measuring unit 2.
2, a write / read control instruction 17 for instructing writing and reading of a pattern in the main memory 13, and a write control instruction 18 for instructing writing in the storage memory 14. Are input to the measurement signal sampler 12, the main memory 13, and the storage memory 14, respectively.

The measurement signal sampler 12 outputs sampling status monitoring information 19 indicating the sampling status of the measurement signal, and the main memory 13 outputs the writing / reading status monitoring information 20 indicating the writing status and the reading status. The storage memory 14 has write / read status monitoring information 21 indicating a write status.
These are collected as monitoring information 10 inside the portable measuring unit 2 and sent to the display device 5.

A patterning signal 22 generated by sampling the measurement signal 15 is sent from the measurement signal sampler 12 to the main memory 13 as the written content, and the patterning signal 22 is sent from the main memory 13 to the storage memory 14. 23 is sent out as the written content. Further, a read control signal 8 for controlling a read state from the simulator body 3 (see FIG. 1) is input to the storage memory 14, and the stored contents are stored in the storage memory 14 in accordance with the read control signal 8 for the circuit to be verified. The input pattern / output expected value 9 is sent to the simulator body 3.

FIG. 3 is a block diagram showing in detail the configuration of the simulator body 3 which is a part of the logic simulator 1 of FIG.

In FIG. 3, the simulator body 3 comprises a circuit under test 24 to be simulated, an execution control unit 25, a signal distribution unit 26, and an expected output value comparison unit 27. The execution command 7 from the console 4 is input to the execution control unit 25, and the execution control unit 25 reads the read control signal 8 and the operation timing signal 2 according to the content of the execution command 7.
8 are sent to the portable measuring unit 2 (see FIG. 1) and the circuit under test 24, respectively.

The input pattern / output expected value 9 for circuit verification under test sent from the portable measuring unit 2 is input to the signal distribution unit 26. The signal distribution unit 26 sends the input pattern indicated by the input pattern / output expected value 9 for the circuit to be verified as the input-side pattern signal 29 to the circuit 24 to be verified, and the input pattern / output expected value for the circuit to be verified. The expected value pattern 30 (signal generation model) shown in FIG.
Send to

As described above, the operation timing signal 28 from the execution control unit 25 is sent to the circuit under test 24, and the input-side pattern signal 29 is sent from the signal distribution unit 26. The circuit under test 24 performs an operation based on the input-side pattern signal 29 at the timing of the operation timing signal 28, and sends an output-side pattern signal 31 indicating the operation result to the output expectation value comparison unit 27.

The output expected value matching section 27 compares the output side pattern signal 31 with the expected value pattern 30 and outputs expected value matching result information 32 indicating the comparison result. On the other hand, from the circuit under test 24, the execution control unit 25, and the output expected value matching unit 27, in addition to the above-described signals, execution status information 33 indicating the respective operating status is output.
2 and the execution status information 33 are combined and sent to the display device 5 as the simulation information 11.

Next, the use procedure and operation of the present embodiment will be described.

In order to execute a simulation using the logic simulator 1 shown in FIG. 1, a circuit to be verified 24 (see FIG. 3) must be prepared in the simulator body 3 and a test pattern for the simulation must be prepared. Here, as a feature of the logic simulator 1 of the present embodiment, the portable measurement unit 2 is provided, the measurement signal 15 is taken in from the outside of the logic simulator 1 by the portable measurement unit 2, and the measurement signal 15 is used for a test pattern. Has a function.

FIG. 4 is a diagram showing a connection example of a method for taking in the measurement signal 15 from outside the logic simulator 1, and shows a state in which the logic simulator 1 is connected to an external experiment apparatus.

In FIG. 4, an experimental apparatus 34 includes a prototype circuit 35 designed with the same specifications as the circuit under test 24 to be simulated, and a pre-stage circuit for realizing the same conditions as the usage conditions of the circuit 24 under test. 36 and post-stage circuit 37
And a measuring device 38 for detecting the output of the post-stage circuit 37. In addition to the input signal 39 to the prototype circuit 35 and its output signal 40, the monitoring information 41 and 42 obtained from the pre-stage circuit 36, the post-stage circuit 37, and the measuring device 38 are used as the measurement signal 15
And sent to the portable measuring unit 2.

The input signal 39 output from the pre-stage circuit 36 is
The contents of the input-side pattern signal 29 output to the circuit under test 24 at the time of the simulation shown in FIG. 1 are obtained, and the output signal 40 is output to the output expected value comparison unit 30 at the time of the simulation shown in FIG. This is the content of the value pattern 30.

When the control command 6 to start the measurement is sent from the console 4 of the logic simulator 1, the portable measuring unit 2
Reads the input signal 39 and the output signal 40 of the prototype circuit 35 while checking the monitoring information 41 and 42 of each unit of the experimental apparatus 34 included in the measurement signal 15. Portable measuring unit 2
The input signal 39 and the output signal 40 which are taken in are converted into digital signals by the measurement signal sampler 12 shown in FIG.

Here, the logic simulator 1 of the present embodiment
Since the portable measuring unit 2 is configured to be separable from the simulator body 3 and can be placed near the experimental apparatus 34, the above-described reading operation can be easily performed. Also in this case, since the control command 6 can be received from the remote console 4 by the communication means and the monitoring information 10 can be sent to the display device 5, the measurer does not need to be near the experimental device 34.

The main memory 13 is composed of a large-capacity RAM chip and a combination of a serial / parallel signal conversion circuit and the like so that a high-speed signal can be read. The main memory 13 reads out the stored pattern data and uses it as a patterning signal 23 when the data becomes full or when the measurement is completed and the data cannot be saved due to power-off, for example, using a magnetic disk or the like. The data is sent to the storage memory 14 and stored again.

As described above, the test pattern is taken in from the experimental device 34 provided outside.

Next, a procedure for simulating the circuit under test 24 by the simulator body 3 will be described.

When executing a simulation, as in the logic simulator 1 shown in FIG. 1, the portable measuring unit 2 is connected to the simulator body 3 and a read control signal 8 is connected between them.
And the input pattern / output expected value 9 for the circuit under test simulation. Even in this case, the control command 6 and the monitoring information 10 can be transmitted between the portable measuring unit 2, the console 4, and the display device 5.

At the start of the simulation, the device user
First, an execution command 7 is instructed from the console 4 to the simulator body 3. Here, as shown in FIG. 3, the execution instruction 7 is input to the execution control unit 25 inside the simulator body 3,
The execution control unit 25 generates the read control signal 8 and the operation timing signal 28 to start the simulation. The read control signal 8 is input to the storage memory 14 in the portable measuring unit 2 as shown in FIG. 2, and the input pattern / output expected value 9 for the circuit to be verified is output from the storage memory 14 to the simulator main body 3 in FIG. The signal is output to the internal signal distribution unit 26, and the input side pattern signal 29 and the expected value pattern 3 are output.
Distributed to zero.

As described above, the operation timing signal 28 and the input side pattern signal 29 are given to the circuit to be verified 24 to perform a simulation, and the circuit to be verified 24 sends out the output side pattern signal 31. This output side pattern signal 31
And the expected value pattern 30 sent from the signal distribution unit 26, the expected value matching result information 32
Is obtained.

In addition to the expected value collation result information 32, the simulation information 11 including the execution status information 33 obtained from the circuit under test 24, the execution control unit 25, and the output expected value collation unit 27 is sent to the display device 5. By viewing the display contents of the display device 5, the user can confirm the simulation execution status and the result of the logic verification (the quality of the circuit under test 24).

[0048]

Since the present invention is configured as described above, it has the following effects.

A portable measuring unit is provided, which is separated from the simulator body and connected to a prototype circuit on an experimental device, for example, so that the actual operation signal whose validity is confirmed is directly sent to the logic simulator as a test pattern. Therefore, even in the case of simulating a circuit under test having the same function as in the case where a prototype circuit is made into an LSI, a simulation executor manually inputs a test pattern or prepares a signal generation model and connects the circuit to the circuit under test. The operation is not required, and it is only necessary to instruct, from the console of the simulator body, an execution instruction for reading the input pattern / output expected value for the circuit to be verified from the portable measurement unit.

In addition, it becomes unnecessary to manually input a test pattern by a simulation executor or to debug a test pattern or a signal generation model itself, which is inevitable when a signal generation model is prepared. Can be greatly reduced.

As described above, there is an effect that the number of work steps related to the execution of the simulation can be greatly reduced.
Further, since the device configuration is very close to the actual layer value configuration, there is an effect that a highly reliable verification result can be obtained with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a portable measuring unit 2 in FIG. 1 in detail.

FIG. 3 is a block diagram showing a configuration of a simulator 3 in FIG. 1 in detail.

FIG. 4 is a block diagram showing a connection example between the logic simulator 1 and an external experimental device.

FIG. 5 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Logic simulator 2 Portable measurement part 3 Simulator main body 4 Operation console 5 Display device 6 Control instruction 7 Execution instruction 8 Read control signal 9 Input / output expected value for circuit to be verified 10 Monitoring information 11 Simulation information 12 Measurement signal sampler 13 Main Memory 14 Storage memory 15 Measurement signal 16 Sampling control command 17 Write / read control command 18 Write control command 19 Sampling status monitor information 20, 21 Write / read status monitor information 22, 23 Patterned signal 24 Circuit to be verified 25 Execution control Unit 26 signal distribution unit 27 output expected value comparison unit 28 operation timing signal 29 input-side pattern signal 30 expected value pattern 31 output-side pattern signal 32 expected value comparison result information 33 execution status information 34 experimental apparatus 35 prototype circuit 36 pre-stage circuit 37 post-stage Circuit 3 8 Measuring instrument 39 Input signal 40 Output signal 41, 42 Monitoring information

Claims (6)

[Claims] 1. A logic simulator for providing an input pattern for operating a circuit under test to a circuit under test, and comparing the operation result with a predetermined signal generation model, wherein the input pattern and the signal generation model are generated. A portable measuring unit that incorporates the circuit to be verified, supplies the input pattern generated by the portable measuring unit to the circuit to be verified, and compares its output with a signal generation model generated by the portable measuring unit. A simulator that outputs the result as simulation information, a display device that displays the contents of the simulation information, and a console that outputs an execution instruction indicating an operation timing to the simulator body. The portable measurement unit is configured to be separable, and the signal pattern such as the output of an external circuit is provided. The is configured to be stored as the input pattern and signal generation model, the operator console, the logic simulator and outputs a control command for controlling the time of signal patterns stored in the portable measuring unit. 2. The logic simulator according to claim 1, wherein the portable measurement unit samples and inputs a signal pattern such as an output of a circuit provided outside as an input pattern and a signal generation model, and inputs the first pattern. A measurement signal sampler that outputs as a structured signal, temporarily stores the first patterned signal, and when data becomes full, or when measurement is completed and data cannot be saved such as when power is turned off, A logic simulator, comprising: a main memory that reads stored pattern data and outputs the read data as a second patterned signal; and a storage memory that stores the second patterned signal. 3. The logic simulator according to claim 2, wherein the main memory includes a large-capacity RAM chip and a serial / parallel signal conversion circuit for reading a high-speed signal. 4. The logic simulator according to claim 2, wherein the storage memory comprises a magnetic disk. 5. The logic simulator according to claim 1, wherein the simulator body includes an input pattern and a signal generation model generated by a portable measurement unit, in addition to a circuit to be verified as a simulation target. And a signal distribution unit for supplying these to the circuit to be verified with respect to an input pattern, and an output of the circuit to be verified that has received the input pattern from the signal distribution unit and a signal distributed by the signal distribution unit. A logic simulator, comprising: an output model input unit; an output model comparison unit that inputs an occurrence model, compares the input models, and outputs the result as simulation information. 6. A logic simulation system comprising the logic simulator according to claim 1 and an experiment device configured to be able to be combined with a portable measurement unit, wherein the experiment device is , A prototype circuit having the same function as the circuit under test, and a pre-stage circuit and a post-stage circuit for realizing the same conditions as the usage conditions of the circuit under test, and the portable measurement unit was combined with the experimental device. A logic simulation system characterized in that the outputs of the pre-stage circuit and the prototype circuit are stored as input patterns and signal generation models.