JP2004348596A - Device, method and program for debugging ic tester program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform the debugging operation of an IC tester program by constructing a virtual IC tester having a simple structure and high versatility. <P>SOLUTION: The debugging device for the IC tester program comprises a test information extraction means 2 for extracting test information including the operation setting and test standard information of the IC tester from the IC tester program for controlling the operation of the IC tester connected to a performance board on which an IC to be tested is mounted and capable of testing the IC to be tested, a net list generation means 7 for generating a net list to be used for a simulator for simulating the operation of the IC tester from the operation setting information of the IC tester and the circuit information of the IC to be tested and the performance board, and a determination means 11 for comparing the execution result of the virtual circuit based on the net list with a test standard based on the test standard information and determining whether the execution result satisfies the test standard or not. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an IC tester program debugging apparatus, method, and program having excellent versatility.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, manufactured ICs (integrated circuits) have been inspected using an IC inspection apparatus (IC tester). FIG. 5 is a block diagram showing the configuration of such an IC inspection device.
[0003]
The inspected IC 61 to be inspected is mounted on the performance board 62. Each pin of the IC 61 to be inspected is connected to each terminal of the IC tester 63 via each terminal of the performance board. The IC tester 63 includes a signal source 64, a measuring device 65, a control signal generator 66 for a performance board, a memory 67, and a control section 68.
[0004]
The IC tester 63 is supplied with an IC tester program from the external storage device 69, and the control unit 68 performs an IC test according to the IC tester program. That is, the control section 68 controls the signal source 64 to generate a signal necessary for inspection and supply the signal to the IC 61 to be inspected. The inspected IC 61 generates a response output according to the input signal.
[0005]
The output of the IC under test 61 is supplied directly to the measuring device 65 or is supplied to the measuring device 65 in accordance with the performance board control signal from the performance board control signal generator 66. The measuring device 65 supplies the measurement result of the output of the IC under test 61 to the control unit 68. The control unit 68 uses the memory 67 to determine whether the IC 61 is good or bad, a defective part, or the like based on the measurement result of the measuring device 65 according to the IC tester program.
[0006]
By using an appropriate program as an IC tester program, an accurate inspection of the IC 61 to be inspected becomes possible. In other words, unless an IC tester program having no bug is used, an accurate inspection of the IC to be inspected cannot be performed. However, it is difficult to determine that there is no bug in the IC tester program to be used before manufacturing the IC to be inspected. That is, the debugging work for finding a defect in the program for the IC tester and responding to the problem is performed after the IC to be inspected and the performance board are manufactured, and the performance board on which the IC to be inspected is mounted is connected to the IC tester. This is only possible by executing the IC tester program.
[0007]
Therefore, debugging of the IC tester program cannot be started until the IC to be inspected or the performance board is manufactured. Also, in the initial stage of debugging, even if an operation not intended by the test designer occurs, it is not possible to specify whether the cause is the IC under test, the performance board, or the program for the IC tester. Is extremely difficult.
[0008]
Japanese Patent Application Laid-Open No. 9-185519 discloses a technique in which a virtual model of an IC tester is created so that the IC tester can be simulated by a simulator or the like. That is, in this proposal, a virtual IC tester model is developed by developing a model of a virtual IC tester on a general-purpose computer and simulating the IC tester by a program.
[0009]
In this case, on a general-purpose computer, simulation is performed by applying an actual IC tester program to a model of a virtual IC tester, and on a general-purpose computer, an IC dedicated to the virtual IC tester is added to a model of the virtual IC tester. Some simulations are performed by applying a tester program.
[0010]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 9-185519
[Problems to be solved by the invention]
As described above, the virtual IC tester is realized by reading an IC tester program into a model of the virtual IC tester on a general-purpose computer. The operation of the IC tester is simulated by the virtual IC tester, thereby enabling the debug work of the IC tester program.
[0012]
However, the program for the IC tester and the model of the virtual IC tester are adapted only to a specific IC tester, and a general-purpose virtual IC tester cannot be constructed. Moreover, the model of the virtual IC tester is extremely complicated, and the production of the virtual IC tester adapted to various IC testers requires enormous labor.
[0013]
The model of the IC tester is created according to the language and grammar of the program for the IC tester. FIG. 6 shows the correspondence between the model of the virtual IC tester and the program for the IC tester. As shown in FIG. 6, the program for the IC tester A and the circuit information of the IC to be inspected and the performance board are applied to the model A of the virtual IC tester, and the IC tester is applied to the model B of the virtual IC tester. It shows that the B program and the circuit information of the IC under test and the performance board are applied.
[0014]
That is, for the same virtual IC tester, it is necessary to apply an IC tester program with the same grammar, and when writing an IC tester program with a different grammar, it is necessary to prepare a virtual IC tester adapted to the grammar. There is. Therefore, development of each virtual IC tester requires an enormous amount of time and cost.
[0015]
The present invention has been made in view of such a problem, and realizes debugging of an IC tester program without applying the IC tester program to an IC tester model on a general-purpose computer and executing the program. It is an object of the present invention to provide an IC tester program debugging device, method, and program that can be used with a plurality of types of IC testers by an IC tester.
[0016]
[Means for Solving the Problems]
An IC tester program debugging device according to the present invention includes an IC tester program for controlling an operation of an IC tester connected to a performance board on which an IC to be inspected is mounted and inspecting the IC to be inspected. The test information extracting means for extracting test information including the information on the operation setting and the test standard of the IC tester, the information on the operation setting of the IC tester, and the circuit information of the IC to be inspected and the performance board are obtained from the IC tester. Netlist generation means for generating a netlist used in a simulator for simulating operation; comparing the execution result of the virtual circuit based on the netlist with a test standard based on the information of the test standard; Determining means for determining whether or not the test standard is satisfied.
In addition, the method for debugging an IC tester program according to the present invention includes an IC tester program for controlling an operation of an IC tester that is connected to a performance board on which an IC to be inspected is mounted and performs inspection of the IC to be inspected. Extracting the test information including the information on the operation setting of the IC tester and the test standard, and the operation of the IC tester from the information on the operation setting of the IC tester and the circuit information of the IC under test and the performance board. A process of generating a netlist used for a simulator that simulates the above, a result of execution by a virtual circuit based on the netlist, and a test standard based on the information of the test standard are compared, and the execution result satisfies the test standard. Processing to determine whether or not to perform
Further, the debug program of the IC tester program according to the present invention is an IC tester for controlling the operation of an IC tester which is connected to a performance board on which a test IC is mounted and which tests the test IC. Extracting the test information including the information on the operation setting of the IC tester and the test standard from the application program, and the information on the operation setting of the IC tester, and the circuit information of the IC under test and the performance board. A process of generating a netlist used in a simulator for simulating the operation of the tester, a result of execution by a virtual circuit based on the netlist, and a test standard based on the information of the test standard are compared. Determining whether or not the standard is satisfied.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an apparatus for debugging a program for an IC tester according to the first embodiment of the present invention.
[0018]
This embodiment does not produce a modeled virtual IC tester, but creates a netlist from circuit information of an IC to be inspected and a performance board to which the IC to be inspected is conventionally used for IC inspection. By applying an IC tester program to a virtual circuit obtained from this netlist, a virtual IC tester that enables simulation of IC inspection is constructed. In this embodiment, the virtual IC tester 13 is realized by hardware.
[0019]
The device for debugging an IC tester program according to the present embodiment includes a virtual IC tester 13, a storage unit 1 for storing an IC tester program to be debugged, and a storage unit 6 for storing circuit information. The IC tester program includes tester operation setting data and test standard data. Further, the tester operation setting data includes setting of test conditions for each pin of the IC under test simulated by the virtual IC tester 13 and setting of signals to be applied. Includes information for The test standard data indicates a standard value of an IC inspection to be compared with a simulation result by a virtual IC tester using the tester operation setting data. The circuit information stored in the storage unit 6 includes information on the circuit of the IC to be inspected and information on the circuit of the performance board on which the IC to be inspected is mounted.
[0020]
The test information extraction unit 2 in the virtual IC tester 13 accesses the storage unit 1 and extracts data such as tester operation settings and test standards described in an IC tester program that controls the operation of the IC tester. The test information extraction unit 2 is configured to provide the extracted test standard data and tester operation setting data to the storage units 3 and 4 in the test information storage unit 5 and store them.
[0021]
The net list generation unit 7 reads out the circuit information from the storage unit 6 and the tester operation setting data from the test information storage unit 5, and generates a net list for simulation. If a complete virtual circuit is constructed using all of the circuit information and the tester setting data is applied thereto, the amount of calculation in the simulation will be enormous. Thus, in the present embodiment, the amount of simulation calculation is reduced by constructing only a virtual circuit suitable for each test item for each test item using the tester operation setting data. .
[0022]
The netlist generation unit 7 gives the generated netlist to the netlist storage unit 8 and stores it. The netlist storage unit 8 supplies the stored simulation netlist to the simulator 9.
[0023]
The simulator 9 executes a simulation using the input simulation netlist. The simulation result of the simulator 9 is given to the result data storage unit 10. The result data storage unit 10 holds the input result data and outputs the result data to the determination unit 11.
[0024]
The determination unit 11 compares the simulation result data from the result data storage unit 10 with the test standard data stored in the test information storage unit 5 to determine whether the simulation execution result satisfies the test standard. The judgment is made. The controller 12 controls each part of the virtual tester 13.
[0025]
Next, the operation of the embodiment configured as described above will be described with reference to FIG. FIG. 2 is a flowchart showing the operation of the first embodiment.
[0026]
The program for the IC tester to be debugged is stored in the storage unit 1, and the circuit information including the information on the circuit of the IC to be tested and the circuit of the performance board on which the IC to be tested is mounted is stored in the storage unit 6. I do.
[0027]
In step S21 of FIG. 2, the test information extraction unit 2 is controlled by the controller 12 to read the IC tester program from the storage unit 1 into the virtual IC tester 13, and reads the tester operation setting data and the test standard from the IC tester program. Test information such as data is extracted (step S22). The test information extraction unit 2 gives the extracted test standard data and tester operation setting data to the test information storage unit 5 and stores them (step S23).
[0028]
Next, the controller 12 sets test items to be simulated by the virtual IC tester 13 (Step S24). The netlist generation unit 7 reads out the tester operation setting data corresponding to the set test item from the test information storage unit 5 and also reads out the circuit information from the storage unit 6, and based on the tester setting data and the circuit information, A net list is generated (Step S25). The generated netlist is supplied to and stored in the netlist storage unit 8 (step S26).
[0029]
The simulator 9 is controlled by the controller 12 to execute a simulation based on the netlist stored in the netlist storage unit 8 (Step S27). The data of the execution result of the simulation by the simulator 9 is stored in the result data storage unit 10 as simulation result data (step S28).
[0030]
In the next step S29, the test standard data stored in the test information storage unit 5 and the simulation result data stored in the result data storage unit 10 are compared by the determination unit 11, and the simulation execution result satisfies the test standard. Is determined.
[0031]
In step S30, it is determined whether the test item set in step S24 is the last test item to be simulated. If it is the last test item, the operation is terminated (step S31); otherwise, the process returns to step S24 to repeat the same operation for the next test item.
[0032]
Thereafter, these series of operations are performed until the end of the test item. If the judgment by the judging unit 11 indicates that all the test items satisfy the test standards, the test conditions and test standards for each test item are properly described as an IC tester program. Can be determined. If there is a test item that is determined not to meet the test standard, it is determined that the description of the test condition and test standard for the test item in the IC tester program is inappropriate. Can be. In this case, the flow of FIG. 2 is executed after correcting the description of the part determined to be inappropriate in the IC tester program. Thereafter, the same processing is repeated until it is obtained that all the test items satisfy the test standard.
[0033]
As described above, in the present embodiment, instead of simulating the operation of the IC tester in the form of an IC tester program, information necessary for verifying the operation of the IC tester including the IC under test and the performance board is obtained. Since the operation of the IC tester is extracted and simulated, there is no need to develop the IC tester program and the IC tester model on a general-purpose computer. That is, it is not necessary to construct a complicated virtual IC tester model for each IC tester, and a simple and highly versatile virtual IC tester using existing circuit information of the IC under test and the performance board can be constructed. The versatility of test results can be improved.
[0034]
3 and 4 relate to a second embodiment of the present invention. FIG. 3 is a block diagram showing an IC tester program debugging device according to the second embodiment. FIG. 4 is a block diagram showing the second embodiment. 9 is a flowchart showing the operation of the embodiment. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
[0035]
In the present embodiment, debugging of a plurality of IC tester programs described in different languages or grammars can be realized using a common virtual IC tester.
[0036]
The storage unit 41 stores the program for the IC tester A, and the storage unit 51 stores the program for the IC tester B. The IC tester A and the IC tester B are different types of IC testers, and the program for the IC tester A and the program for the IC tester B are described in mutually different syntaxes.
[0037]
The virtual IC tester 40 of FIG. 3 employs a test information extraction unit 42 for IC tester A and a test information extraction unit 52 for IC tester B instead of the test information extraction unit 2 in the virtual IC tester 13 of FIG. It is. The IC tester A test information extraction unit 42 extracts data such as tester operation settings and test standards described in an IC tester A program for controlling the operation of the IC tester A. The information extracting unit 52 extracts data such as tester operation settings and test standards described in a program for the IC tester B that controls the operation of the IC tester B. The test standard data and the tester operation setting data extracted by the IC tester A test information extractor 42 and the IC tester B test information extractor 52 are given to the accumulators 3 and 4, respectively, and are accumulated.
[0038]
Next, the operation of the embodiment configured as described above will be described with reference to the flowchart of FIG. In FIG. 4, the same steps as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.
[0039]
The flow of FIG. 4 differs from the flow of FIG. 2 in that the process of step S60 for selecting one of the program for the IC tester A and the program for the IC tester B is added. The operations after the IC tester program is selected (steps S21 to S31) are the same as those in the first embodiment.
[0040]
That is, in step S60, the controller 12 operates one of the IC tester A test information extraction unit 42 and the IC tester B test information extraction unit 52 to execute the IC tester A program or the IC tester B program. Read. Test information is extracted from the read IC tester A program or IC tester B program and stored in the storage units 3 and 4. Subsequent operations are the same as in the first embodiment.
[0041]
By executing the series of flows in FIG. 4 until the end of the test items, it is determined whether the test conditions and test standards for each test item are properly described as an IC tester program, as in the first embodiment. Can be determined. If it is determined that the read IC tester program is not properly described, the debugged IC tester program is corrected, and the processing after step S60 is performed again to confirm that all the test items are correct. The process is repeated until the determination is made.
[0042]
As described above, in this embodiment, the same effects as those of the first embodiment can be obtained, and the IC tester test for extracting information such as tester operation settings and test standards described in the IC tester program. By preparing a plurality of types of information extraction units, debugging work of a plurality of types of IC tester programs having different languages and grammars can be performed. That is, even when the language and grammar of the IC tester program are different, there is no need to design a virtual IC tester for each IC tester program, and the development time and cost of the virtual IC tester can be significantly reduced. As a result, the test designer can describe the program for the IC tester in a program format familiar to the handling, and the versatility can be improved.
[0043]
It is to be noted that each configuration in each of the above embodiments can be variously modified and changed. For example, the netlist generation unit 7 and the simulator 9 may be directly connected without storing the netlist output from the netlist generation unit 7 in the netlist storage unit 8.
[0044]
Further, it may be connected to a storage unit for storing information output from the determination unit 11 or a display unit such as a monitor and a printer.
[0045]
Although the above embodiments have been described with reference to the hardware configuration, it is needless to say that the embodiments may be implemented as software (programs) based on the flowchart in FIG. 2 or FIG.
[0046]
【The invention's effect】
As described above, according to the present invention, debugging of an IC tester program can be realized without applying an IC tester program to an IC tester model on a general-purpose computer and executing the program. Has the effect of being able to correspond to the IC tester.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a debugger for an IC tester program according to a first embodiment of the present invention.
FIG. 2 is a flowchart showing the operation of the first embodiment.
FIG. 3 is a block diagram showing an IC tester program debug device according to a second embodiment;
FIG. 4 is a flowchart showing the operation of the second embodiment.
FIG. 5 is a block diagram showing a configuration of an IC inspection device.
FIG. 6 is an explanatory diagram showing the correspondence between a virtual IC tester model and an IC tester program.
[Explanation of symbols]
1, 6, 3, 4,..., A storage unit, 2, a test information extraction unit, 7 a net list generation unit, 9 a simulator, 11 a determination unit, 12 a controller

Claims (6)

A test including an operation setting of the IC tester and information on a test standard from an IC tester program for controlling the operation of the IC tester connected to the performance board on which the IC to be mounted is mounted and inspecting the IC to be tested. Test information extracting means for extracting information;
A netlist generating means for generating a netlist used for a simulator for simulating the operation of the IC tester from the information on the operation setting of the IC tester and the circuit information of the IC under test and the performance board;
Determining means for comparing an execution result of the virtual circuit based on the netlist with a test standard based on the information of the test standard, and determining whether the execution result satisfies the test standard;
An apparatus for debugging a program for an IC tester, comprising: 2. The device according to claim 1, wherein a plurality of the test information extracting means are provided corresponding to various IC testers corresponding to the plurality of IC tester programs. A test including an operation setting of the IC tester and information on a test standard from an IC tester program for controlling the operation of the IC tester connected to the performance board on which the IC to be mounted is mounted and inspecting the IC to be tested. Processing to extract information;
A process of generating a netlist used for a simulator for simulating the operation of the IC tester from the information on the operation setting of the IC tester and the circuit information of the IC under test and the performance board;
Comparing the execution result by the virtual circuit based on the netlist with a test standard based on the information of the test standard, and determining whether the execution result satisfies the test standard;
A method for debugging a program for an IC tester, comprising: 4. The method according to claim 3, wherein the extraction of the test information is performed for each of various IC testers corresponding to the plurality of IC tester programs. On the computer,
A test including an operation setting of the IC tester and information on a test standard from an IC tester program for controlling the operation of the IC tester connected to the performance board on which the IC to be mounted is mounted and inspecting the IC to be tested. Processing to extract information;
A process of generating a netlist used for a simulator for simulating the operation of the IC tester from the information on the operation setting of the IC tester and the circuit information of the IC under test and the performance board;
Comparing the execution result by the virtual circuit based on the netlist with a test standard based on the information of the test standard, and determining whether the execution result satisfies the test standard;
Debug program for the IC tester program for executing the program. 6. The program according to claim 5, wherein the extraction of the test information includes a process performed for each of various IC testers corresponding to the plurality of IC tester programs.

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