CN118069441A

CN118069441A - Test vector file conversion method, device, computer equipment and storage medium

Info

Publication number: CN118069441A
Application number: CN202410154570.XA
Authority: CN
Inventors: 洪志伟; 李超超; 朱鹏; 宋威
Original assignee: Hexin Technology Co ltd; Shanghai Hexin Digital Technology Co ltd
Current assignee: Hexin Technology Co ltd; Shanghai Hexin Digital Technology Co ltd
Priority date: 2024-02-02
Filing date: 2024-02-02
Publication date: 2024-05-24

Abstract

The application relates to a test vector file conversion method, a test vector file conversion device, a test vector file conversion computer device, a test vector file conversion storage medium and a test vector file conversion computer program product. The method comprises the following steps: acquiring a first test vector file aiming at equipment to be tested in a simulation environment; identifying content information and timing information of each signal from the first test vector file; generating a clock block and a data block of each signal according to the content information and the time sequence information of each signal; the clock block at least comprises time sequence information of each signal, and the data block of each signal at least comprises corresponding signal waveform text data; generating a second test vector file for the device to be tested according to the clock block and the data block of each signal; the file format of the second test vector file is different from the file format of the first test vector file, and the file format of the second test vector file is matched with the current automatic test equipment for the equipment to be tested. By adopting the method, the equipment testing accuracy can be improved.

Description

Test vector file conversion method, device, computer equipment and storage medium

Technical Field

The present application relates to the field of computer technology, and in particular, to a test vector file conversion method, apparatus, computer device, storage medium, and computer program product.

Background

After the design of a device (e.g., a chip) is completed, it needs to be tested for functionality and reliability in order to ensure that the device meets quality standards and specifications.

In the conventional technology, when testing equipment, ATE (Automatic Test Equipment ) is mainly used for testing, and a test vector file used by the test vector file is in a fixed file format; however, if the test vector files supported by different ATE are different in file format, the test vector files with the same fixed file format are adopted for different ATE, which results in lower accuracy of the obtained device test result and lower device test accuracy.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a test vector file conversion method, apparatus, computer device, computer readable storage medium, and computer program product that can improve the accuracy of device testing.

In a first aspect, the present application provides a test vector file conversion method, including:

acquiring a first test vector file aiming at equipment to be tested in a simulation environment;

identifying content information and timing information of each signal from the first test vector file;

Generating a clock block and a data block of each signal according to the content information and the time sequence information of each signal; the clock block at least comprises time sequence information of each signal, and the data block of each signal at least comprises corresponding signal waveform text data;

generating a second test vector file for the device to be tested according to the clock block and the data block of each signal; the file format of the second test vector file is different from the file format of the first test vector file, and the file format of the second test vector file is matched with the current automatic test equipment for the equipment to be tested.

In one embodiment, the identifying the content information and the timing information of each signal from the first test vector file includes:

identifying an objective function associated with each signal from the first test vector file;

and identifying the content information and the time sequence information of each signal from the objective function associated with each signal.

In one embodiment, the identifying the content information and the timing information of each signal from the objective function associated with each signal includes:

inputting the objective function associated with each signal into a pre-trained content information identification model to obtain the content information of each signal;

And respectively inputting the objective function associated with each signal into a pre-trained time sequence information identification model to obtain the time sequence information of each signal.

In one embodiment, the generating the clock block and the data block of each signal according to the content information and the timing information of each signal includes:

generating a clock block according to the reference time sequence information and the time sequence information of each signal; the reference time sequence information is extracted from the first test vector file;

generating a signal identifier and signal waveform text data corresponding to each signal according to the content information and the time sequence information of each signal;

and generating a data block of each signal according to the signal identifier and the signal waveform text data corresponding to each signal.

In one embodiment, the generating the signal identifier and the signal waveform text data corresponding to each signal according to the content information and the time sequence information of each signal includes:

extracting signal definition and key content information of each signal from the content information of each signal;

Defining the signal of each signal, and confirming the signal identification corresponding to each signal;

and generating signal waveform text data corresponding to each signal according to the key content information and the time sequence information of each signal.

In one embodiment, the generating a second test vector file for the device under test according to the clock block and the data block of each signal includes:

Acquiring a pre-established test vector file structure; the test vector file structure comprises a clock block area and a data block area of each signal; the pre-created test vector file structure is a test vector file structure matched with the current automatic test equipment;

And adding the clock block into the clock block area, and respectively adding the data block of each signal into the data block area of each signal to obtain a test vector file corresponding to the test vector file structure, wherein the test vector file corresponds to the test vector file structure and is used as a second test vector file for the equipment to be tested.

In one embodiment, before generating the second test vector file for the device under test according to the clock block and the data block of each signal, the method further includes:

creating a clock block area and a data block area of each signal;

And combining the clock block area and the data block area of each signal according to a preset combination sequence to obtain a test vector file structure matched with the current automatic test equipment, wherein the test vector file structure is used as the pre-created test vector file structure.

In a second aspect, the present application further provides a test vector file conversion device, including:

the file acquisition module is used for acquiring a first test vector file aiming at the equipment to be tested in the simulation environment;

The information identification module is used for identifying the content information and the time sequence information of each signal from the first test vector file;

an information processing module, configured to generate a clock block and a data block of each signal according to the content information and the timing information of each signal; the clock block at least comprises time sequence information of each signal, and the data block of each signal at least comprises corresponding signal waveform text data;

The file generation module is used for generating a second test vector file aiming at the equipment to be tested according to the clock block and the data block of each signal; the file format of the second test vector file is different from the file format of the first test vector file, and the file format of the second test vector file is matched with the current automatic test equipment for the equipment to be tested.

In a third aspect, the present application also provides a computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:

In a fourth aspect, the present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:

In a fifth aspect, the application also provides a computer program product comprising a computer program which, when executed by a processor, performs the steps of:

According to the test vector file conversion method, the device, the computer equipment, the storage medium and the computer program product, the first test vector file aiming at the equipment to be tested in the simulation environment is obtained, the content information and the time sequence information of each signal are identified from the first test vector file, then a clock block and a data block of each signal are generated according to the content information and the time sequence information of each signal, the clock block at least comprises the time sequence information of each signal, the data block of each signal at least comprises corresponding signal waveform text data, finally a second test vector file aiming at the equipment to be tested is generated according to the clock block and the data block of each signal, the file format of the second test vector file is different from the file format of the first test vector file, and the file format of the second test vector file is matched with the current automatic test equipment aiming at the equipment to be tested; in this way, in the process of generating the second test vector file, on the basis of the first test vector file of the equipment to be tested in the acquired simulation environment, the current automatic test equipment of the equipment to be tested is comprehensively considered, and the first test vector file is favorably converted into the second test vector file matched with the current automatic test equipment, so that the equipment test result obtained based on the current automatic test equipment is more accurate, the equipment test accuracy is further improved, and the defects that the accuracy of the obtained equipment test result is lower, and the equipment test accuracy is lower are overcome by adopting test vector files of the same fixed file format for different automatic test equipment.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a flow diagram of JTAG interface control in one embodiment;

FIG. 2 is a flow chart of a test vector file conversion method according to an embodiment;

FIG. 3 is a flow diagram of steps for generating a clock block and a data block for each signal in one embodiment;

FIG. 4 is a flowchart illustrating steps for generating a second test vector file for a device under test in one embodiment;

FIG. 5 is a flowchart of a test vector file conversion method according to another embodiment;

FIG. 6 is a flow chart of a test vector conversion method according to one embodiment;

FIG. 7 is a flow chart of a test vector conversion method according to another embodiment;

FIG. 8 is a block diagram of a test vector file conversion device in one embodiment;

fig. 9 is an internal structural diagram of a computer device in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

ATE (Automatic Test Equipment ) testing is an indispensable step in the production of modern electronic products. After the design of an integrated circuit or an electronic product is completed, functional and reliability tests are required to ensure that the product meets quality standards and specification requirements, and automatic test equipment is used for simulating real working conditions in ATE tests and testing the product to be tested. Automated test equipment typically includes test equipment, test systems, test software, and the like. By means of these devices, various test signals can be generated, test results collected, data analyzed, etc. The test program is written by a test engineer and comprises test mode, test flow, test parameters and other information. The test program is loaded into the ATE device, which automatically performs the test process according to the instructions of the test program.

The WGL (Waveform Generation Language ) file is a hardware description language used in ATE testing to describe test vector generation and control. The WGL file contains information required for test pattern generation, such as input signals, timing control, expected output, etc. A design engineer may write WGL files to create the correct test patterns based on test requirements. The WGL file is loaded into the ATE device, which can generate a correct input signal according to the test sequence and timing requirements defined in the WGL file, provide the correct input signal to the product to be tested, and compare the output signal of the product to be tested with the expected result to verify the function and reliability of the product to be tested. ATE testing and WGL files are an integral part of the production of integrated circuits and electronics. Through automated test equipment and test programs, the products to be tested can be comprehensively and accurately tested to ensure that the products meet quality standards and specification requirements, and WGL files serve as important components in ATE test, so that necessary information and guidance are provided for test vector generation and control.

In chip functional testing, a common approach is to use a simulation environment, such as UVM (Universal Verification Methodology ), for verification and testing, rather than directly generating WGL files. The meaning of converting test vectors written based on System Verilog codes in a simulation environment into WGL files is that test patterns in the simulation environment can be applied to actual hardware tests. Test vectors in a simulation environment are sequences of input signals used to verify that a product under test, such as a circuit design, is correct. After simulation and verification, the input signal sequences can ensure that the circuit to be tested operates normally under ideal conditions. However, because the simulation environment differs from the actual hardware environment, it is necessary to convert the test vectors in the simulation environment into WGL files in order to perform the actual hardware test on the ATE equipment. The WGL file contains information required for test pattern generation, such as input signals, timing control, expected output, etc. Through the WGL file, ATE equipment can generate correct input signals according to specified test sequences and time sequence requirements, provide the correct input signals for a circuit to be tested, and compare output signals of the circuit to be tested with expected results so as to verify the functions and reliability of the circuit to be tested. Therefore, the application provides a test vector file conversion method, which can directly apply the test result in the simulation environment to the actual hardware test by converting the test vector in the simulation environment into the WGL file, thereby being beneficial to improving the test efficiency and accuracy, and simultaneously shortening the test time and reducing the test cost. Next, a description will be given of a procedure of performing a functional test in UVM by using a System Verilog through a JTAG (Joint Test Action Group ) protocol.

Chip design simulations typically utilize a UVM environment for functional testing and verification. UVM typically uses the System Verilog language to write test code to perform various tests on the chip under test and verify its function and performance. The JTAG protocol is a universal test and debug interface protocol for performing functional testing, fault analysis, and debug operations on integrated circuits. The system defines a group of signal lines and a state machine, and realizes the read-write of the internal register of the chip and the input and output of test data through the control and data exchange of the signal lines. The JTAG protocol uses four standard signal lines for control and data transfer:

TCK (Test Clock signal): for controlling the timing of JTAG operations. The frequency of the TCK signal can be set as desired, typically separately from the operating clock of the chip.

TMS (Test Mode Select, state machine control signal): indicating the state in which the current JTAG state machine is located. By changing the sequence of the TMS signal, the state of the JTAG state machine can be switched, and the flow of JTAG operation can be controlled.

TDI (TEST DATA IN, test data input signal): for writing data to registers in the chip. By sequentially inputting test data bits into the TDI on the edges of the TCK, data can be written to the chip's registers.

TDO (Test Data Out, test Data Out signal): for reading data from registers in the chip. By reading the data bits from the TDO on the edges of the TCK, the response data of the chip register can be obtained.

When the function test is carried out, test data can be input into a register of the chip in a binary form through TDI through a JTAG interface, and then corresponding test results are read from the register of the chip through TDO. This can verify whether the chip functions properly. Control and data transfer must follow a certain sequence of state transitions according to the requirements of the JTAG protocol. By changing the sequence of the TMS signal, the state of the JTAG state machine can be switched, thereby realizing control of JTAG operation. Different JTAG states correspond to different operations.

When using UVM for functional testing, the JTAG protocol may be used to input data into the DUT (Device Under Test ) and read the output data; in UVM, the control and operation of JTAG interface can be realized by writing an excitation class of JTAG protocol through System Verilog code, and the specific operation flow is shown in FIG. 1.

Referring to fig. 1, first, a JTAG object is created using a user-written JTAG function, the object representing a connection with a JTAG interface. Next, the JTAG operating function may be called for register writing. By configuring the address and data, the data to be written is transferred onto the TDI signal line of the JTAG interface. By invoking the JTAG function, the clock signal (TCK) and the state machine control signal (TMS) may be controlled to input data from the TDI into the DUT's registers at the timing specified by the JTAG protocol. Meanwhile, the JTAG protocol can be utilized to simulate the reading operation of the register. By calling the JTAG function, the address and control signals required for the read operation can be configured. Then, the data read from the DUT register is simulated by inputting simulated data bits from the TDI onto the TDO signal line of the JTAG interface and by reading the data bits of the TDO according to JTAG timing specification to verify whether the DUT is functioning properly. The above is a procedure of performing a functional test by JTAG protocol using System Verilog in UVM, and a procedure of converting the simulated functional test part into WGL test vector file in the present application is described next.

The WGL file in ATE testing is typically used to describe stimulus and expected responses during integrated circuit testing, which is the input format of the ATE when performing actual hardware testing. WGL is generated under DFT (Design for Testability) tools. The following explains the difference between the DFT test performed by WGL obtained from DFT and the functional test performed by converting WGL from System Verilog, the present application emphasizes that the test vector obtained from System Verilog is converted into WGL test file that is the same as the DFT tool, so as to satisfy the requirements of different test machines:

1. WGL obtained from DFT:

DFT is a strategy that is integrated during the design phase of an integrated circuit in order to improve the testability of the chip. WGL files generated by DFT means such as SCAN, boundary SCAN, BIST (Built-In Self-Test) and the like typically contain complex sequences of Test vectors required for fault detection for specific circuit structures, these tests being mainly aimed at checking the basic functional correctness of the circuit and potential manufacturing defects (e.g. Stuck-at faults, transition faults, PATH DELAY DEFECTS, bridge defects, etc.). Testing is a testing activity conducted directly using the DFT method described above, focusing mainly on the full coverage of the logic paths inside the chip and on hidden nodes that are difficult to access through conventional functional testing. In performing DFT testing on ATE, WGL files used are generated by specialized DFT tools or engineers based on the DFT characteristics of the design, with the aim of ensuring that faults can be found and isolated effectively and efficiently in the mass production stage.

2. Functional test from System Verilog to WGL:

System Verilog is a high-level hardware description language that is widely used in the verification field, including the functional verification section. The WGL file obtained by conversion from the System Verilog more reflects the verification result of the functional behaviors defined in the chip design specification, and the test content focuses on verifying whether the design meets the functional requirements specified by the specification. In this process, a tester may write a system-level and module-level test platform using a verification framework such as UVM, and generate detailed functional test cases, and then translate these test results into WGL format that the ATE can understand in order to perform functional testing on a physical chip. In summary, the WGL test obtained from DFT focuses on detecting various potential defects caused by manufacturing by DFT mechanism, and the functional test from System Verilog to WGL focuses on verifying whether the chip operates correctly according to design intent, which combine to ensure the quality and reliability of the chip.

Therefore, by utilizing the System Verilog to write a simulation test platform, design defects can be discovered and repaired early, so that the generated WGL test vector is more targeted, and unnecessary ATE test time and cost are reduced. And allows the designer to participate in the definition of the test content at the early stage of design, so that the test process is more flexible and easy to maintain. Meanwhile, the reusable System Verilog test code can quickly update the corresponding WGL test vector in the design iteration process.

Moreover, when performing DFT testing on ATE, the test vector files utilized are all in WGL format. However, for different ATE, it is necessary to generate test vector files corresponding to specific formats, that is, different formats of test vector files supported by different ATE, for example, ATE1 supports WGL format, ATE2 supports STIL (STANDARD TEST INTERFACE Language) format, ATE3 supports VMS (Vector Markup Language ) format, and so on. If test vector files of the same fixed file format (such as WGL format) are adopted for different ATEs, the accuracy of the obtained device test results is low, and thus the device test accuracy is low. Based on the method, the method for converting the test vector file comprehensively considers the current automatic test equipment of the equipment to be tested on the basis of the first test vector file of the equipment to be tested in the acquired simulation environment, and is favorable for converting the first test vector file into the second test vector file matched with the current automatic test equipment, so that the equipment test result obtained based on the current automatic test equipment is more accurate, the equipment test accuracy is further improved, and the defects that the accuracy of the obtained equipment test result is lower and the equipment test accuracy is lower due to the fact that the test vector files with the same fixed file format are adopted for different automatic test equipment are avoided.

In one embodiment, as shown in fig. 2, a test vector file conversion method is provided, and the embodiment is applied to a terminal for illustration by the method; it will be appreciated that the method may also be applied to a server, and may also be applied to a system comprising a terminal and a server, and implemented by interaction between the terminal and the server. The terminal can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and the like; the server may be implemented as a stand-alone server or as a server cluster composed of a plurality of servers. In this embodiment, the method includes the following steps S201 to S204.

Wherein:

step S201, a first test vector file for a device to be tested in a simulation environment is obtained.

Wherein, the simulation environment may refer to a UVM environment; of course, the simulation environment may also refer to other environments, and the present application is not limited thereto. A Device Under Test (DUT) refers to a device that needs to be tested for functionality, such as a chip under test, a circuit under test, an electronic product under test, etc.

The first test vector file refers to a test vector file for functional test of a device to be tested in a simulation environment, and specifically refers to an input signal sequence for verifying whether the device to be tested functions normally in the simulation environment, such as a test vector written based on System Verilog codes in a UVM environment for performing functional test of the device. In an actual scenario, the first test vector file refers to a test vector file in the form of System Verilog code. Of course, the first test vector file may also refer to other code forms, such as Verilog (Verification Logic, validation logic), VHDL (VHSIC HARDWARE Description Language, ultra-high speed integrated circuit hardware description language), and the like, i.e., the first test vector file may support multiple file formats.

The first test vector file includes information required for conversion into the second test vector file, such as global settings, signal definition of each signal, signal data, expected value information, test mode, clock period, timing constraint, edge trigger condition, and the like.

Where global setting refers to a reference clock that provides a reference for each signal's clock cycle. The signal definition refers to the signal name. The signal data refers to an actual input signal, such as a level value of 0 or 1. The expected value information refers to an expected output signal.

It should be noted that, the first test vector file for the device under test in the simulation environment is generated in advance, but because the simulation environment is different from the actual hardware environment, the first test vector file in the simulation environment needs to be converted into the second test vector file (such as WGL file) so as to apply the test mode in the simulation environment to the actual hardware test, thereby improving the test accuracy of the device.

The terminal screens out the first test vector file for the device to be tested from the first test vector files for the plurality of devices in the simulation environment. Further, the terminal may further obtain a first test vector file for the device under test in the simulation environment from the local database.

The terminal identifies the device identifier corresponding to the first test vector file in the simulation environment, then respectively matches the device identifier of the device to be tested with the device identifiers corresponding to the first test vector files, and uses the first test vector file successfully matched with the corresponding device identifier of the device to be tested as the first test vector file for the device to be tested in the simulation environment.

Step S202, identifying the content information and the time sequence information of each signal from the first test vector file.

The first test vector file records content information and timing information of a plurality of signals (i.e., test signals), so that the content information and timing information of each signal can be extracted from the first test vector file.

Wherein the content information of each signal includes signal definition, signal data, expected value information, test pattern, and the like. The timing information for each signal includes clock cycles, timing constraints, edge trigger conditions, and the like. Of course, the terminal may also extract the global settings from the first test vector file.

Illustratively, the terminal identifies content information for each signal from the first test vector file using the content information identification instruction; and simultaneously, identifying the time sequence information of each signal from the first test vector file by utilizing the time sequence information identification instruction.

Further, the terminal may identify, from the first test vector file, information corresponding to the content information identifier of each signal, as the content information of each signal; and identifying information corresponding to the time sequence information identifier of each signal from the first test vector file, and correspondingly serving as time sequence information of each signal.

For example, the terminal uses a grammar analysis and semantic understanding algorithm to perform grammar analysis processing on the System Verilog code in the first test vector file to obtain content information and time sequence information of each signal.

Step S203, generating a clock block and a data block of each signal according to the content information and the time sequence information of each signal; the clock block includes at least timing information for each signal, and the data block for each signal includes at least corresponding signal waveform text data.

The clock block refers to an information block including timing information of each signal, and specifically refers to a WGL file header. It should be noted that the clock block may also include global settings.

Wherein each signal corresponds to a block of data. The data block includes corresponding signal waveform text data, specifically, WGL block. It should be noted that the data block may further include a corresponding signal definition.

The signal waveform text data is used for describing the signal waveform in text form, such as a text segment. The signal waveform text data of each signal is obtained by processing according to the corresponding content information and time sequence information, for example, according to the corresponding test mode and time sequence requirement. Of course, the signal waveform text data of each signal can also be obtained by processing according to the corresponding test mode, time sequence requirement and actual design condition.

Illustratively, the terminal generates a clock block based on the timing information of each signal; then generating signal waveform text data corresponding to each signal according to the content information and the time sequence information of each signal; and finally, generating a data block of each signal according to the signal waveform text data corresponding to each signal.

Step S204, generating a second test vector file for the device to be tested according to the clock block and the data block of each signal; the file format of the second test vector file is different from the file format of the first test vector file, and the file format of the second test vector file is matched with the current automatic test equipment for the equipment to be tested.

The second test vector file refers to a test vector file for a function test of the device under test in an actual hardware environment, and specifically refers to an input signal file, such as a WGL file, an STIL file, a VMS file, etc., used for verifying whether the function of the device under test is normal in the actual hardware environment. In an actual scenario, the second test vector file refers to a test vector file in the form of WGL code. Of course, the second test vector file may also refer to other code forms, such as a STIL (STANDARD TEST INTERFACE Language ), a VCD (Value Change Dump, value change dump), a EVCD (Extended Value Change Dump ), a VMS (Vector Markup Language, vector markup Language), etc., that is, the second test vector file may support multiple file formats, and may be specifically adjusted according to practical situations; for example, test vector files corresponding to a particular format need to be generated for different ATEs. In other words, the second test vector file refers to a test vector file that is adapted to the current ATE; for example, the terminal may convert the first test vector file into a test vector file that is compatible with the current ATE, and use it as the second test vector file.

Wherein, the file formats of the second test vector files supported by different ATEs are different; the matching of the file format of the second test vector file with the current automatic test equipment for the device to be tested means that the file format of the second test vector file is matched with the current automatic test equipment, i.e. the current automatic test equipment supports the file format of the second test vector file.

The current automatic test equipment for the equipment to be tested refers to the automatic test equipment for performing functional test on the equipment to be tested currently; the second test vector file is loaded to the current automatic test equipment, and then the current automatic test equipment is based on the second test vector file, so that the functional test of the equipment to be tested can be realized.

The second test vector file comprises a clock block and a data block of each signal, and the clock block and the data block are used for carrying out functional test on the equipment to be tested in an actual hardware environment. For example, the WGL file contains information required for test pattern generation, such as input signals, timing control, expected output, etc. By loading the WGL file into the ATE equipment, the ATE equipment can generate correct input signals according to specified test sequences and time sequence requirements, provide the correct input signals for the equipment to be tested, and compare actual output signals of the equipment to be tested based on the input signals with expected output signals so as to verify the functions and reliability of the equipment to be tested.

It should be noted that, after the second test vector file for the device to be tested is generated, in order to implement automatic verification and test, the present application may also establish an automatic verification and test framework to perform comprehensive functional verification and performance test on the conversion tool, so as to ensure accuracy and reliability of the conversion result.

The terminal combines the clock block and the data block of each signal to obtain a test vector file with a corresponding file format different from that of the first test vector file and matching with the current automatic test equipment of the device to be tested as a second test vector file of the device to be tested.

According to the test vector file conversion method, the first test vector file aiming at the equipment to be tested in the simulation environment is obtained, the content information and the time sequence information of each signal are identified from the first test vector file, then a clock block and a data block of each signal are generated according to the content information and the time sequence information of each signal, the clock block at least comprises the time sequence information of each signal, the data block of each signal at least comprises corresponding signal waveform text data, finally a second test vector file aiming at the equipment to be tested is generated according to the clock block and the data block of each signal, the file format of the second test vector file is different from the file format of the first test vector file, and the file format of the second test vector file is matched with the current automatic test equipment aiming at the equipment to be tested; in this way, in the process of generating the second test vector file, on the basis of the first test vector file of the equipment to be tested in the acquired simulation environment, the current automatic test equipment of the equipment to be tested is comprehensively considered, and the first test vector file is favorably converted into the second test vector file matched with the current automatic test equipment, so that the equipment test result obtained based on the current automatic test equipment is more accurate, the equipment test accuracy is further improved, and the defects that the accuracy of the obtained equipment test result is lower, and the equipment test accuracy is lower are overcome by adopting test vector files of the same fixed file format for different automatic test equipment.

In an exemplary embodiment, the step S202 identifies, from the first test vector file, content information and timing information of each signal, including the following specific contents: identifying an objective function associated with each signal from the first test vector file; from the objective function associated with each signal, the content information and timing information of each signal are identified.

Wherein the first test vector file includes an objective function associated with each signal. The objective function associated with each signal is used to document the content information and timing information of the corresponding signal. It should be noted that, the objective function associated with each signal is different, and the objective function associated with each signal may be predefined.

Illustratively, the terminal obtains the objective function name associated with each signal from a local database; then screening out a function corresponding to the name of the objective function associated with each signal from the first test vector file, and correspondingly taking the function as the objective function associated with each signal; finally, the content information of each signal is identified from the objective function associated with each signal using the content information identification instruction, and the timing information of each signal is identified from the objective function associated with each signal using the timing information identification instruction.

Further, the terminal may identify, from the objective function associated with each signal, information corresponding to the content information identifier of each signal, as the content information of each signal; and identifying information corresponding to the timing information identifier of each signal from the objective function associated with each signal, the information corresponding to the timing information of each signal.

In this embodiment, the content information and the time sequence information of each signal are identified from the first test vector file and the objective function associated with each signal, so that the content information and the time sequence information of each signal can be accurately extracted, the defect that the extracted content information and time sequence information have low accuracy due to omission or errors when the content information and the time sequence information are directly extracted from the first test vector file is avoided, and the extraction accuracy of the content information and the time sequence information of the signal is further improved.

In an exemplary embodiment, the content information and the timing information of each signal are identified from the objective function associated with each signal, and specifically include the following contents: inputting the objective function associated with each signal into a pre-trained content information identification model to obtain the content information of each signal; and respectively inputting the objective function associated with each signal into a pre-trained time sequence information identification model to obtain the time sequence information of each signal.

The content information recognition model is a neural network model for recognizing content information of the signal, such as a first semantic recognition model, and can be obtained through pre-training.

The time sequence information identification model is a neural network model for identifying time sequence information of signals, such as a second semantic identification model, and can be obtained through pre-training.

The terminal firstly carries out iterative training on the content information identification model to be trained to obtain a content information identification model after training, and the content information identification model is used as a content information identification model trained in advance; and performing iterative training on the time sequence information recognition model to be trained to obtain a trained time sequence information recognition model which is used as a pre-trained time sequence information recognition model. Then, the terminal respectively inputs the objective function associated with each signal into a pre-trained content information identification model, and semantic analysis processing is carried out on the objective function associated with each signal through the pre-trained content information identification model to obtain the content information of each signal; inputting the objective function associated with each signal into a pre-trained time sequence information recognition model, and carrying out semantic analysis processing on the objective function associated with each signal through the pre-trained time sequence information recognition model to obtain the time sequence information of each signal.

In the present embodiment, the content information of each signal is identified from the objective function associated with each signal using the content information identification model trained in advance, and the time series information of each signal is identified from the objective function associated with each signal using the time series information identification model trained in advance; in this way, the content information and the time sequence information of each signal are identified by means of the pre-trained content information identification model and the pre-trained time sequence information identification model, so that the content information and the time sequence information of each signal can be accurately extracted, the content information and the time sequence information of the signal reflected by the first test vector file can be accurately described by the subsequently generated second test vector file, and the conversion accuracy of the second test vector file is further improved.

In an exemplary embodiment, as shown in fig. 3, the step S203 generates a clock block and a data block of each signal according to the content information and the timing information of each signal, including steps S301 to S303. Wherein:

Step S301, generating a clock block according to the reference time sequence information and the time sequence information of each signal; the reference time sequence information is extracted from the first test vector file.

Step S302, according to the content information and the time sequence information of each signal, generating a signal identifier and signal waveform text data corresponding to each signal.

Step S303, generating a data block of each signal according to the signal identifier and the signal waveform text data corresponding to each signal.

The reference timing information refers to global settings, such as a reference clock. The reference timing information is also recorded in the first test vector file.

The clock block specifically includes reference timing information and timing information of each signal.

The signal identifier corresponding to each signal refers to a signal name corresponding to each signal, and specifically refers to a signal definition in content information of each signal.

The data block of each signal specifically comprises a corresponding signal identifier and signal waveform text data. It should be noted that the signal identifier is included in the data block to indicate which signal the signal waveform text data in the data block is.

The terminal may extract information corresponding to the reference timing information identifier from the first test vector file as the reference timing information, or may identify the reference timing information from the first test vector file in accordance with the reference timing information identification instruction. And then combining the reference time sequence information and the time sequence information of each signal to obtain a clock block. Then, the terminal defines the signals in the content information of each signal as the signal identifications corresponding to each signal, processes the content information and the time sequence information of each signal to obtain signal waveform text data corresponding to each signal, and finally combines the signal identifications corresponding to each signal and the signal waveform text data to obtain the data block of each signal.

In this embodiment, according to the reference timing information and the timing information of each signal, a clock block is generated, and according to the signal identifier and the signal waveform text data corresponding to each signal, a data block of each signal is generated, which is favorable for generating a second test vector file matched with the current automatic test equipment according to the clock block and the data block of each signal, is favorable for improving the equipment test accuracy, and avoids the defect that the generated second test vector file is not matched with the current automatic test equipment, resulting in lower equipment test accuracy.

In an exemplary embodiment, the step S302 generates, according to the content information and the timing information of each signal, a signal identifier and signal waveform text data corresponding to each signal, which specifically includes the following contents: extracting signal definition and key content information of each signal from the content information of each signal; defining the signal of each signal, and confirming the signal as a signal identifier corresponding to each signal; and generating signal waveform text data corresponding to each signal according to the key content information and the time sequence information of each signal.

The key content information refers to signal data, test modes and the like.

The terminal may extract information corresponding to the signal definition identifier from the content information of each signal as the signal definition of each signal, and extract information corresponding to the key content information identifier from the content information of each signal as the key content information of each signal. Or the terminal identifies the signal definition of each signal from the content information of each signal according to the signal definition identification instruction, and identifies the key content information of each signal from the content information of each signal according to the key content information identification instruction. Then, the terminal defines the signal of each signal, confirms the signal identification corresponding to each signal, and finally processes the key content information and the time sequence information of each signal to obtain text data for describing the signal waveform corresponding to each signal, and the text data is used as the signal waveform text data corresponding to each signal; for example, the test mode, the signal data, the time sequence information, the clock period, the time sequence constraint, the edge triggering condition and the like of each signal are processed to obtain the signal waveform text data corresponding to each signal.

For example, the terminal may process the test mode, the timing requirement and the actual design condition corresponding to each signal, to obtain the signal waveform text data corresponding to each signal.

In this embodiment, according to the content information and the time sequence information of each signal, the signal identifier and the signal waveform text data corresponding to each signal are generated, which is favorable for generating the data block of each signal based on the signal identifier and the signal waveform text data corresponding to each signal, and further, based on the clock block and the data block of each signal, the second test vector file is automatically generated, thereby realizing the purpose of automatically generating the second test vector file matched with the current automatic test equipment, without re-writing the second test vector file matched with the current automatic test equipment, simplifying the test process of the equipment to be tested, and being favorable for shortening the test time of the equipment to be tested, and further improving the test efficiency of the equipment.

In an exemplary embodiment, step S204 generates a second test vector file for the device under test according to the clock block and the data block of each signal, including steps S401 to S402. Wherein:

Step S401, a pre-created test vector file structure is obtained; the test vector file structure comprises a clock block area and a data block area of each signal; the pre-created test vector file structure is a test vector file structure that matches the current automatic test equipment.

In step S402, a clock block is added to the clock block area, and a data block of each signal is added to the data block area of each signal, respectively, to obtain a test vector file corresponding to the test vector file structure, as a second test vector file for the device under test.

The pre-created test vector file structure refers to a test vector file structure matched with the current automatic test equipment, and specifically refers to a test vector file structure supported by the current automatic test equipment, such as a WGL file structure. The test vector file structure supported by different automatic test equipment is different. The clock block area refers to a WGL file header area for storing WGL file headers. The data block area is referred to as WGL block area, and stores WGL blocks of corresponding signals.

The terminal obtains a test vector file structure matched with the current automatic test equipment from a local database as a pre-created test vector file structure, identifies a clock block area and a data block area of each signal from the pre-created test vector file structure, adds a clock block to the clock block area, and adds the data block of each signal to the data block area of each signal respectively to obtain a test vector file corresponding to the test vector file structure, and uses the test vector file as a second test vector file for the equipment to be tested.

For example, the terminal adds a clock block to a clock block area in the WGL file structure that matches the current automatic test equipment, adds a data block of the a signal to a data block area of the a signal, adds a data block of the B signal to a data block area of the B signal, adds a data block of the C signal to a data block area of the C signal … …, and so on, and finally obtains the WGL file for the device under test.

In the embodiment, adding a clock block into a clock block area in a test vector file structure matched with the current automatic test equipment, and respectively adding a data block of each signal into a data block area of each signal in the test vector file structure matched with the current automatic test equipment to obtain a second test vector file aiming at the equipment to be tested; in this way, in the process of generating the second test vector file, the test vector file structure matched with the current automatic test equipment is comprehensively considered, and the clock block and the data block are placed in the corresponding area in the test vector file structure, so that the accuracy of the obtained second test vector file is guaranteed, the conversion accuracy of the second test vector file is improved, and the determination accuracy of the second test vector file is further improved.

In an exemplary embodiment, the step S204 further includes, before generating the second test vector file for the device under test according to the clock block and the data block of each signal: creating a clock block area and a data block area for each signal; and combining the clock block area and the data block area of each signal according to a preset combination sequence to obtain a test vector file structure matched with the current automatic test equipment, wherein the test vector file structure is used as a pre-established test vector file structure.

The preset combination sequence means that the clock block area is arranged at the forefront, the data block area of each signal is arranged at the rear of the clock block area in sequence, for example, the head area of the WGL file is arranged at the forefront, and the WGL block area of each signal is arranged at the rear of the head area of the WGL file in sequence.

The obtained test vector file structure may be referred to as WGL file structure, and is specifically determined according to the current automatic test equipment.

The number of the data block areas is determined according to the number of the signals to which the content information (or the time sequence information) analyzed from the first test vector file belongs, that is, the number of the data block areas is equal to the number of the signals to which the content information (or the time sequence information) analyzed from the first test vector file belongs.

Illustratively, the terminal creates a clock block area and a data block area for each signal in accordance with a second test vector file format (such as WGL file format); according to the sequence that the clock block areas are arranged at the forefront and the data block areas of each signal are arranged at the rear of the clock block areas in sequence, combining the clock block areas and the data block areas of each signal together to obtain a test vector file structure matched with the current automatic test equipment, and taking the test vector file structure as a pre-established test vector file structure.

In this embodiment, the created clock block area and the data block area of each signal are combined according to a preset combination sequence to obtain a test vector file structure matched with the current automatic test equipment; in this way, by creating the test vector file structure matched with the current automatic test equipment, the clock blocks can be accurately added into the clock block area in the test vector file structure, and the data blocks of each signal can be accurately added into the data block area of each signal in the test vector file structure, so that a second test vector file matched with the current automatic test equipment can be obtained, the integrity, the order and the accuracy of information in the generated second test vector file can be ensured, the generation accuracy of the second test vector file can be further improved, and the content consistency of the second test vector file and the first test vector file can be ensured.

In an exemplary embodiment, as shown in fig. 5, another test vector file conversion method is provided, and the method is applied to a terminal for illustration, and includes steps S501 to S509. Wherein:

step S501, a first test vector file for a device under test in a simulation environment is obtained.

Step S502, identifying an objective function associated with each signal from the first test vector file.

Step S503, respectively inputting the objective function associated with each signal into a pre-trained content information identification model to obtain the content information of each signal; and respectively inputting the objective function associated with each signal into a pre-trained time sequence information identification model to obtain the time sequence information of each signal.

Step S504, creating a clock block area and a data block area of each signal; and combining the clock block area and the data block area of each signal according to a preset combination sequence to obtain a test vector file structure matched with the current automatic test equipment, wherein the test vector file structure is used as a pre-established test vector file structure.

Step S505, generating a clock block according to the reference time sequence information and the time sequence information of each signal; the reference time sequence information is extracted from the first test vector file.

Step S506, extracting signal definition and key content information of each signal from the content information of each signal; defining the signal of each signal, and confirming the signal as a signal identifier corresponding to each signal; and generating signal waveform text data corresponding to each signal according to the key content information and the time sequence information of each signal.

Step S507, generating a data block of each signal according to the signal identifier and the signal waveform text data corresponding to each signal.

In step S508, the clock block is added to the clock block area of the pre-created test vector file structure, and the data block of each signal is added to the data block area of each signal of the pre-created test vector file structure, respectively, to obtain the test vector file corresponding to the test vector file structure.

Step S509, a test vector file corresponding to the test vector file structure is used as a second test vector file for the device to be tested; the file format of the second test vector file is different from the file format of the first test vector file, and the file format of the second test vector file is matched with the current automatic test equipment for the equipment to be tested.

In the test vector file conversion method, in the process of generating the second test vector file, on the basis of the first test vector file of the equipment to be tested in the acquired simulation environment, the current automatic test equipment of the equipment to be tested is comprehensively considered, and the first test vector file is favorably converted into the second test vector file matched with the current automatic test equipment, so that the equipment test result obtained based on the current automatic test equipment is more accurate, the equipment test accuracy is further improved, and the defects that the accuracy of the obtained equipment test result is lower and the equipment test accuracy is lower due to the fact that the test vector files with the same fixed file format are adopted for different automatic test equipment are avoided.

In an exemplary embodiment, in order to more clearly illustrate the test vector file conversion method provided in the embodiment of the present application, a specific embodiment is described below specifically. In one embodiment, referring to fig. 6, a test vector conversion method is provided, in which a test vector written based on a hardware verification language (System Verilog) code in a simulation environment is parsed by using a parsing syntax, and is extracted in time sequence, and then WGL waveform generation and encoding are performed by using parsed information and extracted information, and finally a Waveform Generation Language (WGL) test vector file is output. The method specifically comprises the following steps:

Parsing System Verilog code: firstly, analyzing a System Verilog code, and identifying signal definition, signal data and expected value information in the function. This requires parsing and semantic understanding by means of a compiler or parser.

Extracting time sequence information: the timing information of each signal is extracted from the System Verilog code, including clock period, timing constraint, edge trigger condition, etc. These information determine the timing characteristics of the waveform data in the WGL file being generated.

Generating a WGL file: and generating waveform data meeting the requirements of the WGL format according to the time sequence information extracted by the System Verilog code. This includes clock waveforms, data signal waveforms, and relative timing relationships between them. The WGL file generated should be consistent with the original System Verilog code and be able to be identified and used by the target simulation tool or ATE System.

The above embodiment can achieve the following technical effects: (1) Accurately analyzing and extracting time sequence information of the signals, and ensuring that the generated WGL file can accurately describe waveform characteristics in a System Verilog code; (2) Maintaining consistency of the converted WGL file and the original System Verilog code, including signal naming, hierarchical structure and the like, so as to ensure conversion correctness and maintainability; (3) Processing complex control flow and condition logic to ensure that the generated WGL file can accurately simulate the behavior in the System Verilog code; (4) It is ensured that no additional errors or deviations are introduced during the conversion process and that sufficient verification and testing is performed.

In another embodiment, referring to fig. 7, another test vector conversion method is provided for converting System Verilog codes in UVM into WGL files, specifically including the following:

Parsing hardware verification language (System Verilog) code from keywords: first, a parser is written using the Python language, which needs to be able to read the System Verilog code in the current functional test and recognize definitions of individual signals, clock cycles, test patterns, expected value information, and the like. By traversing the driver portion of the functional test code, the required information may be extracted and stored in a defined data structure for later use in generating WGL files.

Defining a Waveform Generation Language (WGL) file structure: the structure and syntax of the WGL file is defined according to the specification of the WGL file format. WGL files are typically made up of clock blocks and data blocks, each block describing waveform text information of a signal. The structure of WGL files is defined using a string formatting template in Python.

Generating a Waveform Generation Language (WGL) file header: in generating a WGL file, header information of the file, including global settings and clock period definitions, is first required to be output. This part of the information can be obtained directly from the parsing result of the System Verilog code, for example the clock frequency.

Signal-by-signal generation Waveform Generation Language (WGL) block: and generating corresponding WGL blocks for each signal in the WGL file according to the signal information obtained by analysis. For each signal, its name and corresponding waveform data need to be generated. The waveform data can be obtained by processing according to the test mode, the time sequence requirement and the actual design condition.

Integrated Waveform Generation Language (WGL) file contents: and integrating the generated WGL blocks according to the grammar rule of the WGL file to form final WGL file content. This is done using a function related to the file operation, writing parts of the content into the file step by step.

Output Waveform Generation Language (WGL) file: finally, writing the generated WGL file content into a file, and storing the WGL file content into a WGL format file. The finally generated file is ensured to meet the requirement of WGL format, and can be identified and used by an ATE test machine, and the file operation related function in Python is used for realizing the output and storage of the file.

The above embodiment can achieve the following technical effects: (1) ATE compatibility: ATE is a commonly used test equipment, commonly used to test integrated circuits and chips. By converting the System Verilog code to WGL format, it can be ensured that waveform data is compatible with the ATE System, making System Verilog code easier for the ATE System to use and perform testing. (2) reducing development time: after the System Verilog code is converted into WGL format, the generated WGL file can be directly used for testing in an ATE System. Therefore, the time for a developer to write the ATE test program can be saved, and the establishment of a test environment and the execution speed of the test case can be accelerated. (3) facilitating fault injection: in ATE testing, it is sometimes necessary to inject a specific failure mode to test the fault tolerance of the chip. By converting the System Verilog code into the WGL format, corresponding fault waveform data can be generated according to fault injection requirements and loaded and executed in an ATE System, so that fault injection testing is facilitated. (4) Cross-platform and Cross-tool support: because WGL is a general sequencing vector format, the generated WGL file can be used on different operating systems and different simulation tools, so that the portability and flexibility of codes are improved.

It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.

Based on the same inventive concept, the embodiment of the application also provides a test vector file conversion device for realizing the above-mentioned test vector file conversion method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in the embodiments of the test vector file conversion device or devices provided below may be referred to the limitation of the test vector file conversion method hereinabove, and will not be repeated herein.

In an exemplary embodiment, as shown in fig. 8, there is provided a test vector file conversion apparatus, including: a file acquisition module 810, an information identification module 820, an information processing module 830, and a file generation module 840, wherein:

the file obtaining module 810 is configured to obtain a first test vector file for a device under test in the simulation environment.

The information identifying module 820 is configured to identify content information and timing information of each signal from the first test vector file.

An information processing module 830 for generating a clock block and a data block of each signal according to the content information and the timing information of each signal; the clock block includes at least timing information for each signal, and the data block for each signal includes at least corresponding signal waveform text data.

A file generating module 840, configured to generate a second test vector file for the device under test according to the clock block and the data block of each signal; the file format of the second test vector file is different from the file format of the first test vector file, and the file format of the second test vector file is matched with the current automatic test equipment for the equipment to be tested.

In an exemplary embodiment, the information identifying module 820 is further configured to identify, from the first test vector file, an objective function associated with each signal; from the objective function associated with each signal, the content information and timing information of each signal are identified.

In an exemplary embodiment, the information identifying module 820 is further configured to input the objective function associated with each signal into a pre-trained content information identifying model to obtain content information of each signal; and respectively inputting the objective function associated with each signal into a pre-trained time sequence information identification model to obtain the time sequence information of each signal.

In an exemplary embodiment, the information processing module 830 is further configured to generate a clock block according to the reference timing information and the timing information of each signal; the reference time sequence information is extracted from the first test vector file; generating a signal identifier and signal waveform text data corresponding to each signal according to the content information and the time sequence information of each signal; and generating a data block of each signal according to the signal identifier corresponding to each signal and the signal waveform text data.

In an exemplary embodiment, the information processing module 830 is further configured to extract the signal definition and the key content information of each signal from the content information of each signal; defining the signal of each signal, and confirming the signal as a signal identifier corresponding to each signal; and generating signal waveform text data corresponding to each signal according to the key content information and the time sequence information of each signal.

In an exemplary embodiment, the file generation module 840 is further configured to obtain a pre-created test vector file structure; the test vector file structure comprises a clock block area and a data block area of each signal; adding a clock block into the clock block area, and respectively adding a data block of each signal into the data block area of each signal to obtain a test vector file corresponding to the test vector file structure, wherein the test vector file is used as a second test vector file for equipment to be tested; the pre-created test vector file structure is a test vector file structure that matches the current automatic test equipment.

In an exemplary embodiment, the test vector file conversion apparatus further includes a structure creation module for creating a clock block area and a data block area for each signal; and combining the clock block area and the data block area of each signal according to a preset combination sequence to obtain a test vector file structure matched with the current automatic test equipment, wherein the test vector file structure is used as a pre-established test vector file structure.

The modules in the test vector file conversion device can be all or partially realized by software, hardware and a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

In an exemplary embodiment, a computer device, which may be a terminal, is provided, and an internal structure thereof may be as shown in fig. 9. The computer device includes a processor, a memory, an input/output interface, a communication interface, a display unit, and an input means. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input/output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program, when executed by a processor, implements a test vector file conversion method. The display unit of the computer device is used for forming a visual picture, and can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be a key, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.

It will be appreciated by persons skilled in the art that the architecture shown in fig. 9 is merely a block diagram of some of the architecture relevant to the present inventive arrangements and is not limiting as to the computer device to which the present inventive arrangements are applicable, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.

In an exemplary embodiment, a computer device is also provided, comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the method embodiments described above when the computer program is executed.

In one exemplary embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method embodiments described above.

In an exemplary embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the steps of the method embodiments described above.

It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are both information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data are required to meet the related regulations.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magneto-resistive random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (PHASE CHANGE Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in various forms such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims

1. A method for converting a test vector file, the method comprising:

2. The method of claim 1, wherein identifying content information and timing information for each signal from the first test vector file comprises:

3. The method of claim 2, wherein identifying the content information and the timing information of each signal from the objective function associated with each signal comprises:

4. The method of claim 1, wherein generating the clock block and the data block of each signal based on the content information and the timing information of each signal comprises:

5. The method of claim 4, wherein generating the signal identifier and the signal waveform text data corresponding to each signal according to the content information and the timing information of each signal comprises:

6. The method of claim 1, wherein generating a second test vector file for the device under test based on the clock block and the data block for each signal comprises:

7. The method of claim 6, further comprising, prior to generating a second test vector file for the device under test based on the clock block and the data block for each signal:

creating a clock block area and a data block area of each signal;

8. A test vector file conversion apparatus, the apparatus comprising:

9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 7 when the computer program is executed.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.

11. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.