JP2005032191A - Virtual tester, test device, test system for semiconductor integrated circuit, and verification method of test program for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a virtual tester capable of completely executing a test program by simulation; to provide a test device composed by realizing the virtual tester by a hardware description language on a computer; to provide a test system for a semiconductor integrated circuit capable of easily determining whether there is a bug in a test program or not; and to provide a verification method of a test program for a semiconductor integrated circuit capable of surely verifying percentage completion of the test program. <P>SOLUTION: A virtual CPU 2 (program execution circuit) and a virtual RAM 3 (program storage circuit) are modeled on a computer by a hardware description language; the entire test program is stored in the virtual RAM 3; and a semiconductor integrated circuit modeled by a hardware description language of a test object is tested. By using a good product for the semiconductor integrated circuit, whether there is a bug in the test program or not can be determined. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a virtual tester for testing a semiconductor integrated circuit modeled in a hardware description language by simulation on a computer, a test apparatus in which such a virtual tester is modeled on a computer in a hardware description language, The present invention also relates to a semiconductor integrated circuit test system using such a virtual tester or test apparatus, and further to a verification method for verifying the completeness of a semiconductor integrated circuit test program used in such a system.

  Conventionally, a function test and a current voltage test using a semiconductor integrated circuit test system (hereinafter referred to as an LSI tester) as an actual device have been performed on a semiconductor integrated circuit before shipment. In the functional test, a test pattern signal prepared in advance is given to a semiconductor integrated circuit before shipment, and it is determined whether or not the semiconductor integrated circuit is operating as planned according to the test pattern signal. In the current-voltage test, a current when a specific voltage is applied to each terminal of the semiconductor integrated circuit before shipment is measured, and it is determined whether or not this current value satisfies the specifications of the semiconductor integrated circuit. A test and a test for measuring a voltage when a current is applied to each terminal of the semiconductor integrated circuit and determining whether or not this voltage value satisfies the specifications of the semiconductor integrated circuit are performed.

  In order to carry out these functional tests and current / voltage tests using an LSI tester, it is necessary to create a test program for that purpose in advance. However, since this test program requires the setting work of the power supply voltage value / current value and the operating condition for the test target semiconductor integrated circuit and the test result for the measurement result for each of the plurality of test items, There was a problem that the code lengthened and this increased the overall size of the test program.

  Furthermore, the test program as described above needs to be created so as to correspond to each type of semiconductor integrated circuit, and also when only a part of the semiconductor integrated circuit is changed, the semiconductor integrated circuit Even if the specifications are changed, it is necessary to create a new one, or to modify or change the specification.

  When such a new test program is created, modified, or changed, it is necessary to perform debugging as in the case of a general program. In addition, in order to debug a test program, a test target semiconductor integrated circuit Needless to say, an LSI tester is necessary. Furthermore, when such a new test program is created and debugged, the start time and completion time are important. In other words, when a new semiconductor integrated circuit is developed and manufactured, a new LSI tester and test program are created before the actual production of the semiconductor integrated circuit in order to shorten the development period and improve efficiency. However, there is a problem that the semiconductor integrated circuit to be tested does not actually exist at that time.

  Under these circumstances, a virtual tester technique has been put to practical use as a technique for creating (developing) and debugging a test program without using an actual semiconductor integrated circuit and an LSI tester.

  A virtual tester is a test target that can be used to create a new test program and debug it by preparing a model in a hardware description language of a semiconductor integrated circuit to be tested and a model in a hardware description language of an LSI tester on a computer. This technology is realized by simulation on a computer without using the semiconductor integrated circuit and the LSI tester.

  Here, the test program is a program for an LSI tester that tests a semiconductor integrated circuit. The test pattern is included in the test program as a part thereof, and is input to the input terminal of the test target semiconductor integrated circuit and output from the output terminal of the test target semiconductor integrated circuit accordingly. This data corresponds to the data to be output (output expected value information). Therefore, if the data output from the semiconductor integrated circuit according to the test pattern input to the test target semiconductor integrated circuit is different from the output expected value information, the semiconductor integrated circuit is a defective product, Alternatively, it can be determined that there is a defect (bug) in the test program.

  As a conventional virtual tester, for example, DVT (Digital Virtual Tester) developed by IMS is known, and a test program debugging environment in a functional test on a computer is realized (for example, see Non-Patent Document 1). ). As another conventional technique, a technique that enables debugging of a test program related to a function test and a current-voltage test is also known (see, for example, Patent Document 1).

  An example of a simulation execution procedure using the conventional virtual tester disclosed in Non-Patent Document 1 described above will be described with reference to the flowchart of FIG.

  As shown in FIG. 15, in the prior art disclosed in Non-Patent Document 1, a test program including a plurality of measurement items and determination items is prepared in advance, and for example, a function test item is executed from among them. The part is extracted (step S1), compiled so that the virtual tester can take in (specifically, the description of “for”, “if”, etc. is binary coded) (step S2), and the result of compilation 2 A simulation is carried out by taking the binary code into the PLI of the virtual tester and executing it (step S3).

  What should be noted here is that, in the prior art disclosed in Non-Patent Document 1 shown in FIG. 15 and the like, only the program of the portion related to the function test item is extracted in step S1, and therefore, as a result. In step S3, only the functional test portion of the test program is executed and simulated.

  FIG. 16 is a schematic diagram for explaining a conventional method for verifying the completeness of a test program for a semiconductor integrated circuit. Specifically, a test program TP is loaded onto the LSI tester 1 ′, and the LSI tester 1 ′ executes this test program, thereby providing a semiconductor integrated circuit composed of actual semiconductor integrated circuits 7′-1, 7′-2,. A test was performed on the circuit group 70 '.

  However, in this conventional example, the actual semiconductor integrated circuit (non-defective LSI) 7′-1, 7′-2... 7′- having various characteristics (characteristics that fall within the design specifications) that the test program TP should determine as non-defective In reality, it is impossible to have all n. Similarly, all of the actual semiconductor integrated circuits (defective LSI) 70'-1, 70'-2 ... 70'-m that have various characteristics (characteristics that deviate from the design specifications) to be judged as defective products are available. It is impossible.

  Therefore, the semiconductor integrated circuit group 70 ′ is a semiconductor integrated circuit 7′-1, 7′-2,... 7′-n having a characteristic as a non-defective product manufactured accidentally among the semiconductor integrated circuits actually manufactured. Therefore, the completeness of the test program must be verified using the conductor integrated circuits 70′-1, 70-2 ′... 70′-m having characteristics as defective products. For this reason, the test program determines that all of the semiconductor integrated circuits having various characteristics to be determined as non-defective products are actually non-defective products, and all of the semiconductor integrated circuits having various characteristics to be determined as defective products are actually rejected. It was impossible as a real problem to check whether or not it was judged as a good product. In addition, it is necessary to inspect and check what kind of non-defective product or defective product each of the actually manufactured semiconductor integrated circuits has.

  Thus, an important problem in debugging a test program is that the developed test program determines that only a semiconductor integrated circuit that satisfies various conditions as a non-defective product is a non-defective product and does not satisfy various conditions as a non-defective product. Whether or not it is possible to determine that all the semiconductor integrated circuits are defective. Although debugging of a test program is usually performed using an LSI tester and a semiconductor integrated circuit that actually exists, a semiconductor integrated circuit having various conditions as a defective product from a large number of actually existing semiconductor integrated circuits It is impossible as a real problem to prepare.

That is, in waiting for the acquisition of a semiconductor integrated circuit having various conditions as a defective product that occurred by chance among the manufactured semiconductor integrated circuits or caused by variations in manufacturing conditions, In reality, there is a problem that tests cannot be performed. Therefore, it is determined that all semiconductor integrated circuits that satisfy various conditions as good products assumed by the test program are good products, and conversely, all semiconductor integrated circuits that satisfy various conditions as defective products that are assumed. It is virtually impossible to reliably verify whether it is actually possible to determine that the product is defective.
JP 2001-51025 A Web site about IMS (INTEGRATED MEASURMENT SYSTEMS, INC.) Virtual tester http://www.virtualtest.com/news/design to production 10302001.html http://www.innotech.co.jp/products/ims/ virtualtest / index.html

  However, the conventional techniques as described above have the following problems. First, IMS DVT described in Non-Patent Document 1 targets only a functional test in a test program including a plurality of measurement items and determination items, as shown in FIG. Specifically, the IMS DVT reads the input signal change timing of the input / output terminals and the signal capture timing of the output terminals, and compares them with the test pattern data described in the test program. A functional test has been realized.

  Therefore, in the prior art described in Non-Patent Document 1, it is possible to simulate a function test of a semiconductor integrated circuit to be tested on a virtual tester, but consideration is given to other tests such as a current voltage test. Therefore, since there is no description regarding the functions of the power supply circuit and the current / voltage measuring circuit in the test program, the current / voltage test cannot be performed. For this reason, the technique described in Non-Patent Document 1 cannot accurately simulate all tester operations described in the test program on a computer.

  On the other hand, the invention described in Patent Document 1 is a virtual tester constructed by modeling an LSI tester using a hardware description language that can be simulated by a computer, and debugging a test program for a functional test and a current-voltage test is actually performed. This is possible without the need to use a semiconductor integrated circuit and an LSI tester. However, this Patent Document 1 only describes that a virtual tester is constructed using an HDL description, and a functional test and a current / voltage test are performed, and a specific virtual tester implementation method is disclosed. Not.

  Furthermore, the test program reliably determines that only semiconductor integrated circuits that satisfy various conditions as good products are good products, and reliably determines that all semiconductor integrated circuits that do not satisfy various conditions as good products are defective products. It is necessary to verify whether it is possible. However, waiting for the acquisition of a semiconductor integrated circuit having various conditions as a defective product that occurred by chance among the manufactured semiconductor integrated circuits or occurred due to variations in manufacturing conditions, Has the problem that it cannot be tested. Therefore, it is determined that all semiconductor integrated circuits that satisfy various conditions as good products assumed by the test program are good products, and conversely, all semiconductor integrated circuits that satisfy various conditions as defective products that are assumed. There has been a problem that it is practically impossible to reliably verify whether it is actually possible to determine that the product is defective.

  The present invention has been made in view of the above circumstances, and a first object is to realize a configuration of an LSI tester when a virtual tester is modeled by a hardware description language, and thereby a current voltage test. It is an object of the present invention to provide a virtual tester and a test apparatus that implements such a virtual tester on a computer using a hardware description language.

  A second object of the present invention is to test a semiconductor integrated circuit modeled in a hardware description language by a virtual tester and a test apparatus realized by the first object, and to check whether a bug exists in the test program. An object of the present invention is to provide a test system for a semiconductor integrated circuit that can easily determine whether or not.

  The third object of the present invention is to determine that all non-defective products assumed by the test program are non-defective products, and conversely, determine that all defective products assumed by the test program are defective products. An object of the present invention is to provide a method for verifying a test program for a semiconductor integrated circuit capable of surely verifying whether or not it is actually possible.

  The virtual tester according to the present invention is the virtual tester modeled in the hardware description language so that the semiconductor integrated circuit modeled in the hardware description language is operated and tested on a computer according to the test program. A test program storage circuit in which a function for storing a program is modeled by a hardware description language, a test program execution circuit in which a function for executing the test program is modeled by a hardware description language, and the hardware description language And a control circuit in which a function for controlling the test program storage circuit and the test program execution circuit modeled by the hardware description language is modeled.

  The test apparatus according to the present invention models a virtual tester for testing a semiconductor integrated circuit modeled on a computer in a hardware description language by operating the computer in accordance with a test program on the computer in a hardware description language. In the test apparatus, a test program storage means in which a function for storing the test program is modeled on a computer by a hardware description language, and a function for executing the test program on the computer by a hardware description language. It is characterized by comprising a modeled test program execution means, and a control means in which functions for controlling the test program storage means and the test program execution means are modeled on a computer by a hardware description language.

  In such a virtual tester (test apparatus) of the present invention, since the functions of the program execution circuit (program execution means) and the program storage circuit (program storage means) are modeled in a hardware description language, The simulation on the computer becomes easier, and the operation of all test items described in the test program is accurately simulated.

  The virtual tester according to the present invention has a function of generating an analog value representing a power supply voltage value and / or a current value based on a test program stored in the test program storage circuit in the above-described virtual tester invention. And a power supply circuit modeled by a hardware description language.

  The test apparatus according to the present invention has a function of generating an analog value representing a power supply voltage value and / or a current value based on a test program stored in the test program storage means in the above-described test apparatus invention. And a power supply means modeled on a computer by a hardware description language.

  In such a virtual tester (test apparatus) of the present invention, a simulation is performed in which the power supply voltage value and the current value are treated as analog values by a power supply circuit (power supply means) whose function is modeled in a hardware description language. .

  Furthermore, the virtual tester according to the present invention is the above-described virtual tester invention, wherein a function of applying a current and / or voltage value to the semiconductor integrated circuit according to the execution of the test program, and a function according to the execution of the test program. A function that takes in an analog value representing a current and / or voltage value output from the semiconductor integrated circuit and a function that processes the taken-in analog value with a test program stored in the test program storage circuit using a hardware description language Further comprising a modeled current voltage measuring circuit.

  The test apparatus according to the present invention further includes a function of applying a current and / or voltage value to the semiconductor integrated circuit according to the execution of the test program, and a function according to the execution of the test program. A function for taking in an analog value representing a current and / or voltage value output from the semiconductor integrated circuit and a function for processing the taken-in analog value with a test program stored in the test program storage means by a hardware description language It further comprises current voltage measuring means modeled on a computer.

  In such a virtual tester (test apparatus) of the present invention, a simulation for handling an analog value can be performed by a current voltage measurement circuit (current voltage measurement means) whose function is modeled in a hardware description language.

  The semiconductor integrated circuit test system according to the present invention tests a semiconductor integrated circuit modeled in a hardware description language by operating it on a computer according to a test program using a virtual tester modeled in the hardware description language. In the test system for a semiconductor integrated circuit, the virtual tester includes a test program storage circuit in which a function for storing the test program is modeled by a hardware description language, and a function for executing the test program is described in hardware. A test program execution circuit modeled by a language, a test program storage circuit modeled by the hardware description language, and a control circuit modeled by a hardware description language for controlling the test program execution circuit The function for generating a condition setting signal for setting the semiconductor integrated circuit to a predetermined test state in accordance with the test program is modeled by a hardware description language, and the condition setting signal is given. A function of setting the first and second current and / or voltage values according to the condition setting signal and detecting whether or not the semiconductor integrated circuit is set to the predetermined test state according to the condition setting signal And a state detection circuit in which a function for generating the first or second current and / or voltage value according to the detection result is modeled by a hardware description language, and the virtual tester includes the state The presence or absence of a bug in the test program is determined based on the current and / or voltage value generated by the detection circuit.

  The semiconductor integrated circuit test system according to the present invention also provides a virtual tester for testing by operating a semiconductor integrated circuit modeled on a computer in a hardware description language on the computer according to the test program. In a test system for a semiconductor integrated circuit provided with a test device modeled on a computer, the test device comprises a test program storage means in which a function for storing the test program is modeled on a computer by a hardware description language , A test program execution means in which a function for executing the test program is modeled on a computer by a hardware description language, and a function for controlling the test program storage means and the test program execution means. Control means modeled on a computer by a predicate language and a function for generating a condition setting signal for setting the semiconductor integrated circuit to a predetermined test state according to the test program are modeled on a computer by a hardware description language Means for setting the first and second currents and / or voltage values according to the condition setting signal given by the condition setting signal, and the semiconductor integrated circuit has the condition A hardware description of a function for detecting whether or not the predetermined test state is set according to a setting signal and a function for generating the first or second current and / or voltage value according to the detection result A state detection unit modeled on a computer by a language, and the test apparatus is configured to generate a current and / or voltage value generated by the state detection unit. Zui and characterized that you have to determine the presence or absence of bugs in the test program.

  In such a semiconductor integrated circuit test system according to the present invention, the program execution circuit (program execution means) and the program storage circuit (program storage means) are modeled in a hardware description language. In addition to making the above simulation easier, the operation of all test items described in the test program is accurately simulated. Further, it is detected whether or not the semiconductor integrated circuit is set to a predetermined test state according to the condition setting signal, and a preset current voltage value is generated according to the detection result, so that the virtual tester (test The apparatus) can determine whether or not there is a bug in the test program based on the current voltage value.

  The semiconductor integrated circuit test system according to the present invention is the above-described semiconductor integrated circuit test system invention, wherein the virtual tester is configured to supply power supply voltage values and / or values based on a test program stored in the test program storage circuit. Or a power supply circuit in which a function for generating an analog value representing a current value is modeled by a hardware description language, and the state detection circuit has an analog value of a power supply voltage value and / or a current value generated by the power supply circuit. A function for determining whether or not an analog value representing a power supply voltage value and / or current value to be generated based on the test program is within a predetermined range is modeled by a hardware description language, and the virtual The tester determines whether or not there is a bug in the test program based on the determination result of the state detection circuit. Characterized that you have manner.

  The semiconductor integrated circuit test system according to the present invention is the above-described semiconductor integrated circuit test system invention, wherein the test apparatus is configured to supply power supply voltage values and / or values based on a test program stored in the test program storage means. Alternatively, it further includes power supply means that has a function of generating an analog value representing a current value modeled on a computer by a hardware description language, and the state detection means includes a power supply voltage value and / or current value generated by the power supply means. A function for determining whether or not an analog value of a power supply voltage value and / or current value to be generated based on the test program is within a predetermined range with respect to the analog value on the computer using a hardware description language The test apparatus includes a modeled means, and the test apparatus is configured to perform the test based on a determination result of the state detection means. Characterized in that you have to determine the presence or absence of bugs in Preparative program.

  In such a semiconductor integrated circuit test system according to the present invention, a simulation is performed in which the power supply voltage value and the current value are treated as analog values by a power supply circuit (power supply means) whose function is modeled in a hardware description language. In addition, it is possible to determine the presence or absence of a bug in the test program based on the power supply voltage value and current value that are treated as analog values.

  The semiconductor integrated circuit test system according to the present invention is the above-described semiconductor integrated circuit test system invention, wherein the state detection circuit includes the current output by the semiconductor integrated circuit in response to execution of the test program and / or A function of taking in an analog value representing a voltage value, a function of determining whether or not a current and / or voltage value to be output in accordance with execution of the test program is within a predetermined range, and a result of the determination Accordingly, the function of generating the first or second current and / or voltage value is modeled by a hardware description language, and the current / voltage measurement circuit is configured to generate the current and / or voltage generated by the state detection circuit. The presence or absence of a bug in the test program is determined based on an analog value representing the value.

  The semiconductor integrated circuit test system according to the present invention is the above-described semiconductor integrated circuit test system, wherein the state detecting means includes a current output by the semiconductor integrated circuit in response to execution of the test program and / or A function of taking in an analog value representing a voltage value, a function of determining whether or not a current and / or voltage value to be output in accordance with execution of the test program is within a predetermined range, and a result of the determination In response, the first or second current and / or voltage value generating function is modeled on a computer using a hardware description language, and the current / voltage measuring means is generated by the state detecting means. The presence or absence of a bug in the test program is determined on the basis of an analog value representing a current and / or voltage value. That.

  In such a test system for a semiconductor integrated circuit according to the present invention, the current / voltage measurement circuit (current / voltage measurement means) whose function is modeled in a hardware description language enables simulation to handle an analog value, It is possible to determine the presence or absence of a bug in the test program based on the analog value to be handled.

  The semiconductor integrated circuit test system according to the present invention is the above-described semiconductor integrated circuit test system invention, wherein the semiconductor integrated circuit includes a plurality of logic blocks modeled in a hardware description language, A function for inputting a signal from the virtual tester to the logical block to be tested according to an operation in a logical block before and after the logical block to be tested in the block, and a current output in accordance with the input signal And / or a signal transmission circuit in which a function of reading a voltage value is modeled by a hardware description language.

  The semiconductor integrated circuit test system according to the present invention is the above-described semiconductor integrated circuit test system invention, wherein the semiconductor integrated circuit includes a plurality of logic blocks modeled on a computer by a hardware description language, A function of inputting a signal from the virtual tester to the logical block to be tested according to an operation in a logical block before and after the logical block to be tested among a plurality of logical blocks, and an output according to the input signal And a function of reading out a current and / or voltage value to be signaled on a computer modeled by a hardware description language.

  In such a test system for a semiconductor integrated circuit according to the present invention, the logic blocks before and after the test target logic block among the plurality of logic blocks modeled in the hardware description language included in the semiconductor integrated circuit are used. A signal from the virtual tester (test device) is input to the logic block to be tested in a state reflecting the operation of the test, and the virtual tester (test device) is used for testing based on the current voltage value output in response to this signal. It becomes possible to determine the presence or absence of bugs in the program.

  The semiconductor integrated circuit test system according to the present invention is modeled by a hardware description language so that the semiconductor integrated circuit is determined to be non-defective by the test program in the above-described semiconductor integrated circuit test system invention. It is characterized by being.

  The semiconductor integrated circuit test system according to the present invention is the above-described semiconductor integrated circuit test system invention, wherein the semiconductor integrated circuit is determined to be non-defective by the test program on a computer using a hardware description language. It is characterized by being modeled by.

  In such a test system for a semiconductor integrated circuit according to the present invention, since the semiconductor integrated circuit is modeled in a hardware description language so that it is determined to be a non-defective product by the test program, the defective product is tested by the test program. If it is determined that there is a bug, it can be determined that there is a bug in the test program.

  A virtual tester and a test system for a semiconductor integrated circuit according to the present invention are the same as the virtual tester and the test system for a semiconductor integrated circuit in the invention described above, wherein the control circuit is an FPGA (Field Programmable) modeled in a hardware description language. Gate Array) hardware description language and / or netlist.

  A test apparatus and a semiconductor integrated circuit test system according to the present invention include an FPGA in which the control means is modeled on a computer in a hardware description language in each of the test apparatus and the semiconductor integrated circuit test system. (Field Programmable Gate Array) hardware description language and / or netlist.

  In such a test apparatus and test system for a semiconductor integrated circuit according to the present invention, an FPGA hardware description language model is used, and the netlist used there is used as it is, whereby a virtual tester FPGA is developed. .

  The semiconductor integrated circuit test program verification method according to the present invention further comprises: modeling a semiconductor integrated circuit test system and a semiconductor integrated circuit to be tested with a hardware description language and operating the semiconductor integrated circuit on a computer. In a method for verifying the completeness of a test program for a semiconductor integrated circuit for debugging a test program for a semiconductor, it is modeled by a hardware description language so that the test program for a semiconductor integrated circuit to be verified is judged as a non-defective product A semiconductor integrated circuit and a semiconductor integrated circuit modeled in a hardware description language so as to be determined as defective by the semiconductor integrated circuit test program to be verified are prepared. According to the above The semiconductor integrated circuit modeled by the hardware description language is tested so as to be judged as a defective product and the semiconductor integrated circuit modeled by the hardware description language. When the modeled semiconductor integrated circuit is determined to be a non-defective product, and the semiconductor integrated circuit modeled by a hardware description language is determined to be a defective product so as to be determined as the defective product, the semiconductor integrated circuit to be verified It is determined that the circuit test program is complete.

  In such a semiconductor integrated circuit test program verification method of the present invention, a semiconductor integrated circuit modeled in a hardware description language so as to be determined as a non-defective product is determined as a non-defective product and is determined as a defective product. When the semiconductor integrated circuit modeled in the hardware description language is determined to be defective, it is determined that the test program is complete.

  According to the virtual tester of the present invention, since the program execution circuit and the program storage circuit are modeled in the hardware description language, all the test programs are stored in the program storage circuit (virtual RAM) modeled in the hardware description language. can do. Further, according to the test apparatus of the present invention, since the program execution means and the program storage means are modeled on the computer by the hardware description language, the program storage means (virtual storage) in which all the test programs are modeled by the hardware description language. RAM). Therefore, in the virtual tester and the test apparatus of the present invention, it is easier to simulate on the computer, and a virtual tester capable of accurately simulating the test operation described in the test program is realized.

  Further, according to the virtual tester of the present invention, in the above-described invention, a virtual tester capable of simulating the power supply voltage value as an analog value is realized by the power supply circuit (virtual power supply circuit) modeled in the hardware description language. Is done. Further, according to the test apparatus of the present invention, in the above-described invention, the power supply means (virtual power supply circuit) modeled on the computer by the hardware description language can be simulated to handle the power supply voltage value as an analog value. A test device is realized. As a result, the virtual tester technology can be applied to test items other than the logical test, which is impossible with the conventional technology, and all test programs can be executed.

  Furthermore, according to the virtual tester according to the present invention, in the above-described invention, a virtual tester capable of simulating handling an analog value is realized by a current voltage measurement circuit (virtual current voltage measurement circuit) modeled in a hardware description language. Is done. Furthermore, according to the test apparatus according to the present invention, in the above-described invention, a simulation for handling an analog value is possible by means of current voltage measurement means (virtual current voltage measurement circuit) modeled on a computer by a hardware description language. A test device is realized. As a result, the virtual tester technology can be applied to test items other than the logical test, which is impossible with the conventional technology, and all test programs can be executed.

  Further, according to the test system for a semiconductor integrated circuit according to the present invention, in addition to the effect of the virtual tester described above, it is detected whether or not the semiconductor integrated circuit is set to a predetermined test state according to the condition setting signal, Since a preset current voltage value is generated according to the detection result, the virtual tester (test device) can determine the presence or absence of a bug in the test program based on the current voltage value. Debugging is easy.

  According to the semiconductor integrated circuit test system of the present invention, in the above-described invention, the power supply voltage (power supply means) modeled in the hardware description language can be used to simulate handling of the power supply voltage value as an analog value. At the same time, it is possible to determine whether or not there is a bug in the test program based on the power supply voltage value treated as an analog value, and debugging can be easily performed.

  Further, according to the test system for a semiconductor integrated circuit according to the present invention, in the above-described invention, a simulation for handling an analog value can be performed by the current-voltage measuring circuit (current-voltage measuring means) modeled in the hardware description language. At the same time, the presence or absence of a bug in the test program can be determined based on the analog value to be handled, and debugging can be easily performed.

  Further, according to the test system for a semiconductor integrated circuit according to the present invention, in the above-described invention, a test target logic block among a plurality of logic blocks modeled in a hardware description language included in the semiconductor integrated circuit is stored. A signal from the virtual tester (test device) is input to the logical block to be tested in a state reflecting the operation in the preceding and subsequent logical blocks, and the virtual tester (test) is based on the current voltage value output in response to this signal. Apparatus) can determine whether or not there is a bug in the test program, so that it is possible to determine whether or not there is a bug related to a desired logic block in the semiconductor integrated circuit in the test program. Debugging is easy.

  According to the semiconductor integrated circuit test system of the present invention, in the above-described invention, the semiconductor integrated circuit is modeled in a hardware description language so that it is determined to be a non-defective product by the test program. If it is determined that the test program is defective, it is possible to determine that there is a bug in the test program, and debugging can be performed easily.

  According to the virtual tester, the test apparatus, and the semiconductor integrated circuit test system according to the present invention, when developing the virtual tester, a model based on the hardware description language of the FPGA is used, and the net list used there is used as it is. By using it, an actual virtual tester FPGA can be developed, so that the construction and modification of an LSI tester can be developed in a short time and efficiently.

  Furthermore, according to the method for verifying a test program for a semiconductor integrated circuit according to the present invention, a semiconductor integrated circuit modeled in a hardware description language so as to be determined as a non-defective product is determined as a non-defective product and is determined as a defective product. When a semiconductor integrated circuit modeled in a hardware description language is determined to be defective, it is determined that the test program is complete, so that the completeness of the test program can be verified easily and accurately. It becomes possible. Also, it is not a semiconductor integrated circuit that has an accidental characteristic included in an actually manufactured semiconductor integrated circuit, but is theoretically modeled with a hardware description language by setting allowable values such as voltage, current value, and resistance value. Judgment can be made using the semiconductor integrated circuit, so it is possible to accurately set the judgment criteria for good and defective products set in the test program even at values close to the permissible value. It becomes possible to develop a program.

  Hereinafter, the present invention will be described in detail with reference to the drawings showing embodiments thereof. First, the virtual tester of the present invention will be described.

  FIG. 1 is a schematic diagram showing a conceptual configuration of a virtual tester of the present invention. The virtual tester 1 of the present invention includes a CPU 2 as a test program execution circuit for executing a test program, a RAM 3 as a memory circuit for storing the test program, a power supply circuit 4 for generating a power supply voltage, and a semiconductor to be tested (not shown). A current / voltage measuring circuit 5 that measures a current / voltage output from the integrated circuit and an FPGA (Field Programmable Gate Array) 20 as a control circuit that controls these elements are included. The FPGA 20 includes a PLL (Phase-Locked Loop), an ADC (analog-digital converter), a DAC (digital-analog converter), and the like, for example, a CPU, a RAM, a power supply circuit, a voltage / current application circuit, It is also possible to provide functions of the measurement circuit and the like.

  FIG. 2 is a block diagram of the functions of the virtual tester 1 of the present invention, whose conceptual configuration is shown in FIG. 1, is modeled on a computer using a hardware (HW) description language so that each block actually operates on the computer. It is a functional block diagram showing a configuration example in the case of an actual test apparatus.

  As the virtual CPU 2, an existing PLI model or circuit model can be used. PLI is a programming language interface generally used in Verilog (IEEE Std-1364). It is written in C language for simulation and written in Verilog or VHDL (VHSIC High Description Language). Acts as an interface to the simulation description of the target circuit.

  As the virtual FPGA 20, it is possible to use a net list necessary for writing a logic circuit into the FPGA and an RTL (Register Transfer Level) model used for logic circuit design.

  Further, as the virtual RAM 3, the virtual power supply circuit 4, and the virtual current voltage measurement circuit 5, the functions of parts used when configuring as an actual device are faithfully modeled and used on a computer by a hardware description language. It is possible. Specifically, with regard to the virtual power supply circuit 4, a function for outputting data of analog values corresponding to desired voltage values and current values to be generated based on a test program is modeled on a computer by a hardware description language. Has been. The virtual current voltage measurement circuit 5 corresponds to a current value and a voltage value generation function input to the test target semiconductor integrated circuit according to the test program, and a current value and voltage value output from the test target semiconductor integrated circuit. A function for inputting analog value data, determining whether the value is within an allowable value of the specification defined by the test program, and writing the result data in the virtual RAM 3 is performed by a hardware description language. Modeled above.

  By adopting the conceptual configuration as shown in FIG. 1, the virtual tester of the present invention can be constructed as a test apparatus of the present invention that actually operates on a computer as shown in FIG. At that time, only the virtual RAM 3, the virtual power supply circuit 4 and the virtual current / voltage measuring circuit 5 need only be modeled by the hardware description language, and the existing models, ie, general models, are used for the other circuits, that is, the virtual CPU 2 and the virtual FPGA 20. It is possible to use the circuit model used in On the other hand, the function description in the hardware description language of the virtual RAM 3, the virtual power supply circuit 4 and the virtual current voltage measurement circuit 5 is very simple. Therefore, it becomes very easy to realize the functions of all the components of the LSI tester having the conceptual configuration as shown in FIG. 1 on the computer using the hardware description language.

  As a hardware description language, known Verilog-HDL, VHDL, etc. can be used. In addition, a PLI model that operates as a virtual CPU 2 or a circuit description of the virtual CPU 2 is available and a CPU-dedicated compiler such as C language or BASIC used in a test program is necessary. As the CPU 2, any type such as Z80, ARM ("Advanced RISC Machine" developed by ARM Ltd.) can be used.

  Next, a description will be given by comparing the simulation execution procedure between the case of the prior art disclosed in Non-Patent Document 1 described above and the case of a test apparatus in which the virtual tester of the present invention is modeled on a computer. . FIG. 3 is a flowchart showing an example of the simulation execution procedure of the test apparatus of the present invention.

  As shown in FIG. 3, in the test apparatus of the present invention, the entire test program including a plurality of test items is extracted (step S4), and descriptions such as “for” and “if” are binary coded. Compiled for the test apparatus 1 (step S5). The entire test program compiled in this way is written in the virtual RAM 3 modeled in the hardware description language (step S6).

  Next, the virtual CPU 2 modeled in the hardware description language executes the test program (step S7). Similarly, the virtual FPGA 20, the virtual power supply circuit 4, and the virtual current voltage measurement circuit 5 modeled in the hardware description language are displayed. A test program is executed as necessary (step S8). Thereby, the operation of the test apparatus of the present invention is simulated.

  In the prior art disclosed in the above-mentioned Non-Patent Document 1, first, only a part of a plurality of test items included in a test program is extracted and compiled, and compiled data (a test program is converted into binary data). A simulation is performed by executing the coded data) by the virtual CPU 2 constructed by PLI. However, in such a conventional virtual tester, not all of the test program is used, and therefore it is impossible to accurately simulate all of the test program.

  On the other hand, as described above, in the test apparatus of the present invention, the entire test program is converted into binary code data by compiling all the source codes of the test program. The data thus binarized (binary code data) can be stored in the virtual RAM 3 modeled in the hardware description language. Therefore, the entire test program (actually its binary code) is stored in the virtual RAM 3 modeled in the hardware description language, and these test programs are virtualized by the PLI model of the virtual CPU 2 modeled in the hardware description language. Since it can be sequentially read from the RAM 2 and executed, it can be accurately processed by simulation.

  As described above, according to the test apparatus in which the virtual tester of the present invention is modeled on the computer, it is possible to execute the entire test program and realize a more accurate simulation.

  Next, the semiconductor integrated circuit test system according to the present invention including the test apparatus (virtual tester) according to the present invention as described above will be described.

  FIG. 4 is a functional block diagram showing an embodiment of a test system for a semiconductor integrated circuit of the present invention. The test apparatus 1 of the present invention shown in FIG. 2 and its functions are modeled in a hardware description language. The state detection circuit 6 and the semiconductor integrated circuit 7 are also configured. Of course, these are all configured as a simulator that is realized by software on a computer.

  As shown in FIG. 2, the test apparatus 1 includes an FPGA 20 having a function as a control circuit, and a virtual CPU 2 that is a PLI model (modeled by a hardware description language) of a CPU as a virtual test program execution circuit. A virtual RAM 3 that is a program storage circuit (modeled by a hardware description language) as a virtual memory circuit, a virtual power supply circuit 4 (modeled by a hardware description language), and a virtual current voltage measurement circuit 5 (hardware description) Modeled by language). Note that the test apparatus 1 is controlled by both the virtual CPU 2 described above and the FPGA 20 including functions of the CPU as described above.

  Reference numeral 10 denotes an input terminal for loading a test program from the outside of the test apparatus 1 and giving various instructions such as an operation start instruction, and 11 is between the virtual CPU 2 of the test apparatus 1 and the semiconductor integrated circuit 7. Input / output terminals for sending and receiving signals, 12 an output terminal for sending power supply voltage data from the virtual power supply circuit 4 in the test apparatus 1 to the state detection circuit 6, and 13 a virtual current voltage measurement circuit in the test apparatus 1 5 and an input / output terminal for transmitting / receiving data between the state detection circuit 6 and the state detection circuit 6.

  62 is an input terminal for the state detection circuit 6 to receive data from the output terminal 12, 63 is an input / output terminal for the state detection circuit 6 to send and receive data to and from the input / output terminal 13, 71 is Input / output terminals for the semiconductor integrated circuit 7 to send / receive signals to / from the input / output terminals 11 described above, 74 an output terminal for sending signals from the semiconductor integrated circuit 7 to the state detection circuit 6, and 64 from this output terminal 74 The state detection circuit 6 is an input terminal for receiving a signal.

  Hereinafter, as an example of the test items included in the test program, it is determined whether or not there is a bug in the program for measuring the voltage application current to the output terminal 74 of the semiconductor integrated circuit 7 modeled by the hardware description language. Details of the procedure will be described. However, here is an example of a test program for testing whether or not the current that can be output when the output terminal 74 of the semiconductor integrated circuit 7 is at a high level is within an allowable value. The semiconductor integrated circuit 7 itself is normally modeled in a hardware description language, and a current value that can be output when the output terminal 74 of the semiconductor integrated circuit 7 that is normally modeled is at a high level. For example, a test program is described so that the semiconductor integrated circuit 7 is determined to be a non-defective product when the current is 0.8 mA or more.

  5 and 6 show a procedure in which the state detection circuit 6 modeled in the hardware description language measures the high-level output current of the semiconductor integrated circuit 7 according to the test program, and whether or not there is a bug in the test program. It is a flowchart which shows the procedure which determines.

  First, in accordance with a test program stored in the virtual RAM 3, the test apparatus 1 adds the normal ON resistance value of the output terminal 74 of the semiconductor integrated circuit 7 to the state detection circuit 6 modeled in the hardware description language. The abnormal current value when the ON resistance value is abnormal is set in advance via the terminal 13-63 (step S10). Here, the resistance value to be set as the normal ON resistance value is a value determined in the test pattern of the test program as a normal resistance value when the output terminal 74 to be measured is at the high level output, as an example. 500Ω. In addition, as described above, the test program includes an abnormal ON resistance value when the output terminal 74 to be measured shows an abnormal ON resistance value, that is, a value other than 500Ω. However, when the current value that can be output when the output terminal 74 of the semiconductor integrated circuit 7 is at a high level is, for example, 0.8 mA or more, the semiconductor integrated circuit 7 is determined to be a non-defective product. For example, 0.5 mA is set.

  When the test is started, a test start signal is first sent from the virtual current / voltage measurement circuit 5 to the state detection circuit 6 via the terminal 13-63 according to the test program (step S11).

  Next, the test apparatus 1 sets the power supply voltage value of the semiconductor integrated circuit 7 in accordance with the test program, and the power supply voltage value in which the virtual power supply circuit 4 modeled by the hardware description language is set as an analog value is set as an analog value. Output to the state detection circuit 6 through the terminal 12-62 (step S12). Here, if the power supply voltage value set in the virtual power supply circuit 4 by the test program is 5.0 V, for example, if there is no bug in the test program, the power supply voltage value sent from the virtual power supply circuit 4 to the state detection circuit 6 is 5.0. The analog value is within a specified range centered on V (YES in step S13).

  Next, a test pattern signal is sent from the virtual CPU 2 of the test apparatus 1 via the terminals 11-71 according to the test program so that the terminal 74, which is the measurement target of the current application voltage of the semiconductor integrated circuit 7 by the test program, is in a measurable state. To the semiconductor integrated circuit 7 (step S14). Needless to say, when a correct test pattern signal is given to the semiconductor integrated circuit 7, a test program is written so that the output terminal 74 to be measured is in a high level state (YES in step S15).

  Next, the test apparatus 1 analogizes the voltage value to be applied in order to measure the output current of the output terminal 74 of the semiconductor integrated circuit 7 according to the test program stored in the virtual RAM 3 (modeled by the hardware description language). The value is set (step S16). Based on this setting, the virtual current / voltage measuring circuit 5 modeled by the hardware description language inputs a voltage value to be applied to the state detecting circuit 6 to measure the output current of the output terminal 74 of the semiconductor integrated circuit 7. Output via 13-63. Here, the voltage value applied to measure this output current is 4.5V.

  Here, if there is no bug in the test program, the voltage value to be applied set from the virtual current voltage measurement circuit 5 to the state detection circuit 6 is within a specified range centered on 4.5 V (YES in step S17).

As described above, the state detection circuit 6 has the output state of the terminal 74 to be measured by the test program of the semiconductor integrated circuit 7 modeled in the hardware description language, and two received voltage values, specifically, The power supply voltage value received from the virtual power supply circuit 4 and the applied voltage value received from the virtual current voltage measurement circuit 5 are determined in steps S17, S13, and S15, respectively. If the output state of the measurement target terminal 74 of the semiconductor integrated circuit 7 is at a high level (YES in step S15), the state detection circuit 6 is in a built-in arithmetic circuit (not shown of course, modeled by a hardware description language). “Output current value = (Power supply voltage value−Applied voltage value) / ON resistance value”, specifically “1 mA = (5.0 V−4.5 V) / 500Ω”
Is calculated (step S18). However, the “ON resistance value” is not a fixed value, and a different value is applied depending on the magnitude of the “power supply voltage”. By the way, in this example, 500Ω is set as the “ON resistance value” for 5.0V of the “power supply voltage”, but for example, when the “power supply voltage” is 3.0V, 700Ω is set as the “ON resistance value”. May be set. Then, the output current value of 1 mA obtained as a result of such calculation is sent to the virtual current voltage measurement circuit 5 via the terminal 63-13 (step S19).

  The output current value of the output terminal 74 of the semiconductor integrated circuit 7 measured by the virtual current voltage measuring circuit 5 as described above is sent to the virtual CPU 2, and in other words, the semiconductor integrated circuit 7 is a non-defective product by software, that is, by a test program. Or a defective product is determined. In this test program, as described above, when the current value that can be output when the output terminal 74 of the semiconductor integrated circuit 7 is at a high level is 0.8 mA or more, the semiconductor integrated circuit 7 is determined to be a non-defective product. Therefore, if the output current value obtained from the calculation result in step S18 is 1 mA, it is determined that the semiconductor integrated circuit 7 is a non-defective product (YES in step S20).

  As described above, the power supply voltage value generated based on the test program, the voltage value to be applied to measure the output current value from the terminal 74, the setting of the output terminal state (here, the corresponding output terminal 74 is at high level), etc. It is found that there is no mistake in the content of the test program, that is, there is no bug (step S21).

  When executing the test program as described above, the power supply voltage value, the applied voltage value, the state setting of the output terminal 74, etc. are not predetermined values or states, that is, values or states determined by the test pattern of the test program. If it is determined that the state detection circuit 6 is not “NO” in at least one of steps S13, S15, and S17, the state detection circuit 6 modeled in the hardware description language is Then, a signal of 0.5 mA which is an abnormal current value prepared in step S10 is sent to the virtual current voltage measuring circuit 5 modeled by the hardware description language via the terminal 63-13 (step S22).

  Thereby, in terms of software, in other words, the semiconductor integrated circuit 7 is determined to be defective by the test program. In this case, since it is assumed that the semiconductor integrated circuit 7 modeled by the hardware description language is normal, this means that there is a bug in the test program (step S23). Also, if NO in step S20, it means that there is a bug in the test program (step S23).

  As described above, the test program bug can be found and the test program can be debugged on the assumption that the semiconductor integrated circuit 7 modeled by the hardware description language is normal.

  Next, an example of determining whether or not a bug exists in the test program for current consumption measurement test of the semiconductor integrated circuit 7 by the semiconductor integrated circuit test system according to the present invention shown in FIG. 4 will be described.

  7 and 8 show a procedure for the state detection circuit 6 modeled by the hardware description language to measure the current consumption of the semiconductor integrated circuit 7 and a procedure to determine whether or not a bug exists in the test program. It is a flowchart to show. In this example, the test program determines that the semiconductor integrated circuit 7 is a non-defective product if the current consumption is 100 mA or less and 10 mA or more.

  First, in accordance with a test program stored in the virtual RAM 3, the test apparatus 1 includes a current consumption value during normal operation of the semiconductor integrated circuit 7 and an abnormal operation in a state detection circuit 6 modeled in a hardware description language. The current consumption value at the time is preset through the terminal 13-63 (step S30). Note that these values may be set in the state detection circuit 6 in advance before the simulation is started. Here, the current value to be set as the current consumption value during normal operation is 50 mA as an example. Further, as described above, the test program determines that the semiconductor integrated circuit 7 is a non-defective product if the current consumption is 100 mA or less (and 10 mA or more), as described above. A large value, for example 200 mA, is set.

  When the test is started, a test start signal is first sent from the virtual current voltage measurement circuit 5 to the state detection circuit 6 via the terminals 13-66 according to the test program (step S31).

  Next, the test apparatus 1 sets the power supply voltage value of the semiconductor integrated circuit 7 in accordance with the test program, and the power supply voltage value in which the virtual power supply circuit 4 modeled by the hardware description language is set as an analog value is set as an analog value. Output to the state detection circuit 6 via the terminal 12-62 (step S32). Here, if the power supply voltage value set in the virtual power supply circuit 4 by the test program is 5.0 V, for example, if there is no bug in the test program, the power supply voltage value sent from the virtual power supply circuit 4 to the state detection circuit 6 is 5.0. It falls within a specified range centered on V (YES in step S33).

  Next, a test pattern signal is continuously sent from the virtual CPU 2 of the test apparatus 1 to the semiconductor integrated circuit 7 via the terminals 11-71 according to the test program so that the current consumption of the semiconductor integrated circuit 7 can be measured. (Step S34). When a correct test pattern signal is continuously sent to the semiconductor integrated circuit 7, the output terminal 74 to be measured by the test program of the semiconductor integrated circuit 7 operates as expected, that is, a period of 10 MHz or more. Since the high level state and the low level state are repeated and the operation is repeated 10 times or more, the current consumption can be measured (YES in step S35).

  As described above, the state detection circuit 6 determines the operation state of the measurement target terminal 74 of the semiconductor integrated circuit 7 modeled by the hardware description language and the power supply voltage value received from the virtual power supply circuit 4 in steps S35 and S35, respectively. The determination is made in S33. Then, the operation state of the measurement target terminal 74 of the semiconductor integrated circuit 7 is set in the test program, and the high level state and the low level state are repeated at a cycle of 10 MHz or more, and the number of repetitions is 10 times or more. If the operation is performed as expected (YES in step S35), it is assumed that the semiconductor integrated circuit 7 is operating normally, and the state detection circuit 6 virtually uses the 50 mA signal set in step S30 as a normal current consumption value. The current is sent to the current / voltage measuring circuit 5 via the terminal 63-13 (step S36).

  On the other hand, if NO in step S35, that is, if the output terminal 74 to be measured by the test program does not perform the expected operation set by the test program, specifically, the measurement target of the semiconductor integrated circuit 7 is measured. When the state of the terminal 74 does not repeat the high level state and the low level state with a cycle of 10 MHz or more, or when the repetition is stopped before the number of repetitions is less than 10, the semiconductor integrated circuit 7 Assuming that the normal operation according to the given test pattern signal is not performed, the state detection circuit 6 supplies the 200 mA signal set in step S30 as a current consumption value during abnormal operation to the virtual current voltage measurement circuit 5 63-13 is sent (step S39).

  As described above, the current consumption value given from the state detection circuit 6 to the virtual current voltage measurement circuit 5 is sent to the virtual CPU 2, and in terms of software, in other words, whether the semiconductor integrated circuit 7 is a non-defective product by the test program. Processing for determining whether the product is defective is performed. In this test program, as described above, the semiconductor integrated circuit 7 is set to be judged as a non-defective product when the current consumption value of the output terminal 74 of the semiconductor integrated circuit 7 is 100 mA or less and 10 mA or more. If the current consumption value obtained by the virtual current voltage measurement circuit 5 is 50 mA, it is determined that the semiconductor integrated circuit 7 is a non-defective product (YES in step S37).

  As described above, the power supply voltage value generated based on the test program, the operation state of the output terminal (here, the corresponding output terminal 74 repeats the high level state and the low level state at a cycle of 10 MHz or more, and the number of repetitions is 10 times. It turns out that there is no mistake in the content of the test program, i.e., there are no bugs (step S38).

  When executing the test program as described above, the power supply voltage value, the operation state of the output terminal 74, etc. are not predetermined values or states, that is, not the values or states determined by the test pattern of the test program. If found, specifically, if “NO” in at least one of steps S33 and S35, the state detection circuit 6 modeled in the hardware description language is prepared in advance in step S30. The signal of 200 mA that is the current consumption value at the time of abnormality is sent to the virtual current voltage measurement circuit 5 modeled by the hardware description language via the terminal 63-13 (step S39).

  Thereby, in terms of software, in other words, the semiconductor integrated circuit 7 is determined to be defective by the test program. In this case, since the semiconductor integrated circuit 7 modeled by the hardware description language is assumed to be normal, it means that there is a bug in the test program (step S40). Also, if NO in step S37, this means that there is a bug in the test program (step S40).

  As described above, the test program bug can be found and the test program can be debugged on the assumption that the semiconductor integrated circuit 7 modeled by the hardware description language is normal.

  Next, an example of determining whether or not there is a bug in the test program for quiescent current measurement test of the semiconductor integrated circuit 7 by the semiconductor integrated circuit test system according to the present invention shown in FIG. 4 will be described. The following description is an example when the output terminal of the semiconductor integrated circuit 7 at rest is at a low level.

  When the semiconductor integrated circuit 7 is stationary, all output terminals of the semiconductor integrated circuit 7 are at a low level. Therefore, although not shown in FIG. 4, the state detection circuit 6 includes input terminals connected to all the output terminals of the semiconductor integrated circuit 7 on a one-to-one basis. However, in the following description, all output terminals of the semiconductor integrated circuit 7 are represented by output terminals 74 and all input terminals of the state detection circuit 6 are represented by input terminals 64.

  FIG. 9 and FIG. 10 show a procedure for setting conditions for causing the semiconductor integrated circuit 7 to be in a stationary state in order for the state detecting circuit 6 modeled by the hardware description language to measure the quiescent current of the semiconductor integrated circuit 7. 5 is a flowchart showing a procedure for determining whether or not a bug exists in a test program. In this example, the test program determines that the semiconductor integrated circuit 7 is a good product if the quiescent current is 10 μA or less.

  The details of the procedure for determining whether or not there is a bug in the test program of the quiescent current measurement test of the power supply terminal using the semiconductor integrated circuit 7 modeled by the hardware description language will be described below.

  First, in accordance with a test program stored in the virtual RAM 3, the test apparatus 1 correctly sets the setting conditions for setting the semiconductor integrated circuit 7 in a stationary state in the state detection circuit 6 modeled by the hardware description language. The current value at the time and the current value at the time of abnormality setting are set in advance via the terminal 13-63 (step S50). Note that these values may be set in the state detection circuit 6 in advance before the simulation is started. Here, 5 μA is set as an example of the current value at the correct setting. As described above, the current value at the time of abnormality setting is determined to be a non-defective semiconductor integrated circuit 7 if the test program has a quiescent current value of 10 μA or less. Is set.

  When the test is started, a test start signal is first sent from the virtual current voltage measurement circuit 5 to the state detection circuit 6 via the terminal 13-63 according to the test program (step S51).

  Next, the test apparatus 1 sets the power supply voltage value of the semiconductor integrated circuit 7 in accordance with the test program, and the power supply voltage value in which the virtual power supply circuit 4 modeled by the hardware description language is set as an analog value is set as an analog value. It outputs to the state detection circuit 6 via the terminal 12-62 (step S52). Here, if the power supply voltage value set in the virtual power supply circuit 4 by the test program is 5.0 V, for example, if there is no bug in the test program, the power supply voltage value sent from the virtual power supply circuit 4 to the state detection circuit 6 is 5.0. It falls within a specified range centered on V (YES in step S53).

  Next, a test pattern signal for bringing the semiconductor integrated circuit 7 into a static state is generated according to a test program so that the current at rest of the semiconductor integrated circuit 7 can be measured. The data is sent from the CPU 2 to the semiconductor integrated circuit 7 via the terminal 11-71 (step S54). When the correct test pattern signal is given to the semiconductor integrated circuit 7, in other words, when the correct condition for setting the semiconductor integrated circuit 7 to the stationary state is set by the test program, the semiconductor integrated circuit 7 is brought into the stationary state. Thus, all the output terminals 74 become low level (YES in step S55).

  As described above, the state detection circuit 6 determines the levels of all the output terminals 74 of the semiconductor integrated circuit 7 modeled by the hardware description language and the power supply voltage value received from the virtual power supply circuit 4 in steps S55, S55, The determination is made in S53. If all the output terminals 74 of the semiconductor integrated circuit 7 are at a low level (YES in step S55), the semiconductor integrated circuit 7 is correctly set to a stationary state by the test program and the current at rest is measured. The state detection circuit 6 sends the signal of 5 μA set in step S50 as the current value at the normal setting to the virtual current voltage measurement circuit 5 via the terminal 63-13 (step 63). S56).

  On the other hand, if NO in step S55, specifically, if any of the output terminals of the semiconductor integrated circuit 7 is at a high level, the semiconductor integrated circuit 7 is not set to a stationary state, Therefore, assuming that the current at rest cannot be measured, the state detection circuit 6 sends the 100 μA signal set in step S50 to the virtual current voltage measurement circuit 5 as the current value at the time of abnormality setting. Send (step S59).

  As described above, the current value supplied from the state detection circuit 6 to the virtual current voltage measurement circuit 5 is sent to the virtual CPU 2, and in terms of software, in other words, whether or not the semiconductor integrated circuit 7 is a non-defective product by the test program. A process for determining whether the product is non-defective is performed. In this test program, as described above, since the semiconductor integrated circuit 7 is determined to be a non-defective product when the quiescent current value of the semiconductor integrated circuit 7 is 10 μA or less, the virtual current voltage measurement circuit If the static current value obtained by 5 is 5 μA, it is determined that the semiconductor integrated circuit 7 is a non-defective product (YES in step S57).

  As described above, the contents of the test program for setting the power supply voltage value generated based on the test program, the conditions for setting the semiconductor integrated circuit 7 to the stationary state (in this case, all output terminals are at low level), etc. It turns out that there is no mistake, that is, no bug (step S58).

  When executing the test program as described above, the power supply voltage value, the level state of the output terminal 74, etc. are not predetermined values and states, that is, not the values and states determined by the test pattern of the test program. If it is found, specifically, if “NO” in at least one of steps S53 and S55, the state detection circuit 6 modeled in the hardware description language is prepared in advance in step S50. A signal of 100 μA, which is the current value at the time of abnormality setting, is sent to the virtual current voltage measurement circuit 5 modeled by the hardware description language (step S59).

  Thereby, in terms of software, in other words, the semiconductor integrated circuit 7 is determined to be defective by the test program. In this case, since the semiconductor integrated circuit 7 modeled by the hardware description language is assumed to be normal, this means that there is a bug in the test program (step S60). Also, if NO in step S57, this means that there is a bug in the test program (step S60).

  As described above, the test program bug can be found and the test program can be debugged on the assumption that the semiconductor integrated circuit 7 modeled by the hardware description language is normal.

  Next, a configuration for determining the internal state of the semiconductor integrated circuit 7 will be described as another embodiment of the test system for a semiconductor integrated circuit according to the present invention.

  FIG. 11 is a functional block diagram showing another embodiment of a test system for a semiconductor integrated circuit according to the present invention, and a signal transmission circuit instead of the state detection circuit 6 provided in the embodiment shown in FIG. 8 is provided between the test apparatus 1 and the semiconductor integrated circuit 7. Needless to say, this signal transmission circuit 8 is also modeled in a hardware description language.

  The signal transmission circuit 8 is modeled by a hardware description language so that the current voltage value at a desired position inside the semiconductor integrated circuit 7 modeled by the hardware description language can be measured and determined. ing. This will be described in detail below.

  FIG. 12 is a block diagram showing the internal configuration of the semiconductor integrated circuit 7 and the internal configuration of the signal transmission circuit 8 in the test system for a semiconductor integrated circuit of the present invention shown in FIG. FIG.

  Usually, the semiconductor integrated circuit 7 is configured so that the processing of the current voltage value is completed inside, so that the connection terminal for reading the current voltage value from a specific position inside the semiconductor integrated circuit 7 to the outside is a hard terminal. It does not exist as the uppermost terminal (specifically, a terminal directly connected to the outside) of the semiconductor integrated circuit 7 modeled by the wear description language. That is, the general input / output terminal 71 of the semiconductor integrated circuit 7 shown in FIG. 12 is not the highest terminal of the semiconductor integrated circuit 7 modeled by the hardware description language. Therefore, it is impossible to measure the current voltage value at a desired position inside the semiconductor integrated circuit 7 only with the test apparatus 1 of the present invention as described above.

  Further, a connection terminal for externally writing a current voltage value to a specific position inside the semiconductor integrated circuit 7 modeled by the hardware description language does not exist as the uppermost terminal of the semiconductor integrated circuit. In order to measure the current voltage value inside the semiconductor integrated circuit 7 modeled by the hardware description language, a specific logic circuit inside the semiconductor integrated circuit 7 is directly accessed, a signal is input, and the result is generated. It is necessary to read out the current voltage value directly from the inside of the semiconductor integrated circuit 7 to the outside.

  However, even if a signal is input by directly accessing a desired logic circuit as described above and a current voltage value generated by the desired logic circuit is read as a result, the preceding stage (signal flow) of the desired logic circuit is obtained. Of the logic circuit group provided upstream) of the logic circuit group (input condition) and the operation condition (output condition) of the logic circuit group provided downstream of the desired logic circuit (downstream of the signal flow) Both must be in a situation where they are not reflected. Such a situation is not a problem as long as the circuit configuration is such that the desired logic circuit simply processes the signal input from the preceding logic circuit group and outputs it to the succeeding logic circuit group. In the case of a circuit in which a feedback loop is formed before and after the simulation, it is impossible to perform a simulation that correctly reflects the state of each logic circuit through which a signal should normally pass.

  In order to solve such problems, the semiconductor integrated circuit test system according to the present invention is modeled by a hardware description language in a predetermined position of a logic circuit group before and after a desired logic circuit in the semiconductor integrated circuit 7. The signal transmission circuit 8 having a switch circuit modeled by a hardware description language so as to be turned on / off in conjunction with the on / off operation of the switch circuit in the semiconductor integrated circuit 7. 11 is arranged between the test apparatus 1 and the semiconductor integrated circuit 7 as shown in FIG.

  As shown in FIG. 11, the signal transmission circuit 8 is connected to the test apparatus 1, as shown in FIG. 11, an input terminal 82 that receives a signal output from the terminal 12 by the virtual power supply circuit 4, and an input / output terminal 13 of the virtual current voltage measurement circuit 5. And an input / output terminal 83 for inputting / outputting a signal between them. Further, as shown in FIG. 11, the signal transmission circuit 8 is connected to the semiconductor integrated circuit 7, as shown in FIG. 11, an output terminal 85 for outputting a signal to the semiconductor integrated circuit 7, and a signal for inputting a signal from the semiconductor integrated circuit 7. And an input terminal 86.

  As shown in FIG. 12, the signal transmission circuit 8 is a desired logic circuit inside the semiconductor integrated circuit 7, that is, a logic circuit that directly inputs a signal and inputs a signal and wants to read a current voltage value generated as a result. It is modeled by a hardware description language so that a signal is directly given to the processing circuit 702 and a current voltage value obtained as a result of processing the given signal by the arithmetic processing circuit 702 is directly read and measured.

  In this embodiment, a real number conversion circuit 701 and a digital conversion circuit 703 are arranged before and after the arithmetic processing circuit 702 which is a desired logic circuit. The signal output from the logic circuit group 700 in the previous stage is converted into an analog signal representing a real value by the real number conversion circuit 701. The arithmetic processing circuit 702 performs a predetermined operation on the analog signal, and the result is converted into a digital conversion circuit. 703 converts it into a digital signal and outputs it to the logic circuit group 704 in the subsequent stage.

  Switch circuits 7S1 and 7S2 are provided at predetermined positions of the logic circuit group 700 arranged in the input stage of the arithmetic processing circuit 702 (in this example, positions before and after the logic circuit group 700). The on / off control signals of 7S1 and 7S2 are input signals from the virtual current voltage measurement circuit 5 of the test apparatus 1 via the logic gate 801 (assumed to be an AND gate in the example shown in FIG. 12) in the signal transmission circuit 8. Is an on / off control signal for the switch circuit 8S1 for on / off control.

  In this example, a signal is output from the logic circuit group 700 to the real number conversion circuit 701 when both the switch circuits 7S1 and 7S2 before and after the logic circuit group 700 in the preceding stage of the arithmetic processing circuit 702 that is a desired logic circuit are turned on. At this time, however, the switch circuit 8S1 in the signal transmission circuit 8 is also turned on by the signal output from the logic gate 801 at the same time. As a result, the input signal from the current / voltage measurement circuit 5 of the test apparatus 1 is directly input to the arithmetic processing circuit 702 via the signal line 73 via the input / output terminal 83 and the output terminal 85. Thus, the signal input from the signal transmission circuit 8 to the arithmetic processing circuit 702 through the signal line 73 simulates the signal supplied from the real number conversion circuit 701 to the arithmetic processing circuit 702.

  Switch circuits 7S3 and 7S4 are provided at predetermined positions (positions before and after the logic circuit group 704 in this example) of the logic circuit group 704 arranged at the output stage of the arithmetic processing circuit 702 which is a desired logic circuit. At the same time, the on / off control signals of these switch circuits 7S3 and 7S4 are measured through the logic gate 802 (assumed to be an AND gate in the example shown in FIG. 12) in the signal transmission circuit 8 to measure the virtual current voltage of the test apparatus 1. The output signal to the circuit 5 is used as an on / off control signal for the switch circuit 8S2 for on / off control.

  In this example, the output signal of the digital conversion circuit 703 is input to the logic circuit group 704 when both the switch circuits 7S3 and 7S4 before and after the logic circuit group 704 in the subsequent stage of the arithmetic processing circuit 702 which is a desired logic circuit are turned on. However, at this time, the switch circuit 8S2 in the signal transmission circuit 8 is also turned on by the signal output from the logic gate 802 at the same time. As a result, an output signal from the arithmetic processing circuit 702 is output from the signal line 72 via the input terminal 86 and the input / output terminal 83 of the signal transmission circuit 8 and is input to the current-voltage measurement circuit circuit 5. Thus, the signal output from the arithmetic processing circuit 702 to the outside through the signal line 72 and input to the virtual current voltage measuring circuit 5 is arithmetically processed by the signal input from the virtual current voltage measuring circuit 5 to the arithmetic processing circuit 702. The result processed by the circuit 702 is simulated.

  Although the ON / OFF control signals of the switch circuits 7S1, 7S2, 7S3, and 7S4 in the semiconductor integrated circuit 7 are not shown, the semiconductor integrated circuit is based on a signal that is sent via the terminal 11-71 based on a test program. It is generated in the circuit 7.

  The signal transmission circuit 8 modeled by such a hardware description language enables correct simulation reflecting the state of each logic circuit through which the signal originally passes before and after the desired logic circuit.

  By using such a technique, it is not necessary to provide a current voltage terminal at the top of the semiconductor integrated circuit 7 modeled by the hardware description language, and simulation using the current voltage value can be performed on the logic simulator. .

  Next, the method of the present invention for verifying the completeness of a test program for a semiconductor integrated circuit will be described.

  FIG. 13 is a schematic diagram for explaining a procedure for verifying the completeness of a test program for a semiconductor integrated circuit using the test apparatus 1 of the present invention. As described above, in the test apparatus 1 according to the present invention, the test program TP is loaded into the test apparatus 1, more specifically, the virtual RAM 3, and the test is performed on the semiconductor integrated circuit 7 modeled in the hardware description language. Do. Therefore, here, the test program TP is loaded into the virtual RAM 3 of the test apparatus 1 and the test is performed on the semiconductor integrated circuit group 70 modeled in the hardware description language. When such a configuration is adopted, as the semiconductor integrated circuit group 70 modeled in the hardware description language, the semiconductor integrated circuits 7-1 and 7- having various characteristics (characteristics that fall within the design specifications) that should be determined as non-defective products. Semiconductor integrated circuits 70-1, 70-2… 70 that model all of 2… 7-n in hardware description language and have various characteristics (characteristics that deviate from design specifications) that should be judged as defective products It is easy to model all of -m in a hardware description language.

  Therefore, all the semiconductor integrated circuits modeled in the hardware description language to be determined as non-defective products by the semiconductor integrated circuit test program are actually determined as non-defective products and modeled in the hardware description language to be determined as defective products. It is possible to confirm whether or not all the semiconductor integrated times are actually judged as defective products.

  FIG. 14 is a flowchart showing a procedure for implementing a method for verifying a test program for a semiconductor integrated circuit using such a test apparatus of the present invention. Hereinafter, the implementation procedure of the method of the present invention will be specifically described.

  First, a test program to be verified and a semiconductor integrated circuit 7 modeled in a hardware description language so as to have various characteristics to be determined as good and defective by the test program are prepared (step S80). Next, the test program is loaded into the virtual RAM 3 of the test apparatus 1 of the present invention (step S81). Since the preparation is completed as described above, the test by the test apparatus 1 of the present invention is executed for all the semiconductor integrated circuits 7 modeled in the prepared hardware description language (step S82).

  As a result of this test, all of the semiconductor integrated circuits 7 modeled in the hardware description language so as to have various characteristics to be determined as prepared non-defective products are determined as non-defective products (YES in step S83), and prepared defective products are also obtained. If all the semiconductor integrated circuits 7 modeled in the hardware description language having various characteristics to be determined are determined as defective products (YES in step S84), it is determined that there is no problem in the degree of completion of the test program. (Step S85).

  On the other hand, if at least one of the semiconductor integrated circuits 7 modeled in the hardware description language having various characteristics to be determined as good products in step S83 is determined to be defective (NO in step S83), or If any one of the semiconductor integrated circuits 7 modeled in the hardware description language having characteristics to be determined as various defective products is determined to be a non-defective product (NO in step S84), the completeness of the test program Is determined to have a problem (step S86).

  Thus, when verifying the completeness of a test program for a semiconductor integrated circuit using the test apparatus 1 of the present invention, good and defective semiconductor integrated circuits having various characteristics are modeled by a hardware description language. Therefore, before the actual semiconductor integrated circuit is manufactured and even after the actual semiconductor integrated circuit is manufactured, it is assumed that all theoretically possible characteristics are assumed. The completeness of the test program can be verified.

It is a schematic diagram which shows the notional structure of the virtual tester of this invention. FIG. 1 is a functional block diagram showing a configuration example of a test apparatus in which each block of the virtual tester of the present invention whose conceptual configuration is shown in FIG. 1 is modeled by a hardware description language so as to actually operate on a computer. It is a flowchart which shows an example of the implementation procedure of the simulation by the test apparatus of this invention. 1 is a functional block diagram showing an embodiment of a test system for a semiconductor integrated circuit according to the present invention. A procedure for the state detection circuit modeled by the hardware description language of the test system for a semiconductor integrated circuit of the present invention to measure the high-level output current of the semiconductor integrated circuit according to the test program, and whether there is a bug in the test program It is a flowchart which shows the procedure which determines whether or not. A procedure for the state detection circuit modeled by the hardware description language of the test system for a semiconductor integrated circuit of the present invention to measure the high-level output current of the semiconductor integrated circuit according to the test program, and whether there is a bug in the test program It is a flowchart which shows the procedure which determines whether or not. Procedure for measuring state of consumption current of semiconductor integrated circuit by state detection circuit modeled by hardware description language of test system for semiconductor integrated circuit of the present invention and procedure for determining whether or not a bug exists in the test program It is a flowchart which shows. Procedure for measuring state of consumption current of semiconductor integrated circuit by state detection circuit modeled by hardware description language of test system for semiconductor integrated circuit of the present invention and procedure for determining whether or not a bug exists in the test program It is a flowchart which shows. Procedure for setting a condition for a semiconductor integrated circuit to be in a stationary state so that the state detection circuit modeled by the hardware description language of the semiconductor integrated circuit test system of the present invention measures the quiescent current of the semiconductor integrated circuit, and 5 is a flowchart showing a procedure for determining whether or not a bug exists in a test program. Procedure for setting a condition for a semiconductor integrated circuit to be in a stationary state so that the state detection circuit modeled by the hardware description language of the semiconductor integrated circuit test system of the present invention measures the quiescent current of the semiconductor integrated circuit, and 5 is a flowchart showing a procedure for determining whether or not a bug exists in a test program. It is a functional block diagram which shows other embodiment of the test system for semiconductor integrated circuits of this invention. 12 is a block diagram for illustrating an internal configuration of the semiconductor integrated circuit of the test system for a semiconductor integrated circuit of the present invention shown in FIG. It is a schematic diagram for demonstrating the procedure at the time of verifying the completeness of the test program for semiconductor integrated circuits by the method of this invention. It is a flowchart which shows the procedure for enforcing the verification method of the test program for semiconductor integrated circuits of this invention. It is a flowchart which shows an example of the implementation procedure of the simulation by the virtual tester of a prior art. It is a schematic diagram explaining the conventional method for verifying the completeness of the test program for semiconductor integrated circuits.

Explanation of symbols

1 Virtual tester (test equipment)
2 Virtual CPU (CPU PLI model)
3 Virtual RAM
4 Virtual Power Supply Circuit 5 Virtual Current Voltage Measurement Circuit 6 State Detection Circuit 7 Semiconductor Integrated Circuit 8 Signal Transmission Circuit 20 Virtual FPGA
70 Semiconductor Integrated Circuit Group 700 Logic Circuit Group 701 Real Number Conversion Circuit 702 Arithmetic Processing Circuit 703 Digital Conversion Circuit 704 Logic Circuit Group 7S1 Switch Circuit 7S2 Switch Circuit 7S3 Switch Circuit 7S4 Switch Circuit 8S1 Switch Circuit 8S2 Switch Circuit 801 Logic Gate 802 Logic Gate

Claims (21)

In a virtual tester modeled with a hardware description language so that a semiconductor integrated circuit modeled with a hardware description language is operated on a computer according to a test program and tested.
A test program storage circuit in which a function for storing the test program is modeled by a hardware description language;
A test program execution circuit in which a function for executing the test program is modeled by a hardware description language;
A virtual tester comprising: a test program storage circuit modeled by the hardware description language; and a control circuit modeled by a hardware description language with a function for controlling the test program execution circuit.   It further includes a power supply circuit in which a function for generating an analog value representing a power supply voltage value and / or a current value based on a test program stored in the test program storage circuit is modeled by a hardware description language. The virtual tester according to claim 1.   A function of applying a current and / or voltage value to the semiconductor integrated circuit according to the execution of the test program; and an analog value representing the current and / or voltage value output from the semiconductor integrated circuit according to the execution of the test program And a current-voltage measuring circuit that models a function that reads the analog value that has been taken in by a test program stored in the test program storage circuit using a hardware description language. 2. The virtual tester according to 2.   4. The control circuit according to claim 1, wherein the control circuit is configured using a hardware description language and / or a netlist of an FPGA (Field Programmable Gate Array) modeled by a hardware description language. The virtual tester described in Crab. In a semiconductor integrated circuit test system for testing a semiconductor integrated circuit modeled in a hardware description language by operating it on a computer according to a test program by a virtual tester modeled in a hardware description language,
The virtual tester includes a test program storage circuit in which a function for storing the test program is modeled by a hardware description language, and a test program execution in which a function for executing the test program is modeled by a hardware description language A test program storage circuit modeled by the hardware description language and a control circuit modeled by a hardware description language for controlling a function for controlling the test program execution circuit. A function that generates a condition setting signal for setting a predetermined test state according to a program is modeled by a hardware description language,
A function of setting the first and second currents and / or voltage values according to the condition setting signal given by the condition setting signal; and the semiconductor integrated circuit according to the condition setting signal. A state in which a function for detecting whether or not a predetermined test state is set and a function for generating the first or second current and / or voltage value according to the detection result are modeled by a hardware description language Including a detection circuit,
The test system for a semiconductor integrated circuit, wherein the virtual tester determines whether or not there is a bug in the test program based on a current and / or voltage value generated by the state detection circuit. The virtual tester further includes a power supply circuit in which a function for generating an analog value representing a power supply voltage value and / or a current value based on a test program stored in the test program storage circuit is modeled by a hardware description language. ,
The state detection circuit is configured such that an analog value of a power supply voltage value and / or current value generated by the power supply circuit is predetermined with respect to an analog value representing a power supply voltage value and / or current value to be generated based on the test program. The function to determine whether it is within the range is modeled by a hardware description language,
6. The semiconductor integrated circuit test system according to claim 5, wherein the virtual tester determines whether or not a bug exists in the test program based on a determination result of the state detection circuit. The state detection circuit has a function of taking in an analog value representing a current and / or voltage value output by the semiconductor integrated circuit in response to execution of the test program, and a current to be output in response to execution of the test program and A hardware description language having a function for determining whether or not a voltage value is within a predetermined range and a function for generating the first or second current and / or voltage value according to the determination result Is modeled by
The current / voltage measurement circuit is configured to determine whether or not there is a bug in the test program based on an analog value representing a current and / or voltage value generated by the state detection circuit. 7. A test system for a semiconductor integrated circuit according to 6. The semiconductor integrated circuit includes a plurality of logic blocks modeled by a hardware description language,
A function of inputting a signal from the virtual tester to the logical block to be tested in response to an operation in a logical block before and after the logical block to be tested among the plurality of logical blocks, and according to the input signal 8. The test system for a semiconductor integrated circuit according to claim 5, further comprising a signal transmission circuit in which a function of reading an output current and / or voltage value is modeled by a hardware description language.   9. The test system for a semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is modeled by a hardware description language so that the test program determines that the semiconductor integrated circuit is a non-defective product. .   10. The control circuit according to claim 5, wherein the control circuit is configured using a hardware description language and / or a netlist of an FPGA (Field Programmable Gate Array) modeled by a hardware description language. A test system for a semiconductor integrated circuit according to claim 1. In a test apparatus in which a virtual tester for testing a semiconductor integrated circuit modeled on a computer in a hardware description language by operating the computer in accordance with a test program on the computer in a hardware description language,
A test program storage means in which a function for storing the test program is modeled on a computer by a hardware description language;
A test program execution means in which a function for executing the test program is modeled on a computer by a hardware description language;
A test apparatus comprising: control means for modeling a function for controlling the test program storage means and the test program execution means on a computer using a hardware description language.   Further provided is a power supply unit that models a function of generating an analog value representing a power supply voltage value and / or a current value based on a test program stored in the test program storage unit on a computer using a hardware description language. The test apparatus according to claim 11.   A function of applying a current and / or voltage value to the semiconductor integrated circuit according to the execution of the test program; and an analog value representing the current and / or voltage value output from the semiconductor integrated circuit according to the execution of the test program And a current voltage measuring means in which a function for processing the acquired analog value with a test program stored in the test program storage means is modeled on a computer by a hardware description language. The test apparatus according to claim 12.   12. The control means is configured using an FPGA (Field Programmable Gate Array) hardware description language and / or a netlist modeled on a computer in a hardware description language. 14. The test apparatus according to any one of 13. A semiconductor integrated circuit having a test apparatus in which a virtual tester for testing a semiconductor integrated circuit modeled on a computer in a hardware description language by operating on the computer according to a test program is modeled on the computer in a hardware description language In the test system for
The test apparatus includes a test program storage unit in which a function for storing the test program is modeled on a computer by a hardware description language, and a function for executing the test program on the computer by a hardware description language. Modeled test program execution means, control means for modeling the function for controlling the test program storage means and test program execution means on a computer by a hardware description language, and the semiconductor integrated circuit according to the test program A means for modeling a function setting signal for setting a predetermined test state on a computer by a hardware description language;
A function of setting the first and second currents and / or voltage values according to the condition setting signal given by the condition setting signal; and the semiconductor integrated circuit according to the condition setting signal. A function for detecting whether or not a predetermined test state has been set and a function for generating the first or second current and / or voltage value according to the detection result are modeled on a computer using a hardware description language. Equipped with a state detection means
The test system for a semiconductor integrated circuit, wherein the test apparatus determines whether or not there is a bug in the test program based on the current and / or voltage value generated by the state detection means. The test apparatus includes a power supply means in which a function for generating an analog value representing a power supply voltage value and / or current value based on a test program stored in the test program storage means is modeled on a computer by a hardware description language. Further comprising
The state detection means is predetermined for an analog value representing a power supply voltage value and / or a current value to be generated based on the test program. Having means for modeling on a computer by a hardware description language to determine whether it is within a range;
16. The semiconductor integrated circuit test system according to claim 15, wherein the test apparatus determines whether or not a bug exists in the test program based on a determination result of the state detection unit. The state detection means includes a function of taking in an analog value representing a current and / or voltage value output by the semiconductor integrated circuit in response to execution of the test program, and a current to be output in response to execution of the test program and A hardware description language having a function for determining whether or not a voltage value is within a predetermined range and a function for generating the first or second current and / or voltage value according to the determination result Having means modeled on a computer by
The current voltage measurement unit is configured to determine whether or not there is a bug in the test program based on an analog value representing a current and / or voltage value generated by the state detection unit. 16. A test system for a semiconductor integrated circuit according to 16. The semiconductor integrated circuit includes a plurality of logic blocks modeled on a computer by a hardware description language,
A function of inputting a signal from the virtual tester to the logical block to be tested in response to an operation in a logical block before and after the logical block to be tested among the plurality of logical blocks, and according to the input signal 18. The semiconductor integrated circuit device according to claim 15, further comprising: a signal transmission unit that models a function of reading an output current and / or voltage value on a computer using a hardware description language. Test system.   19. The semiconductor integrated circuit according to claim 15, wherein the semiconductor integrated circuit is modeled on a computer by a hardware description language so that the test program determines that the semiconductor integrated circuit is a non-defective product. For test system.   16. The control means is configured by using a hardware description language and / or netlist of FPGA (Field Programmable Gate Array) modeled on a computer by a hardware description language. 20. The test system for a semiconductor integrated circuit according to any one of 19 above. A test program for a semiconductor integrated circuit for debugging a test program for a semiconductor integrated circuit by modeling a semiconductor integrated circuit test system and a semiconductor integrated circuit to be tested in a hardware description language and operating them on a computer In the method of verifying completeness,
A semiconductor integrated circuit modeled in a hardware description language so as to be judged as a non-defective product by a test program for a semiconductor integrated circuit to be verified, and a hardware so as to be judged as a defective product by a test program for a semiconductor integrated circuit to be verified A semiconductor integrated circuit modeled in a hardware description language,
According to the test program for the semiconductor integrated circuit to be verified, the semiconductor integrated circuit modeled by the hardware description language so as to be determined as the non-defective product and the hardware description language modeled as determined as the defective product Testing semiconductor integrated circuits,
A semiconductor integrated circuit modeled in a hardware description language so as to be determined as the non-defective product is determined as a non-defective product, and a semiconductor integrated circuit modeled in the hardware description language as determined as the defective product is defective. When it is determined that the test program for the semiconductor integrated circuit is determined to be complete, the method for verifying the test program for the semiconductor integrated circuit is characterized in that:

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