JP4194959B2 - Simulation analysis system, accelerator device and emulator device - Google Patents

Description

  The present invention relates to a simulation analysis system, an accelerator device, and an emulator device, and more specifically, when a result of operation verification of a circuit to be verified by a programmable device is different from a result of operation verification of a circuit to be verified by a CAD simulator. Further, the present invention relates to an improvement of a simulation analysis system for analyzing the mismatched portion.

  Conventionally, an operation check for writing an electric circuit logically verified by a CAD (Computer Aided Design) simulator into a programmable device and checking whether the electric circuit actually operates correctly has been performed. When the operation result by the programmable device is different from the simulation result by the CAD simulator, the output waveform and the signal state in the programmable device are displayed using a logic analyzer, an internal node trace tool, or the like, and the mismatched portion is analyzed.

  In the analysis of such inconsistencies, by comparing with the simulation of the electric circuit by the CAD simulator, it is a malfunction on the programmable device, or on a peripheral circuit such as an input / output interface that performs input / output control with a peripheral device. It is possible to isolate a defect location as to whether it is a defect in However, since the operation verification of the circuit to be verified in the programmable device and the CAD simulator is performed individually, comparison of the verification results is not easy, and there is a problem that it takes a lot of time to identify the cause of the operation failure.

In addition, acceleration technology and emulation technology have been conventionally used to speed up logic verification of electrical circuits and to quickly and quickly perform operation verification in combination with software. For example, writing a circuit to be verified in a programmable device and operating the programmable device speeds up logic verification of the circuit to be verified as compared to using a CAD simulator. At this time, by extracting the signal state in the circuit to be verified written in the programmable device, a debug environment equivalent to the analysis by the CAD simulator can be obtained. However, if it is considered that the programmable device does not operate according to the logic design of the circuit to be verified, when the operation failure occurs, the circuit to be verified is written in the programmable device to determine whether the logic design of the circuit to be verified is defective. There is a problem that it is difficult to determine whether the problem is caused by this.
Japanese Patent Laid-Open No. 10-10196 JP 2000-215226 A

  As described above, in the conventional simulation analysis, there is a problem that comparison of the verification results by the programmable device and the CAD simulator is not easy, and it takes a long time to identify the cause of the malfunction. In addition, when it is considered that the programmable device does not operate according to the logic design of the circuit to be verified, when the operation failure occurs, the circuit to be verified is written in the programmable device to determine whether the logic design of the circuit to be verified is defective. There is a problem that it is difficult to determine whether the problem is caused by this.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a simulation analysis system, an accelerator device, and an emulator device that can reduce the time required to identify the cause of an operation failure. In particular, an object of the present invention is to provide a simulation analysis system in which comparison of verification results by a programmable device and a CAD simulator is easy.

  Even if it is considered that the programmable device does not operate according to the logic design of the circuit to be verified, when a malfunction occurs, the logic design of the circuit to be verified has a problem, It is an object of the present invention to provide a simulation analysis system in which it is easy to determine whether or not a failure has occurred by writing a verification circuit.

The simulation analysis system according to the present invention includes a programmable device in which a circuit to be verified is written and performs operation verification of the circuit to be verified by hardware, a simulation of the circuit to be verified on an information processing apparatus, and a circuit to be verified by software. and CAD simulator for performing operation verification of, if the hardware by the verification result and the verification result by the software are different from each other, based on the simulation data that caused the discrepancy verification result, the programmable device and the CAD simulator Parallel operation means that operates in parallel while synchronizing each operation cycle, and display means that displays output waveforms of the programmable device and the CAD simulator for each operation cycle.

  According to such a configuration, the programmable device and the CAD simulator are operated in parallel in synchronization with each operation cycle, and the respective output waveforms are displayed for each operation cycle. Therefore, the verification result by the programmable device and the CAD simulator can be easily obtained. The time required for identifying the cause of the malfunction can be shortened. In addition, since the verification result by the CAD simulator is displayed, even if it is considered that the programmable device does not operate according to the logic design of the circuit to be verified, the logic of the circuit to be verified is detected when an operation failure occurs. It is possible to easily determine whether there is a problem in the design or a problem caused by writing the circuit to be verified in the programmable device.

In particular, the CAD simulator has signal state holding means for temporarily holding the signal state in the memory element in the circuit to be verified with a holding period shorter than the simulation period from the start of input of the simulation data to the end of output of the verification result. The CAD simulator starts the simulation again when the verification result is different based on the signal state temporarily held, from the holding period closest to the verification result mismatched position, whereas the programmable device In addition, it is configured to operate independently up to the holding cycle closest to the mismatched portion. According to such a configuration, since the re-simulation by the CAD simulator is started from the holding cycle closest to the mismatched portion, the time required for the re-simulation is reduced, and the time required for specifying the cause of the malfunction is further reduced. Can do.

The accelerator apparatus according to the present invention includes a programmable device in which a circuit to be verified is written and performs operation verification of the circuit to be verified by hardware, and executes simulation of the circuit to be verified on the information processing apparatus. a parallel operating means for parallel operation while synchronizing the CAD simulator for performing operation verification for each operation cycle, and a display means for displaying the output waveform of the programmable device and CAD simulator for each operation period, is the parallel operation means When the verification result by the hardware and the verification result by the software are different from each other, the programmable device and the CAD simulator are operated in parallel on the basis of the simulation data that causes the verification result to be inconsistent. Memory The CAD simulator having signal state holding means for temporarily holding the signal state in the child with a holding cycle shorter than the simulation period from the start of the simulation data input to the end of the verification result output is based on the temporarily held signal state. In contrast, when the verification results are different, another simulation is started from the holding cycle closest to the mismatched location of the verification results, whereas the programmable device operates independently until the holding cycle closest to the mismatched location. Configured as follows.

In the emulator device according to the present invention, a circuit to be verified is written, a programmable device for verifying the operation of the circuit to be verified by hardware, and a simulation of the circuit to be verified is executed on the information processing apparatus. a parallel operating means for parallel operation while synchronizing the CAD simulator for performing operation verification for each operation cycle, and a display means for displaying the output waveform of the programmable device and CAD simulator for each operation period, is the parallel operation means When the verification result by the hardware and the verification result by the software are different from each other, the programmable device and the CAD simulator are operated in parallel on the basis of the simulation data that causes the verification result to be inconsistent. Memory elements Temporarily storing the signal state at shorter retention period than the simulation time to the output end of the verification result from the input start of the simulation data in
The CAD simulator having the signal state holding means to start the simulation again when the verification result is different based on the temporarily held signal state from the holding period closest to the verification result mismatched position. The programmable device is configured to operate independently until the holding period closest to the mismatched portion .

  According to the simulation analysis system, the accelerator device, and the emulator device according to the present invention, the verification results by the programmable device and the CAD simulator can be easily compared, so that the time required for specifying the cause of the malfunction can be shortened.

  In addition, since the verification result by the CAD simulator is displayed, even if it is considered that the programmable device does not operate according to the logic design of the circuit to be verified, it is programmable whether the logic design of the circuit to be verified is defective. It is possible to easily determine whether or not the problem is caused by writing the circuit to be verified in the device.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration example of a simulation analysis system according to Embodiment 1 of the present invention. A simulation analysis system 1 according to this embodiment includes a CAD simulator 2 that executes simulation of a circuit to be verified, a personal computer A1 that performs various types of information processing, a peripheral circuit 3 that performs input / output control between peripheral devices, and a programmable device. It consists of a board A2 on which an FPGA (Field Programmable Gate Array) 4 as a device is mounted, and is connected to each other via communication means such as USB.

  In this simulation analysis system 1, the operation of the circuit to be verified is verified by software, that is, the CAD simulator 2, and the operation of the circuit to be verified is verified by hardware, that is, the FPGA 4. If they are different, the CAD simulator 2 and the FPGA 4 are operated in parallel, and the output waveform by these is displayed on the personal computer A1.

  The personal computer A1 includes a CAD simulator 2, a circuit configuration storage unit 5, a main control unit 6, a parallel operation control unit 7, a display unit 8, a communication control unit 9, and a test data storage unit 10, and the CAD simulator 2 includes an internal It consists of a signal dump control unit 2a, a waveform viewer 2b, a signal state holding unit 2c, and a PLI (Programming Language Interface) control unit 2d. The FPGA 4 is a rewritable integrated circuit, and includes a circuit 4b to be verified written by a mapping tool or the like, and an internal signal dump circuit 4a for extracting a signal state in the circuit 4b to be verified.

  The communication control unit 9 is connected to the peripheral circuit 3 on the board A2 via a communication means such as a USB, and performs input / output data transmission / reception control. The test data storage unit 10 is a storage unit that stores input data used for operation verification by the CAD simulator 2 and the FPGA 4, and stores test bench data and control data as simulation data. The circuit configuration storage unit 5 is a storage unit that stores the circuit configuration of the circuit to be verified, and stores the same data as the data used to write the circuit to be verified 4 b in the FPGA 4. For example, data indicating the types of elements such as arithmetic elements and memory elements constituting the circuit to be verified, and connection relationships are stored.

  The internal signal dump control unit 2a performs extraction control of the signal state in the circuit to be verified in the simulation of the circuit to be verified on the circuit configuration storage unit 5 executed on the personal computer A1. This internal signal extraction control is performed based on an internal signal dump code embedded in the simulation data.

  The waveform viewer 2b is a processor for displaying an output waveform on the display unit 8, and the signal state such as the internal signal extracted by the internal signal dump control unit 2a is displayed for each operation cycle. The signal state holding unit 2 c is a storage unit that temporarily stores a result of a simulation executed on the personal computer A 1 using the circuit to be verified stored in the circuit configuration storage unit 5. Here, the signal state in the memory element in the circuit to be verified is temporarily held as a simulation result. In the signal state holding unit 2c, temporary holding is performed with a continuous holding period or an intermittent holding period within a predetermined simulation period. For example, in the simulation period, a period in which the signal state is temporarily retained and a period in which the signal state is not temporarily retained are alternately repeated. When the simulation is executed again by temporarily holding the internal signal in this manner, the CAD simulator 2 can execute the simulation again from the middle of the simulation period as necessary. The simulation period is a period from the start of input of simulation data including a series of input data to the end of output of verification results. The holding period is determined according to the circuit configuration of the circuit to be verified and simulation data.

  The PLI control unit 2d performs control to convert the format when the simulation data is transmitted to the FPGA 4 on the board A2 and when the output data from the FPGA 4 is received. This format conversion control is performed based on the PLI control code embedded in the simulation data. That is, the CAD simulator 2 performs operation verification of the circuit to be verified based on the simulation data, and the FPGA 4 performs operation verification of the circuit to be verified 4b based on the simulation data. The result of the operation verification by the FPGA 4 is output to the display unit 8 by the waveform viewer 2b, and the signal state of the internal signal extracted by the internal signal dump circuit 4a is displayed as an output waveform for each operation cycle.

  The parallel operation control unit 7 operates the CAD simulator 2 and the FPGA 4 alternately, and controls the CAD simulator 2 and the FPGA 4 to operate in parallel when the results of operation verification for each simulation data are different from each other. That is, when the verification result of the circuit to be verified 4b by the FPGA 4 does not match the verification result of the circuit to be verified by the CAD simulator 2 on the circuit configuration storage unit 5, the CAD simulator 2 and the FPGA 4 operate in synchronization with each operation cycle. Each output waveform is simultaneously displayed by the waveform viewer 2b.

  In this parallel operation, the simulation is performed again by the CAD simulator 2 based on the signal state temporarily held by the signal state holding unit 2c, and in particular, the closest to the mismatched portion of the verification result in the simulation period in which the operation mismatch occurs. The re-simulation starts from the holding period. That is, the CAD simulator 2 starts re-simulation from the middle of the simulation period, and the FPGA 4 starts parallel operation based on the re-simulation by the CAD simulator 2. Thereby, since the re-simulation by the CAD simulator 2 is started from the holding cycle closest to the mismatched portion, the time required for the re-simulation can be reduced and the time required for specifying the cause of the malfunction can be reduced.

  Further, the parallel operation control unit 7 starts displaying the signal states in the circuit to be verified 4b and the peripheral circuit 3 in the FPGA 4 immediately before the mismatched part in the simulation period. At this time, the CAD simulator 2 also starts displaying the signal state in the circuit to be verified. That is, in the parallel operation immediately before the mismatched portion, the corresponding internal signals between the CAD simulator 2 and the FPGA 4 are simultaneously displayed by the waveform viewer 2b.

  FIG. 2 is a diagram showing an example of a verification operation by the simulation analysis system of FIG. 1, and shows a state of transition of operation states in the CAD simulator 2 and the FPGA 4. The parallel operation control unit 7 repeatedly performs the operation verification of the circuit to be verified (CAD simulation phase) by the CAD simulator 2 and the operation verification (FPGA operation confirmation phase) of the circuit to be verified 4b by the FPGA 4 alternately for each simulation data. In the CAD simulation phase, signal states in all the memory elements in the circuit to be verified are temporarily held for each holding cycle B1 and B2. At this time, when the verification result by the FPGA 4 is different from the verification result by the CAD simulator 2, the inconsistency location analysis phase is entered.

  Here, it is assumed that an operation failure has occurred in step S2 of the FPGA operation confirmation phase for the circuit to be verified that the circuit operation is confirmed to be correct in step S1 of the CAD simulation phase, and the operation failure points in the simulation period are inconsistent. Let's say location 11.

  In the mismatch location analysis phase, the CAD simulator 2 and the FPGA 4 are operated in parallel to determine whether the cause of the malfunction is in the internal circuit of the FPGA 4 or in an external circuit such as the peripheral circuit 3. This parallel operation is performed based on the simulation data in which the malfunction occurs, and the second simulation by the CAD simulator 2 whose processing speed is slower than that of the FPGA 4 is started from the holding cycle B2 closest to the mismatched portion 11. Therefore, until the start of the parallel operation, only the FPGA 4 is checked again for operation based on the simulation data (step S3).

  After the start of the parallel operation, the CAD simulator 2 and the FPGA 4 are operated in synchronization with each operation cycle (step S4), and the display of the internal signal is started from C1 immediately before the mismatched portion 11 (step S5).

  FIG. 3 is a diagram showing an example of signal states displayed in the simulation analysis system of FIG. 1, and shows various internal signals a1, a2, b1, b2 and detection signals c1 to c3 displayed for each operation cycle. Has been. Based on the clock signal (CLK) 12 for each operation cycle, internal signals a1 and a2 in the circuit to be verified in the CAD simulation, and internal signals of the circuit 4b to be verified in the FPGA 4 corresponding to the internal signals a1 and a2 respectively. b1 and b2 are displayed as output waveforms.

  Here, it is assumed that the CAD simulator 2 compares corresponding internal signals. For example, processing results such as exclusive OR (exclusive OR) are displayed as detection signals c1 and c2 for each operation cycle. That is, the detection signal c1 is generated based on the comparison result between the internal signals a1 and b1, and the detection signal c2 is generated based on the comparison result between the internal signals a2 and b2. Such display of the detection signals c1 and c2 is performed based on the detection code embedded in the simulation data.

  The logical sum of the detection signals c1 and c2 is displayed as the detection signal c3. By displaying such detection signals c1 to c3, it is possible to easily identify the mismatched portion 11, and thus it is possible to reduce the time required to identify the cause of the malfunction.

  Steps S101 to S105 in FIG. 4 are flowcharts showing an example of the verification operation in the simulation analysis system in FIG. First, the parallel operation control unit 7 causes the CAD simulator 2 to execute a simulation of the circuit to be verified, and after verifying the circuit operation, confirms the operation of the circuit 4b to be verified by the FPGA 4 (steps S101 and S102).

  The operation check for the CAD simulation is repeatedly performed for each simulation data, and when an operation failure occurs, a parallel operation by the CAD simulator 2 and the FPGA 4 is started (steps S103 and S104).

  After the start of the parallel operation, the signal state of the internal signal is displayed immediately before the occurrence of the malfunction (step S105).

  According to the present embodiment, the FPGA 4 and the CAD simulator 2 are operated in parallel in synchronization with each operation cycle, and the respective output waveforms are displayed on the display unit 8, so that the verification result by the FPGA 4 and the CAD simulator 2 can be easily obtained. Thus, the time required to identify the cause of the malfunction can be shortened.

Embodiment 2. FIG.
In the first embodiment, the example in which the operation verification by the CAD simulator 2 and the operation verification by the FPGA 4 are alternately performed for each simulation data has been described. On the other hand, in the present embodiment, a case will be described in which operation verification by the CAD simulator 2 and operation verification by the FPGA 4 are simultaneously performed on each simulation data from the beginning.

  FIG. 5 is a diagram showing an example of the verification operation in the simulation analysis system according to the second embodiment of the present invention, and shows the state of operation state transition in the CAD simulator 2 and the FPGA 4. The parallel operation control unit 7 simultaneously starts operation verification of the circuit to be verified by the CAD simulator 2 and operation verification of the circuit 4b to be verified by the FPGA 4 based on each simulation data.

  In the operation verification by the CAD simulator 2, the signal states in all the memory elements in the circuit to be verified are temporarily held for each holding cycle B11 and B12. When the verification result by the FPGA 4 is actually different from the verification result by the CAD simulator 2 (step S11), a mismatched part analysis phase is entered.

  In the mismatch location analysis phase, the CAD simulator 2 and the FPGA 4 are operated in parallel. This parallel operation is performed based on each simulation data, and the second simulation by the CAD simulator 2 is started from the holding cycle B12 closest to the mismatched portion 21. Therefore, until the parallel operation is started, only the FPGA 4 is checked again based on the simulation data (step S12).

  After the start of the parallel operation, the CAD simulator 2 and the FPGA 4 are operated in synchronization with each operation cycle (step S13), and the display of the internal signal is started from C11 immediately before the mismatched portion 21 (step S14).

  According to this embodiment, since the operation verification by the CAD simulator 2 and the operation verification by the FPGA 4 are simultaneously performed on each simulation data from the beginning, it is possible to confirm the presence or absence of an operation failure for each simulation data at an early stage.

Embodiment 3 FIG.
In the first and second embodiments, when the electric circuit logically verified by the CAD simulator 2 is written in the FPGA 4 and the mismatch is analyzed by the operation check for checking whether or not the electric circuit actually operates correctly. An example was described. On the other hand, in the present embodiment, the circuit to be verified is written in the FPGA 4 and the FPGA 4 is operated, so that the accelerator apparatus that speeds up the logic verification of the circuit to be verified is used compared to the case where the CAD simulator 2 is used. A case where the invention is applied will be described.

  The accelerator device according to the present embodiment includes an FPGA 4 in which a circuit to be verified is written, a parallel operation control unit 7 that operates the FPGA 4 and the CAD simulator 2 in parallel, and a display unit 8. By writing the circuit to be verified in the FPGA 4 and operating the FPGA 4, the logic verification of the circuit to be verified is accelerated compared to using the CAD simulator 2. At this time, it is possible to obtain a debugging environment equivalent to the analysis by the CAD simulator 2 by extracting the signal state in the circuit to be verified written in the FPGA 4.

  At this time, since the verification result by the CAD simulator 2 is also displayed at the same time, even if it is considered that the FPGA 4 does not operate according to the logic design of the circuit to be verified, when the operation failure occurs, the circuit to be verified Therefore, it is possible to easily determine whether there is a problem in the logic design, or a problem caused by writing the circuit to be verified in the FPGA 4.

  In this embodiment, an example in which the present invention is applied to an accelerator device has been described. However, the present invention is not limited to this, and the logic verification of an electric circuit can be speeded up or combined with software. It may be applied to an emulator device for performing the operation verification early and at high speed.

It is the block diagram which showed the example of 1 structure of the simulation analysis system by Embodiment 1 of this invention. It is the figure which showed an example of the verification operation | movement by the simulation analysis system of FIG. It is the figure which showed an example of the signal state displayed in the simulation analysis system of FIG. It is the flowchart which showed an example of the verification operation | movement in the simulation analysis system of FIG. It is the figure which showed an example of the verification operation | movement in the simulation analysis system by Embodiment 2 of this invention.

Explanation of symbols

1 simulation analysis system, 2 CAD simulator,
2a Internal signal dump control unit, 2b waveform viewer, 2c signal state holding unit,
2d PLI control unit, 3 peripheral circuit, 4 FPGA, 4a internal signal dump circuit,
4b Circuit to be verified, 5 Circuit configuration storage unit, 6 Main control unit, 7 Parallel operation control unit,
8 display unit, 9 communication control unit, 10 test data storage unit,
A1 personal computer, A2 board

Claims (5)

A programmable device in which a circuit to be verified is written and performs operation verification of the circuit to be verified by hardware,
A CAD simulator that performs simulation of the circuit to be verified on the information processing apparatus and performs operation verification of the circuit to be verified by software;
If the hardware by the verification result and the verification result by the software are different from each other, the verification result on the basis of the simulation produced a mismatch data, parallel operation while synchronizing each operation cycle the programmable device and the CAD simulator Parallel operation means to
Display means for displaying the output waveform of the programmable device and the CAD simulator for each operation cycle;
The CAD simulator has signal state holding means for temporarily holding the signal state in the storage element in the circuit to be verified with a holding period shorter than the simulation period from the start of input of the simulation data to the end of output of the verification result,
While the CAD simulator starts the simulation again when the verification results are different based on the signal state temporarily held, from the holding cycle closest to the mismatched location of the verification results, the programmable device A simulation analysis system characterized by operating independently up to the holding period closest to the mismatched portion . The programmable device starts parallel operation based on the simulation again by the CAD simulator,
The simulation analysis system according to claim 1 , wherein the display unit starts displaying a signal state in the programmable device from a holding period closest to the mismatched portion . The programmable device is provided on a board equipped with a peripheral circuit that performs input / output control with a peripheral device,
The simulation analysis system according to claim 1, wherein the display unit displays a signal state in the peripheral circuit. A programmable device in which a circuit to be verified is written and which performs operation verification of the circuit to be verified by hardware; a CAD simulator which performs simulation of the circuit to be verified on an information processing apparatus and performs operation verification of the circuit to be verified by software; Parallel operation means that operates in parallel while synchronizing each operation cycle ;
Display means for displaying the output waveform of the programmable device and CAD simulator for each operation cycle;
If the verification result by the hardware and the verification result by the software are different from each other, the parallel operation means causes the programmable device and the CAD simulator to operate in parallel based on the simulation data that caused the verification result to be inconsistent. ,
The CAD simulator having signal state holding means for temporarily holding a signal state in a storage element in a circuit to be verified with a holding period shorter than a simulation period from the start of input of the simulation data to the end of output of the verification result is temporarily held. On the other hand, based on the signal state, the simulation is started again when the verification result is different from the holding period closest to the mismatched location of the verification result, whereas the programmable device has the holding cycle closest to the mismatched location. Until then , an accelerator device that operates independently . A programmable device in which a circuit to be verified is written and which performs operation verification of the circuit to be verified by hardware; a CAD simulator which performs simulation of the circuit to be verified on an information processing apparatus and performs operation verification of the circuit to be verified by software; Parallel operation means that operates in parallel while synchronizing each operation cycle ;
Display means for displaying the output waveform of the programmable device and CAD simulator for each operation cycle;
If the verification result by the hardware and the verification result by the software are different from each other, the parallel operation means causes the programmable device and the CAD simulator to operate in parallel based on the simulation data that caused the verification result to be inconsistent. ,
The CAD simulator having signal state holding means for temporarily holding a signal state in a storage element in a circuit to be verified with a holding period shorter than a simulation period from the start of input of the simulation data to the end of output of the verification result is temporarily held. On the other hand, based on the signal state, the simulation is started again when the verification result is different from the holding period closest to the mismatched location of the verification result, whereas the programmable device has the holding cycle closest to the mismatched location. Emulator device characterized by operating alone until .

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