JPH09127210A - Semiconductor testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor testing apparatus by which a test input signal to be applied to a device under test is displayed and analyzed in a shape which is close to a more actual input signal. SOLUTION: When the waveform of a test pattern signal to be input to a device under test(DUT) 4 is displayed and analyzed, data on the test pattern signal is converted into an analog signal. In a state that the analog signal is supplied to the DUT 4, the test pattern signal is turned down inside a tester from a place 3 which is close to the DUT 4 as far as possible, and analytical data is read out. Thereby, the waveform can be displayed and analyzed in a shape which is close to a more actual application signal to the DUT 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test device for performing various tests on a semiconductor device, and more particularly to a semiconductor test device for facilitating debugging of a signal waveform applied to the semiconductor device.

[0002]

2. Description of the Related Art An example of the configuration of a conventional semiconductor test device is shown in FIG.
This will be described with reference to FIG. As shown in the figure, the semiconductor test device is roughly divided into an input / output device (not shown) including a tester computer 1, a tester main body 2, a test head 3, and a CRT display device. The tester computer 1 has a memory 1
1, a CPU 12 and a CPU bus 13 are included. The memory 11 has a device under test (hereinafter, DU) to be tested.
A test program that creates input data from the test equipment to determine whether T is a good product or a defective product, reads the output from the DUT, and determines whether the output matches the expected value (or signal pattern). Is held. The memory 11 also holds a waveform analysis program for analyzing the captured signal waveform. The tester computer 1 executes a test program or the like, generates a test signal to be supplied to the DUT 4, analyzes a signal output from the DUT 4, and controls the test apparatus as a whole.

The tester main body 2 includes a tester bus 21, an address controller 22, a data memory 23, a master clock generator 24, a frequency divider 25, a D / A converter 26, and a filter 2.
It is composed of 7 etc. The data memory 23 is a DUT
In the mode in which the test signal is supplied to 4, the digital data for forming the test signal waveform is received from the tester computer 1 via the CPU bus 13 and the tester bus 21 and stored. The address control unit 22
The data memory 23 is accessed in response to the address signal supplied from the tester computer 1. The data read from the data memory 23 is converted into an analog signal by the D / A converter 26 and becomes a test input signal via the low pass filter 27. The test input signal is input to the DUT 4 via a test head including a switch for turning on / off the signal relay and a signal selector. Address controller 22, data memory 23, D / A converter 26
The master clock generator 24, the frequency divider 25, etc.
The operation is synchronized by the clock signal output from the.

In such a configuration, when the tester computer 1 executes the test program and instructs the address control section 22 to read the test input signal waveform, the data memory 23 continuously outputs the waveform data. This data is converted into a level signal by the D / A converter 26, an unnecessary component is removed through the filter 27, and the level signal is supplied to the DUT 4 as a test input signal.

The semiconductor test apparatus takes in the output signal output from the DUT 4 and determines whether or not the pattern of the output signal matches the pattern of the expected value signal. Since this operation is not particularly related to the present application, a related circuit is not shown.

[0006]

By the way, the debug for determining whether or not the waveform of the test input signal applied to the DUT 4 is as designed is performed by using the data of the input signal pattern held in the data memory 23 as a test program. Read into the memory 11 of the tester computer 1 by
The tester computer 1 executes the waveform display analysis program to display the waveform pattern on the CRT, and performs arithmetic processing to analyze whether there is an error.

When this input waveform is displayed / analyzed, first, in the test program, the data in the memory 23 in which the waveform data to be displayed / analyzed is stored is stored in the variable area of the memory 11 secured by the test program. To store. The data in this variable is sent to the waveform display analysis means (program) for display and analysis.

However, at this time, since the data to be displayed is the data in the data memory 23, D /
It is not the data actually supplied to the DUT 4 after passing through the A converter 26 and the filter 27. Therefore, the D / A converter 2
6 It is necessary to analyze and observe the characteristics of 6 and the filter.

Further, when reading the data to be debugged by the waveform display analysis device, while the data memory 23 is in operation,
Since the data cannot be read, the application to DUT 4 must be stopped. The test must be suspended, debugging cannot be done while the test is running, and debugging cannot be done easily.

Therefore, an object of the present invention is to provide a semiconductor test apparatus capable of displaying and analyzing a test input signal applied to a device under test in a form closer to an actual input signal. To do.

Another object of the present invention is to provide a semiconductor test apparatus capable of displaying / analyzing a test input signal in a state where a signal is actually applied to a device under test.

[0012]

In order to achieve the above object, the semiconductor test apparatus of the present invention is tested for whether or not an expected output pattern signal is generated with respect to a supplied input pattern signal. A semiconductor device, a first memory that stores a data signal corresponding to a test pattern in advance, and outputs the data signal in response to a read command signal that is supplied, and a data signal that is output from the first memory are analog signals. Signal conversion means for converting the test input pattern signal to the semiconductor device under test and supplying the test pattern signal to the semiconductor device under test to obtain an input pattern inspection data signal Second means for receiving and storing the input pattern inspection data signal in response to a write command signal supplied thereto. Comprising a memory, a signal delay means for adjusting the supply interval between the read command signal and the write command signal.

Further, the semiconductor test apparatus of the present invention converts the semiconductor device under test whose operation is to be tested and the data of the test pattern stored in the memory into an analog signal, and outputs the test pattern signal to the semiconductor device under test. A plurality of test pattern signal generating means, and a signal selecting means for selecting any one of the plurality of test pattern signals supplied from the plurality of test pattern signal generating means to the semiconductor device under test. And sampling means for digitizing and storing the selected test pattern signal, and adjusting means for adjusting the operation timing between the test pattern signal generating means and the sampling means.

[0014]

The semiconductor test apparatus of the present invention converts the data of the test pattern into an analog signal when performing the display analysis of the test pattern signal waveform input to the DUT, and converts the data into an analog signal.
In the state of being supplied to the UT, by returning the test pattern signal from a position as close as possible to the DUT and reading (sampling) it is possible to perform display and analysis in a form closer to the actual applied signal to the DUT. There is.

By separating the memory for storing the data to be subjected to the display analysis from the memory for storing the data applied to the DUT, the waveform display analysis can be performed without stopping the test data to the DUT. it can.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and the description of those parts will be omitted.

In FIG. 1, the tester computer 1 is
The CPU 12 is directly connected to the CPU bus 13. Since the CPU 12 is directly connected to the CPU bus 13, it can independently fetch data from the data memory 202.

The tester main body 2 includes a plurality of test pattern signal generating means including a frequency divider, an address controller, a data memory, a D / A converter, and a filter. For example, the first test pattern signal generating means is the frequency divider 25.
a, address control unit 22a, data memory 23a, D /
It is composed of an A converter 26a and a filter 27a. The second test pattern signal generating means is a frequency divider 25b, an address controller 22b, a data memory 23b, a D / A converter 26.
b and a filter 27b. The address controller uses the read address signal as a read command signal in the data memory 23.
Give to. In FIG. 1, the test pattern signal generating means is 2
However, the same can be applied to the case where n test pattern signal generating means are provided to obtain n pattern signals.

The plurality of test pattern signals output by the plurality of test pattern signal generating means are applied to the input terminal of the DUT 4 via the test head 3. In this test head 3, a signal selection switch (switching relay)
31a and 31b are added, and any one of the signals supplied to the DUT 4 can be selected. The selected test pattern signal is taken in by the sampling means including the A / D converter 201 and the data memory 202.

The sampling means receives a write address signal as a write command signal from an address control section which drives a test pattern signal generating means for outputting a test pattern signal to be sampled, and performs a data sampling operation. Therefore, the signal switching device (switching relay) 20
3 makes it possible to select the address control unit. Also, a delay circuit 204 is provided as an operation timing adjusting means in consideration of the delay of the test pattern signal from the data memories 23a and 23b to the data memory 202. Address control units 25a, 25b,
Data memories 23a, 23b, D / A converters 26a, 2
6b, A / D converter 201, data memory 202, etc.
It operates in synchronization with the master clock.
Address control units 22a and 22b, signal selection switch 31
The operations of a, 31b, the signal switch 203, etc. are controlled by the tester computer 1.

Next, the debugging of the input waveform performed by the semiconductor test device will be described.

The tester computer 1 uses the signal selection switches 31a and 31b in the test head to select the input data as the data for display analysis. The selected data is digitized by the A / D converter 201. The data is loaded into the data memory 202.
At this time, the address control of the data memory 202 is performed via the signal switch 203. The switching control of the signal switch 203 is performed by the address control 22a or 22b which controls the memory of the pattern generating means for generating the pattern signal selected by the signal selection switch 31a or 31b.
Is done to select. Data memory 22a or 2
Since the data of 3b is stored in the data memory 202 after the test head 3 is folded back, it is necessary to adjust the addresses of the data memories 23a and 23b and the data memory 202 in time (setting of delay time). This delay time becomes constant when the memory, the D / A converter, the A / D converter, etc. perform system-synchronized operations, so that the delay circuit 204 outputs the delay time from the data memory 23a or 23b. The pattern formed by the data group is taken into the data memory 202 as a whole.

The display analysis of the waveform data is performed by the tester computer 1 executing the waveform display analysis program and the data of the test pattern stored in the data memory 202 being stored in the CPU 12 of the tester computer 1.

[0025]

As described above, in the semiconductor test apparatus of the present invention, the test pattern applied to the DUT is folded back from immediately before the DUT and read.
It becomes possible to debug the input signal pattern in a form closer to the actual applied data to the UT.

Since the memory for storing the data for display analysis is not the memory for generating the test pattern, the input waveform can be debugged in real time without stopping the input of the test pattern. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor test device for debugging an input / output signal waveform according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a conventional semiconductor test device for debugging an output signal waveform.

[Explanation of symbols]

 4 device under test 22, 22a, 22b address controller 23, 23a, 23b data memory 24 master clock generator 25, 25a, 25b frequency divider 26, 26a, 26b D / A converter 27, 27a, 27b, filter 31a , 31b Signal selection switch 201 A / D converter 202 Data memory 203 Signal switch 204 Delay circuit

Claims (2)

[Claims] 1. A semiconductor device under test, which is tested to generate an expected output pattern signal with respect to a supplied input pattern signal, and a data signal corresponding to a test pattern are stored in advance and supplied. Output in response to a read command signal
Memory, signal conversion means for converting the data signal output from the first memory into a test input pattern signal of an analog signal and supplying the test input pattern signal to the semiconductor device under test, and a test supplied to the semiconductor device under test. An input signal pattern sampling means for sampling the input pattern signal to obtain an input pattern inspection data signal; a second memory for capturing and storing the input pattern inspection data signal in response to a supplied write command signal; A semiconductor test device comprising: a signal delay unit that adjusts a supply interval between the read command signal and the write command signal. 2. A semiconductor device under test whose operation is to be tested, and a plurality of test pattern signals for converting test pattern data stored in a memory into analog signals and supplying a test pattern signal to the semiconductor device under test. Generating means, signal selecting means for selecting one of the test pattern signals from the plurality of test pattern signals supplied to the semiconductor device under test from the plurality of test pattern signal generating means, and the selected test pattern signal A semiconductor test device comprising: sampling means for digitizing and storing the data; and adjusting means for adjusting the operation timing between the test pattern signal generating means and the sampling means.