JPS63286782A - Semiconductor testing system - Google Patents

Abstract

PURPOSE:To observe in a real time an input/output wave form of a device to be measured, by selecting an input/output signal of a prescribed terminal of the device to be measured by a signal selecting circuit in accordance with a signal from an input device, and bringing it to an image processing. CONSTITUTION:Address information outputted from a pattern generating part 6 of a tester body 1 is brought to a timing adjustment by an address formatter 13 of a test head 2, and thereafter, passes through a pin electronics circuit group 14 and outputted to each address pin of a semiconductor memory 10. On the other hand, a data outputted from the generating part 6 is brought to a timing adjustment by a data formatter 15, and thereafter, passes through a pin electronics circuit group 16 and outputted to each data pin of the semiconductor memory 10. To the circuit groups 14, 16, multiplexers 18, 17 are connected, respectively, a contact to be connected is selected by a selection control signal from a control part 3, and an output of an input/output signal generated in accordance with the contents of a test is inputted to an image processor 20 and brought to an image processing, and thereafter, displayed on a display 5, as an input/output signal waveform in a designated terminal of the semiconductor memory 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor test system for testing semiconductor devices such as ICs, and more specifically, when testing a new semiconductor etc., it is possible to examine measurement conditions, etc. The present invention relates to a semiconductor test system that facilitates proper setting of test conditions and examination when measuring new functions.

[Prior Art] A general test method for conductor memory (hereinafter referred to as memory) is to first store predetermined data in the memory, then output the data stored in the memory, and compare it with the expected value. That is what it is. The memory data, expected value data, address information, etc. for such tests are
It is generally generated by a microprogram-controlled pattern generator.

In addition, in various ICs such as logic ICs and video RAM 1 linear ICs, a corresponding pattern signal is manually input to the device under test as data, an output signal is obtained from the device under test, and an expected value and an output signal are obtained from the device under test. are compared and tested.

[Problems to be Solved] By the way, when testing a new IC, it is necessary to newly program test conditions and set a predetermined test pattern or waveform. Furthermore, it is also necessary to determine and modify the expected value in accordance with the resulting output waveform from the device under test. Furthermore, there are bugs in the supply of output signals and their waveforms, which must be depacked.

In such cases, conventionally, an oscilloscope is connected to a terminal of the device under test for observation, and depacking, etc., and setting and changing of measurement conditions are performed in one step.

However, as the number of terminals of devices under test increases, it takes time to connect the oscilloscope to each necessary terminal, and it also takes time and effort to install them. Moreover, there is a risk that the oscilloscope coupling will adversely affect the measurements on the tester side.

The present invention solves the problems of the prior art, and aims to provide an ``I''-conductor test system that can observe the input waveform and output waveform of a device under test in real time. shall be.

[Means for Solving the Problems] In order to achieve this object, the present invention provides an input device, a display device, a tester, a signal selection circuit, and a signal selection circuit from the pin electronics circuit of the tester. It is equipped with an image processing device that receives an input signal to or an output signal from the device under test, and selects an input signal or output signal 3 of a predetermined terminal of the device under test by a signal selection circuit in response to a signal from the human-powered device. The image is then input to an image processing device, processed, and displayed on a display device.

[Operation] In this way, the signal output from the pin electronics circuit to the device under test or the output signal of the device under test that the pin electronics circuit receives is obtained via the signal selection circuit, and its waveform is image-processed and observed. By this,
It is possible to grasp the current test conditions, etc. without having to connect the oscilloscope to the end T of the device under test, etc., and reducing the risk of adversely affecting measurements on the tester side.

As a result, when testing a new IC, it is possible to efficiently program test conditions and set predetermined test patterns and waveforms, and create or change expected values. You can easily carry out depacking, etc.

Furthermore, it is possible to check whether the tester is constantly operating or not because the waveform of the input signal or output signal can be observed.

[Example 1] An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an IC tester according to an embodiment to which the semiconductor test system of the present invention is applied.

In the figure, 1 is a main body of a tester, which tests a semiconductor memory 10 as a device under test. A test head 2 is inserted between the tester main body 1 and the semiconductor memory 10 and receives a test pattern, an expected value of the measured voltage signal 9, etc. from the tester main body 1.

The tester body 1 includes a control unit 3, a keyboard 4, a display 5, and address information and data (written data or expected value data) for testing a semiconductor memory 10.
, and a pattern generating section 6 that generates other control signals. Note that parts related to control signals from the tester main body 1 are omitted in the figure.

Here, the address information output from the pattern generator 6 to the address information line it is adjusted in timing by the address formatter 13 of the test head 2, and then
The signal is input to the pin electronics circuit group 14 related to address pins of the semiconductor memory 10, and output to each address pin of the semiconductor memory 10.

- On the other hand, the data output from the pattern generator 6 to the data line 12 is adjusted in timing by the data formatter 15, and then manually inputted to the pin electronics circuit group 16 related to the data pins of the semiconductor memory 10.
It is output to each data pin of the conductive memory 10. In addition,
One pin electronics circuit (or one board) is typically provided for each pin or pins of the device under test.

Now, when writing data to the semiconductor memory U 10, write data (for example, 8-bit data) is outputted from the pattern generation section 6 to the data line 12, and the data formatter 15. This write data is written to the address specified by the address information 11 via the pin electronics circuit group 16.

Here, the pin electronics circuit group 14 and the pin electronics circuit group 16 include a multiplexer 17.1.
8 are connected to each other (or connected to each correspondingly to each of the plurality of terminal connection pins of each pin electronics circuit), and each pin electronics circuit has one output (or each of its plurality of outputs). The output signals of are connected to respective selection contacts of multiplexer 17.18.

The multiplexers 17 and 18 select the contacts to be connected by a selection control signal for selecting a specified contact from the control unit 3 of the tester main body 1, and the output of the input signal or output signal generated according to the test content is A signal inputted to the processing device 20 and digitized by the A/D conversion circuit 21 is manually inputted to the 111q image memory control circuit 22. As a result, data regarding the waveform of the input signal or the waveform of the output signal to the semiconductor memory 10 is stored in the image memory 23.

The data in the image memory 23 is then read out by the arithmetic processing unit 24 via the image memory control circuit 22 and sent to the control section 3 of the tester main body 1.

Under the control of the control section 3, the signal is displayed on the display 5 of the tester main body 1 as an input signal waveform or an output signal waveform at a designated terminal of the semiconductor memory 10.

Next, to explain the operation, inputting a predetermined function key indicating waveform observation from the keyboard 4, the type of observed waveform (whether it is an output waveform or an input waveform when observing the device under test), its terminal position, etc. Upon receiving the information, when the type indicates the output waveform of the device under test based on the input information from the keyboard 4, the control unit 3 enables the multiplexer 17 and connects it to the terminal of the designated number. A selection signal is sent to multiplexer 17 to start the test.

On the other hand, when the type indicates that the input waveform is for the device under test, the multiplexer 17 or 18
, and sends a selection signal to multiplexer 17 or 18 to connect to the terminal of the designated number, and start the test.

As a result, the input waveform or output waveform of the designated terminal is processed by the image processing device 20 and displayed on the display 5 of the tester main body 1.

In addition, when displaying both the input waveform and the output waveform, the A/D conversion circuit 21 and the image memory 23 of the image processing device 20 are provided respectively for the input waveform and the output waveform, and each of the two image memories 23 and 23 is provided for the input waveform and the output waveform. By storing them separately, it is possible to observe them simultaneously. Furthermore, since the generation timings of the human input signal and the output signal are different, the image memory 23 and the A/D conversion circuit 21 process them in a time-sharing manner as one unit to display them on the control unit 3 or the display 5. They may be displayed simultaneously.

As described above, when obtaining a human input signal or an output signal from a device under test from a pin electronics circuit, it may be connected directly to a pin that is in contact with each terminal of the device under test. Furthermore, although the selection of the terminal is performed by a multiplexer, it may be connected to enable selection via a switch contact such as a relay.

In the embodiment, the keyboard and display are built into the tester body, but these may be installed in parallel with the image processing device or independently from the tester and the image processing device. It may or may not include a display.

Further, the keyboard may be a general input device, and the display may be a general display device.

In the embodiments, the test of semiconductor memory is mainly described, but it goes without saying that the present invention can be applied to testers for other conductor devices in general.

[Effects of the Invention] As can be understood from the following explanation, in this invention, the signal that is output from the pin electronics circuit to the device under test, or the output signal of the device under test that is received by the pin electronics circuit is selected. Obtained through kaiseki,
By image-processing and observing the waveform, you can reduce the risk of having to connect the oscilloscope to the terminals of the device under test (and reduce the risk of adversely affecting measurements on the tester side). You can understand the conditions, etc.

As a result, when testing a new IC, it is possible to efficiently program test conditions and set predetermined test patterns and waveforms, and create or change expected values. In addition to doing this, you can also easily use Depak etc.

Note that it is also possible to check whether the tester is operating normally because the waveform of the input signal or output signal can be observed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an IC tester according to an embodiment to which the semiconductor test system of the present invention is applied. 1... Tester body, 2... Test head, 3...
- Control unit, 4... Keyboard, 5... Display, 6... Pattern generation unit, 10... Semiconductor memory,
11...address information line, 12...data signal line,
13... Address formatter, 14.16... Pin electronics circuit group, 15... Data formatter, 17.18... Multiplexer, 20... Image processing device, 21... A/D conversion circuit,
22... Image memory control circuit, 23... Image memory, 24... Arithmetic processing unit.

Claims (1)

[Claims] (1) an input device, a display device, a tester, a signal selection circuit, and the image processing device that receives an input signal to the device under test or its output signal from the pin electronics circuit of the tester via the signal selection circuit; The input signal or the output signal of a predetermined terminal of the device under test is selected by the signal selection circuit according to a signal from the input device, and is input to the image processing device, and image-processed. A semiconductor test system characterized by displaying information on a display device.