JPH0434110B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Field of Application) The present invention relates to an in-circuit digital tester, and more particularly to a circuit for generating test signals for testing bus-oriented electronic components such as microprocessors. As used in this text, an in-circuit digital tester is a tester that can test a circuit whether or not the electrical connection to which the test signal is supplied is connected to the output of another logic element. Say something. In-circuit testers generate and apply a digital test signal to the output of a logic element, which is normally at a logic ground state, and brings the output to a logic high potential state without damaging the logic element. In other words, "in-circuit" means that the device or circuit under test does not have to be isolated or removed from surrounding circuitry in order to provide test signals and monitor its output. (Prior Art and Problems to be Solved by the Invention) U.S. Patent No. 4,216,539 (assigned to the assignee of this application and incorporated herein by reference).
As shown in Figure 2, a conventional in-circuit digital tester is equipped with a digital test signal generator having each pin on a nail bed fixing plate capable of generating various digital test signals for testing components in a circuit under test. ing. However, some components require particularly complex test signal patterns to adequately test their electrical performance.
One such component is a microprocessor chip. Such components are typically bus-based devices and require the generation of multi-wire data bus signals representing data or addresses. Furthermore, in order to properly implement or set the generation sequence of data bus signals, a series of control signals must occur simultaneously with the data bus signals before the microprocessor can successfully perform its internal sequence. . Because a microprocessor executes all of its instructions using repeated selection sequences such as instruction fet cycles, memory read cycles, memory write cycles, etc., it generates the complex test signal patterns required, and In order to generate a long pattern of data, the number of pin memories required to store the test signals used to generate the data used during the test cycle to generate the required test pattern should be minimized. Means must be provided. (Means for Solving the Problem) In order to solve the problem of generating this complex test signal pattern with advantages and novelty superior to the conventional ones, the present invention provides a bus system (bus-oriented ) The device test signal was divided into two: a data bus test signal and a protocol test signal or control test (hereinafter simply referred to as a protocol test signal). Data bus test signals were applied in parallel words to a data bus containing multiple lines to serve as data or addresses. Each of the plurality of protocol test signals is timed such that, when all protocol test signals are viewed in parallel, the device determines the protocol sequence that conveys the information necessary for the device to perform its normal intended function. Occurs in a relationship. Full functionality of the device is achieved based on this predetermined protocol sequence by iteratively generating the protocol sequences required to test each functionality of the device. The present invention discloses a circuit used in an in-circuit digital test device that generates data bus test signals and control (protocol) test signals to test bus-related electronic components of a circuit under test. This circuit is comprised of a data memory for storing data bus test signal generation data for a plurality of data bus lines. This data bus test signal generation data is output from this data memory in accordance with predetermined consecutive data memory addresses. A protocol memory is provided for storing protocol test signal generation data for a plurality of protocol sequences each defined by a plurality of protocol test signals. The protocol test signal is generated according to a predetermined sequence of protocol memory addresses, with each protocol sequence stored in the protocol memory beginning at a starting address and ending at a final memory address. A sequence controller is provided to generate this predetermined sequence from the addresses supplied to the data memory and protocol memory. The controller generates a predetermined series of start addresses for the protocol memory and selects from among the protocol sequences to generate a protocol sequence. Additionally, the controller can generate data bus test signals specified by data bus test signal generation data stored in the data memory. The controller is constituted by a programmed processor having a random access memory for storing instructions which, when executed by the processor, output the starting address of a predetermined sequence of protocol sequences to be generated. The controller also has a buffer memory device connected to the output of the processor for temporarily storing and outputting the starting address of the protocol sequence in the same sequence as output by the processor. A buffer memory device generates a run command signal to a programmed processor when any memory location is free. The controller further includes a protocol memory address counter, a sequence length memory, a data memory address counter and synchronization means. The protocol memory address counter generates a protocol memory address in response to the output from the buffer memory device, and the sequence length memory outputs an enable signal to generate a predetermined sequence of protocol and data memory addresses in response to the control memory address. The enable signals include a final address signal that may load the protocol memory address counter with the next protocol sequence start address from the buffer memory device, a data memory enable signal that may selectively generate a data bus test signal to the data memory, and a data memory enable signal that may selectively generate a data bus test signal to the data memory. and a data memory address increment signal that can increment a memory address counter to the next data memory address in a predetermined sequence of data memory addresses. A data memory address counter generates a data memory address in response to the sequence length memory enable signal described above. The main function of the synchronization means is to update the control memory address counter with the starting address of the next protocol sequence to be generated in response to the final address signal. The present invention can be applied to an in-circuit digital test device that can be used with a central processing unit, and includes a response signal line for monitoring a digital response test signal from a circuit under test, and further includes a functional tester; It includes a set of test pins for contacting terminals of the circuit under test, a plurality of test signal generators, and response signal selection means. This functional tester performs a functional test of the signals appearing on the response signal line during the test cycle. The results of this test are analyzed by a central processing unit to determine the electrical performance of the components of the circuit under test. Further, the test pin group is used to selectively contact the terminals of the circuit under test and extract the input/output signal points thereof. A test signal generator is provided for each of the test pin groups. Each test signal generator (a) outputs data bus test signal generation data for generating data bus test signals for a plurality of data bus lines in accordance with predetermined consecutive data memory addresses; A plurality of data memories are provided corresponding to each of the above test pins to store bus test signal generation data, and (b) a plurality of protocol test signals are generated in accordance with predetermined consecutive protocol memory addresses. each of the protocol sequences for storing protocol test signal generation data starting at a starting address and ending at a final address for generating a plurality of protocol test signals for such plurality of protocol sequences. (c) A plurality of protocol memories provided corresponding to each test pin; and driver means for causing generation of the protocol test signal. The response test selection means selectively supplies a signal from any one of the test pins to the response signal line as a response signal of the functional tester. The present invention is an improved digital test signal generator with programmed memory. (Embodiment) In-Circuit Digital Tester First, the operation of an in-circuit digital test device 1 to which the present invention is applied will be explained with reference to FIG. The test apparatus 1 of FIG. 1 generates a test cycle during which a predetermined digital test generated by a plurality of driver/receiver plates 20, 22 is applied to the electrical connection points of a circuit or device under test (DUT) 26. A signal is given. The digital test signals generated by the driver/receiver plates 20, 22 are provided to selected connection points of the DUT 26 via the nail bed 24 in which the DUT 26 is located, and their generation is programmable with the test head controller 14. It is controlled by a sequence controller 18. There are two modes of operation of the driver/receiver boards 20 and 22: Gray code mode and protocol/data mode. All drivers/
The receiver board can operate in Gray code mode rather than protocol/data mode. For purposes of explanation, driver/receiver board 22 is assumed to be the only one that can operate in both modes. U.S. Patent No. 4,216,539 (incorporated into this application)
describes an in-circuit digital tester that operates with Gray code test signals. The present invention
It operates in conjunction with the in-circuit digital tester to easily extend the digital test signal generation capability to accommodate the test signal patterns required to test bus-based devices such as microprocessors. However, such pattern generation can be accomplished to some extent using Gray code test signals. Although the present invention is disclosed and discussed in connection with the unique testability of bus-based devices such as microprocessors, it is equally applicable to generating test signals for any type of digital logic device. In order to more easily accommodate the increasingly complex test signal pattern generation conditions for bus-based devices, a programmable sequence controller 18 operating in correspondence with the driver/receiver board 22 may be incorporated into the in-circuit digital test apparatus of FIG. 1. The present invention is a nail bed 2
Each of the four test pins has a corresponding pin memory for storing test signal generation data, thereby generating a desired test signal for each test pin. The test head controller 14 has a function tester 16 that performs any one of several previously selected test items on the signal appearing on the response signal line 17. The driver/receiver boards 20 and 22 also have selection means for selecting a signal appearing at one of the electrical connection points of the circuit under test as a signal to be supplied to the response signal line 17. Function tester 16 outputs response line 1 when enable signal (LISTEN ^* ) is logic zero.
7, in which a signal (LISTEN ^* ) is generated by the programmable sequence controller 18 and supplied to the test head controller 14. Inside this test head controller 14, there is a similar "LISTEN"
There is a signal, which in combination with the signal from controller 18 (LISTEN ^* ) causes functional tester 16 to "listen" to the signal on response line 17.
(LISTEN ^* ) If the in-circuit test equipment operates in protocol data mode, the programmable sequence controller 18 issues a "HALT" command to the test head controller 14 after the end of its test cycle. That is, the test head controller 14 normally generates a test cycle, but when in the protocol/data mode, the programmable sequence controller 18 generates a signal that ends the test cycle when a predetermined sequence of protocol and data test signals is generated. H.A.L.T.”
is generated. A central processing unit (CPU) 10 monitors the occurrence of this test cycle and selects various digital test signals to be generated during the test cycle.
CPU 10 sends and receives signals to and from test head controller 14 and programmable sequence controller 18 via I/O interface 12. Prior to the start of a test cycle, the CPU 10 sends digital test signal generation data needed during the test cycle to the driver/receiver boards 20, 22, and test cycle information, such as test cycle length, The specific functional test to be performed, the clocking signal frequency "MCKL", and other data are provided to the test head controller 14. If the test cycle is performed in protocol/data mode, the information needed to select for the protocol sequence and generate the sequence of pin memory addresses to generate the desired waveform is programmed. is sent to the enable controller 18. When a command is issued from the CPU 10, various necessary digital test signals are applied to predetermined inputs of the DUT 26, generating a test cycle that produces a response on the response line 17. After completion of this test cycle, the results of the functional tester 16 are sent via the I/O interface 12 to the CPU 10 for further processing. To generate Gray code test signals on driver/receiver boards 20, 22, a set of Gray code memory addresses is generated by test head controller 14. This Gray code memory address is provided to both driver/receiver boards 20,22. During a test cycle, a set of protocol/data memory addresses is generated by the programmable sequence controller 18 to generate the protocol/data test signals, but this address is provided only to the driver/receiver board 22. Appropriate address selection circuitry is provided on the driver/receiver board 20 to select pin memory addresses from the test head controller 14 and programmable sequence controller 18 and output the programmed digital test signal generation data stored therein from the pin memory. do. Concept of Protocol Control Data In FIG. 6b, a block diagram of a microprocessor chip, such as the Intel Model 8085 microprocessor, is shown, and its input and output signal lines are numbered. Furthermore, from the outside of the microprocessor chip viewed from the signals appearing on the input/output signal lines, the internal operation of the microprocessor can be clearly seen as shown in the timing diagram of FIG. 6c. FIG. 6c shows the digital signals present at the input and output pins of the microprocessor as it performs its normal functions. For example, four different cycles performed by the microprocessor shown in FIG. 6b are shown in FIG. 6c. A memory fetch cycle is shown in which the microprocessor fetches the contents of a particular main memory address from memory. To accomplish this function, the microprocessor must first send an address onto address buses A0-A15 during the initial portion of its fetch cycle. The address is typically provided to a microprocessor based main memory. The function of main memory is to store instructions and data needed by the microprocessor. At the appropriate time in the fetch cycle, the data at that particular memory address appears on the data bus portion of address buses A0-A7 as input signals to the microprocessor. When read command RD ^* (Read Command) goes to a high logic state, the data appearing on address/data buses A0-A7 are simultaneously input to the microprocessor to complete its fetch cycle. Also shown in the timing diagram of FIG. 6c are read and write cycles by the microprocessor. In the read cycle,
Once again, an address is output by the microprocessor on address buses A0-A15 specifying the memory address in main memory from which the data is to be read. At the appropriate time of a read cycle, the data at that specified memory address is transferred to address bus A0~A7.
It can be used for the data bus section of the microprocessor and is supplied to the microprocessor by the RD ^* signal. During a write cycle, the microprocessor uses the address bus
Addresses indicating locations in the memory where data should be written are supplied to A0 to A17. address line
According to the addresses A0 to A15, the data to be stored is supplied by the microprocessor to the data bus portion of the address bus. At the right time of the write cycle, a write command WR signal is generated,
Main memory typically provides an address/data bus
Causes the data appearing in A0-A7 to be supplied to the previously specified memory address. Finally, the 6th
In the reset cycle shown in Figure C, a reset in is output to the microprocessor,
It initializes the microprocessor's internal circuitry so that any other cycles can begin. To implement the microprocessor 8085 "in-circuit," if any of the four cycles shown are required, digital test signals must be generated as shown in FIG. 6c. The particular processor under test and its particular instruction set will dictate the order in which the various processor cycles are generated to test each performance of the device. The programmable sequence generator of the present invention has various test signals required for testing bus-based devices, such as microprocessors, divided into protocol test signals and data bus test signals. Further, in FIG. 6c, each of the four cycles shown, namely the fetch cycle, read cycle, reset cycle, and write cycle, will hereinafter be referred to as a protocol sequence. Address bus signal lines A0 to A15 (address/data bus A0
The signals appearing at ~A7) are data signals, and all other input/output signals consist of controller signals. Not all of the control signals need to be generated to carry out the selected protocol sequence. For example, the signals X ₁ , X ₂ ,
READY and RESET ^* must occur in a predetermined order during each protocol sequence shown in Figure 6c. During each protocol sequence, the microprocessor defines the specific timing sequence for each of the required control and data signals and also programs the test signal generation data associated with each of the test signal generators in the nail bed 24. Once placed in a pin memory and generating each sequence, any microprocessor cycle can be generated repeatedly by simply specifying the starting and ending addresses of the pin memory. That is, any desired sequence of protocol sequences can be generated by sequentially generating a sequence of starting and final memory addresses. In fact, the test signal generation data stored in the pin memory connected to the test pins is passed through a series of computer program subroutines that are sequentially called by the programmable sequence controller 18 to generate the control and data signals required for each protocol sequence. works exactly the same way. An example of the use of the programmable sequence generator of the present invention to execute a test program on the microprocessor shown in FIG. 6b is described below in the Sample Test Program section. Programmable Sequence Generator Protocol/Data Driver/Receiver Board 22 A detailed block diagram of the programmable sequence controller 18 and driver/receiver board 22 is shown in FIG. can generate eight data bus signals and eight protocol control signals. As mentioned above, each driver/receiver board 22 has 16
Both can work in Gray code mode as well as protocol/data mode for generating digital test signals for real test pins. In the protocol/data mode, eight test pins receive data bus test signals from data memory 52 and the remaining eight test pins receive protocol test signals from protocol memory 54. Data memory 52 and protocol memory 5
Corresponding to 4 is driver means 56 for converting the digital test signal generation data from each of its memories into logic levels that are provided to the DUT via selectable D relays connected to each test pin. Also, each test pin is connected to another 3
selectable switches, namely E, F, and G switches. For this E, F, G test program, the first instruction is to directly transfer (MVI55, A) the contents of the memory address next to the location containing the direct instruction to the accumulator. Since this direct instruction requires the contents of the next memory address to complete the execution of the MVI instruction, the read cycle follows the fetch cycle of the MVI instruction. During this read cycle, the address of the memory location to be read is output by the microprocessor, and the contents of that designated address 55 are simultaneously applied to the address/data bus lines by a test signal generated by the present invention. All read switches are bus wired to all of the driver/receiver boards 20, 22 to connect to these three buses. The F bus functions as a response signal line 17. To generate a test signal at the output of driver means 56, data memory 52 and protocol memory 54 are used.
and supply the address. This data memory and protocol memory have two
It outputs bits of digital signal generation data, one digital test signal for each test pin associated with a particular driver/receiver board, regardless of the mode in which it is performed. For preferred embodiments of the invention:
Both data memory 52 and protocol memory 54 are 1024
memory addresses, and each addressed memory location stores 16 bits of digital information, and 2 bits for each of the 8 test signals. A 10-bit binary address is required to address these 1024 memory locations. As mentioned above, each driver/receiver plate 22
may be operative to generate either a Gray code signal or a protocol test/data test signal.
FIG. 4 shows a data and protocol memory map for a typical driver/receiver board that generates up to 16 digital test signals. For driver/receiver boards 20, 22, when operating in Gray code mode, the above
Only 16 memory addresses are used for data memory 52 and protocol memory 54 to store Gray code test signal generation data (see memory locations 1023-1007 in FIG. 4). protocol/
When operating in data mode, all of the data memory and protocol memory addresses are available for storing test signal generation data for data test signals and protocol test signals. As shown in FIG. 1, the test head controller 14 generates the Gray code memory addresses.
It is. This address is provided to both types of driver/receiver boards 20,22. As further shown in FIG.
8,50. Driver/receiver board 2
2 operates in protocol/data mode,
Signal GRY/PSG is in the proper logic state and 2-
1 multiplexers 48, 50 to provide the four low order bit data addresses to the four low order bit address inputs of data memory 52, and also provide the four low order bits of the protocol memory address to the four low order bits of the protocol memory address. The four lower order address inputs of memory 54 are provided. The remaining six high order address bits are provided from the data address and protocol memory address via three-state buffers (not shown) to data memory 52 and protocol memory 54, respectively. During Gray code mode operation, this high order address bit is held high. Therefore, the 16 memory locations used to store Gray code signal generation data are the final 16 memory locations. Data memory addresses and protocol memory addresses are generated by the controller 18 in a predetermined sequence to output the digital signal generation data to its corresponding driver means 56 to generate the desired data bus test signals required to test the bus device under test. Produces protocol test signals. FIG. 3a shows the data memory 5 shown in FIG.
2, in which first and second memory sections, namely a data memory section 58 and a data enable memory section 60, are shown, which are part of the data memory 52. It is composed of departments. Each memory device 58, 60 is a 124-bit memory and, as previously mentioned, two bits of digital information are required by the driver means 56 to generate one digital test signal. These two bits of information are called data bits and data enable bits, respectively. FIG. 3b shows a memory map for a memory having n memory addresses with two bits of digital information stored in each memory location. For each memory address shown in that memory, the data (D) bit corresponds to the data enable (E) bit. The memory shown in FIG.
1 shows how the digital information from the test pin 1 is combined to generate a digital test signal for test pin 1. That is, a data bit appears on line 82 and a data enable bit appears on line 84. In the preferred embodiment of the invention, data memory 52 and protocol memory 54 are constructed from memory chips with a 1024.times.4 bit array. Therefore,
Although the memory sections 58, 60 shown in FIG. 3a are only capable of producing four data bus test signals, each driver/receiver board 22 is capable of producing a total of eight data bus test signals. Figure 3a
The remaining four data signals can be generated by using two of the circuit configurations shown in FIG. It will be obvious to one of ordinary skill in the above technology to choose different memories with different numbers of memory addresses and different numbers of bits in each address to implement the invention. For example, to double the signal generation capacity of memory sections 58 and 60, four 2-bit 1024 x 2-bit memories could be selected. Furthermore, in FIG. 3a, the data memory section 58
and the respective digital signal generation data stored in the data enable memory section 60 are AND/
OR selection gate circuit 62 and quadrature latch circuit 6
4 is supplied to an identification logic circuit consisting of 4. These 2
The devices 62 and 64 are connected in series, and the output of the quadrature circuit 64 is used as the B-input.
Feedback is provided to the AND/OR logic gate circuit 62. The A- input of gate circuit 62 is 4 bits from either data memory section 58 or data enable memory section 60. logic gate circuit 62
The function of the latch circuit 64 is that when the driver/receiver board 22 is operating in Gray code,
The logic level on line 83 is such that each time a logic one appears on line 82 from data memory section 58, the generated digital output test signal will change state each time a logic one is read from data memory section 58. , acts to change the logical state. When the driver/receiver board 22 operates in the protocol/data mode, the logic level developed on the signal line 83 is transferred from the data memory section 58 to the signal line 82.
It follows the logical level that appears in . That is,
The logic level output by data memory section 58 specifies the logic level appearing at the output of driver amplifier 55, rather than specifying the transition of that digital signal as in the Gray code mode. For Gray code and protocol/data modes, when a logic 1 appears on signal line 85, the logic level on signal line 83 is passed through driver amplifier 55 and appears on line 87 to the D-selectable relay corresponding to test pin 1. Given. The data enable data stored in memory section 60 is selected according to the operating mode to cause a logic 1 to be applied to the output of its corresponding latch circuit 65 when an output logic level is to be generated for that test signal.
cause Sequence controller 18 also generates a data enable signal, DATA ENABLE, which is provided to each logic gate circuit 62. When this data enable signal is true, the combination of gate circuit 62 and latch circuit 64 prevents the generation of any logic signal from its corresponding driver means 56. According to this feature, the device under test itself
When generating logic levels on lines monitored by in-circuit test, all data bus test signals from that address/data bus line can be removed. The selection of the operation mode for the logic gate circuit 62 is specified by the logic level of the signal GRY/PSG,
The clock signals for 65 are DSYNC and ESYNC.
Provided based on the signal. In the preferred embodiment of the present invention, logic gate circuit 62 is manufactured and sold by Monolithic Memory Corporation as PAL 14H4. This device is a programmable device and corresponds to a 512x4 bit ROM. The programming of this device is tabulated on the last page of this specification (after the brief description of the drawings). The memory configuration discussed with respect to data memory 52 in FIG. It does not occur by twisting. Shown in FIG. 3a is a detailed circuit diagram of a driver amplifier, such as amplifier 56. The operation of transistor switches Q ₁ , Q ₂ , Q ₃ , and Q ₄ is well known and obvious to those of ordinary skill in the art and will not be described in detail, but one point will be made. When the data enable bit on line 85 is true, driver amplifier 55 outputs the logic state appearing on signal line 83 on signal line 87. That is, if line 83 logic 1
When , line 87 is at a logic level corresponding to the _Vcc voltage level of DUT 26, and if it is a logic 0, then
Line 87 is also a logic zero. On the other hand, if the data enable bit on line 85 is false, 3-state buffer 70 also
also produces no output in response to the logic signal on line 83.
As a result, transistors Q ₂ and Q ₄ are non-conducting and the signal on line 87 is an open circuit. Programmable Sequence Controller 18 FIG. 2 shows a more detailed block diagram of the programmable sequence controller 18 shown in FIG. The program sequence controller 18 is comprised of a protocol sequence control device 28, a buffer memory device 40, a protocol address counter 44, a data address counter 36, a protocol sequence length memory 38, and synchronization means 42. Protocol address counter 44
and data address counter 36 serve to generate addresses for protocol memory 54 and data memory 52, respectively, and these address counters also include clock signals derived from the MCKL clock signal from test head controller 14 (see FIG. 1). A clock PSG MCKL is supplied. The protocol sequence length memory 38 supplies protocol test signals in the form of enable signals to the data address counter 36 and also to the protocol address counter 44 via synchronization means 42 . This signal causes each address counter to generate a predetermined sequence of addresses required by data memory 52 and protocol memory 54 of driver/receiver board 22 to generate data bus test signals and protocol test signals. The addressing of the protocol sequence length memory 38 is done by the output of the protocol address counter 44, i.e.
The enable signal from 8 is synchronized with the generation of the protocol test signal. The data input line of protocol address counter 44 is connected to the output of buffer memory 40 which contains the starting address of the protocol sequence to be generated during the test cycle. buffer memory 4
0 is a first-in-first-out (FIFO) memory in the preferred implementation of the invention. A synchronization means 42 is connected between the FIFO memory 40 and the protocol address counter 44, which
The contents of the FIFO memory 40 are read, and when a start address exists on the output signal line, the start address is simultaneously supplied to the protocol address counter 44. In the preferred embodiment, the protocol address counter starts at the starting address specified by the contents of the FIFO memory 4.
Generate consecutive memory addresses for each successive protocol sequence until the last address for 0 is generated. Synchronization means 42 synchronizes the UNLOAD clock signal with
Supplies it to FIFO 40 and calls the next starting address. When that address is present on the output signal line,
A signal OUTPUT RDY is generated and the synchronization means 42
is supplied to At appropriate times, synchronization means 42 generates a load clock signal to protocol address counter 44 and simultaneously supplies that counter with the current starting address present at the output of FIFO memory 40. The protocol sequence length memory 38 indicates to the synchronization means 42 when the last address of the current protocol sequence has occurred. Protocol sequence length memory 38 has as many addresses as protocol memory 54 on driver/receiver board 22 and is fed by as many address signals. Therefore, by storing the protocol test signal at a location corresponding to the last memory address for each protocol sequence,
When that address occurs, the logic signal LAST
ADDRESS is generated at the output of memory 38 to indicate to synchronization means 42 that the current protocol sequence has ended and the next protocol sequence start address from the FIFO memory can be loaded into protocol address counter 44. . Protocol sequence length memory 38 generates four enable signals. This signal is
LAST ADDRESS and LISTEN ^* and DATE
ADVANCE, and DATE ENABLE.
The function of LAST ADDRESS, as described above, is to update the protocol address counter 44 with the next memory start address for the next protocol sequence to be generated. The function of the LISTEN ^* signal is to selectively enable a functional tester included in test head controller 14 to test the signal on response line 17 during a test cycle, as described with respect to FIG. The signal LISTEN ^* generated in the programmable sequence controller 18 is
It is combined with the internal LISTEN ^* signal generated in the above to control the function tester 16. enable signal
DATE ADVANCE increments the data address counter 36 by one address each time the DATE ADVANCE signal becomes true using the PSG MCKL clock signal. That is, data address counter 36 is not in free running mode like protocol address counter 44. A DATE ADVANCE signal must be generated from protocol sequence length memory 38 each time data address counter 36 increments. Finally, the function of the signal DATE ENABLE is that the driver means 5 corresponding to the data memory 52
6, it is possible to generate a data test signal according to the data stored in the data memory 52. Unlike the driver means 56 associated with the data memory which is responsive to the DATE ENABLE signal from the protocol sequence length memory 38, the driver means 56 associated with the protocol memory 54 is not supplied with an enable signal from the controller 18 and is not supplied with an enable signal during the test cycle. Do not generate protocol signals. Primarily, the function of the DATE ENABLE signal to driver means 56 is to ensure that a driver amplifier, such as amplifiers 55, 57, generates an open circuit signal at its output while the data bus line to which it connects has a signal generated by the device under test. It is to be. Most data buses have a dual purpose; they may send addresses or they may send data. If driver/receiver board 22 is to generate digital test signals on the data bus signal lines, driver means 56 is enabled by DATE ENABLE. However, the driver/receiver plate 22
If there is data on the data bus line that is not generated by DATE ENABLE, driver means 5
6 cannot cause an open circuit at the outputs of the driver amplifiers 55, 57. Referring also to FIG. 2, programmable sequence controller 18 further includes three-state buffer devices 34, 35, which
By giving a buffer effect to the programming data from the CPU 10, the protocol sequence length memory 3
8 and a protocol controller memory 32 that is part of the protocol sequence controller 28 . At the beginning of a test cycle, data address counter 36 is always set to address 0. Controlling the generation of various protocol sequences during a test cycle is a protocol sequence controller 28, which includes a bit slice processor 30 and a protocol controller memory 32. Protocol controller memory 32 contains operational codes or instructions that processor 30 executes during test cycles. Memory 32 has a word length of 16 bits (PCM0-PCM15), and the upper 4 bits (PCM12-PCM15) serve as machine executable code for processor 30 (see FIG. 7b). Protocol controller memory 3
The lower 11 bits of 2 (PCS0-PCM10) contain data needed by processor 30 to execute its instructions, such as the various starting addresses of the protocol sequences to be generated during the test cycle. PCM 11 generated from memory 32 provides a load clock signal to FIFO 40 when the lower 10 bits (PCM0-PCM9) define the starting address to be loaded into FIFO memory 40. Processor 30 has internal addressing circuitry that addresses protocol controller memory 32 to output the next instruction to be executed. Further, the instruction execution speed of processor 30 is faster than the speed at which protocol address counter 44 generates a predetermined sequence of protocol memory addresses. The function of FIFO memory 40 is to provide a buffering effect on the starting address generated by processor 30 at relatively high speed, and to inhibit continuous execution of instructions by processor 30 when FIFO memory 40 is full. In this manner, execution of instructions by processor 30 is on an as-needed basis and is required whenever FIFO memory 40 is not full and whenever there are more instructions from protocol controller memory to execute. When the program stored in the protocol controller memory 32 ends, the processor 30 automatically enters a looping state, and the start address is not output to the FIFO memory 40. In this case, the FIFO generation signal is sent to the processor 30,
The looping instruction can be allowed to run while the contents of FIFO memory 40 continue to be retrieved upon completion of each protocol sequence. When FIFO memory 40 is empty, the OUT RDY signal no longer produces a true signal in response to the UNLOAD clock from synchronization means 42. Upon this occurrence, synchronization means 42 does not generate a load clock LDAC to protocol address counter 44, but instead generates a HALT signal and inputs this to test head controller 14. The HALT signal ends the current test cycle occurrence. In this preferred embodiment of the invention, processor 30 employs an Advanced Microdevices Model No. Am2910 microcomputer. This material regarding Am2910 is copyrighted by Advance Micro Devices Co., Ltd. (1979), publication No. AM-PUB003,
"Am2900 series data book and related support circuits"
It can be seen in Buffer Memory Device 40 and Synchronization Means 42 Referring to FIG. 5, a more detailed circuit diagram of the buffer memory device 40 and synchronization means 42 is shown. In a preferred embodiment of the present invention, buffer memory device 40 is one of two 5-bit FIFO memories 116 and 118 manufactured and sold by Texas Instruments as Model SN74S225.
connected to form a 10-bit FIFO memory. These registers (memories) work in a manner well known to those skilled in the art and will not be described in detail. Also shown in FIG. 5 is a circuit diagram of the synchronization means 42. At the beginning of a test cycle, the synchronization means 42 synchronizes the buffer memory device 40 with
Signal 1ST when OUTPUT READY signal occurs
ADDR (first address during test cycle) is generated by flip-flop 110, which outputs PSG to the reset input before the start of the test cycle.
This is because it is cleared by the generation of the DCLR signal. With the generation of 1ST ADDR, the signal
LDAC is generated to protocol address counter 44. Flip-flop 90 is the OUTPUT READY from FIFO buffer memory device 40.
An enable signal (Q) is supplied to the AND gate 92 in accordance with the signal. Depending on the state of OUTPUT READY, the load clock signal LDAC to the protocol address counter 44 and buffer memory device 40 or HALT to the test head controller 14
A signal is generated upon generation of the signal LAST ADDRESS from protocol sequence length memory 38.
LAST ADDRESS is input to OR gate 98 and NAND gate 86 of synchronization means 42, NAND gate 86 generates HALT ^* signal and OR gate 9
8 is a flip-flop 90 to an AND gate 92
A logic signal is generated which is combined with the Q output from the LDAC to generate the load clock LDAC. Therefore, if
If OUTPUT READY is a logic 0, indicating that there is no starting memory address in the buffer memory device 40, then the next occurrence of LAST ADDRESS causes the signal HALT ^* to be asserted in the test head controller 14.
is supplied to complete the test cycle. If the OUTPUT READY signal is logic 1,
If indicating that another protocol sequence is to be generated, upon generation of signal LAST ADDRESS, signal LDAC is generated and loads its starting address into protocol address counter 44. 1st
To load the first starting address of the protocol sequence into the protocol address counter 44, the signal 1ST ADDR is generated at the beginning of the test cycle. This signal is the OR gate 98
Take the AND logic with LAST ADDRESS and make the first
Provides LDAC load clock to protocol address counter 44. Sample Test Program The invention is best understood by reference to an example test program for working with a bus-based device, such as a microprocessor. Figure 6b shows an Intel microprocessor (Model
8085), and its input/output control signals and address/data bus lines are also shown. FIG. 6c is a timing diagram of the various input and output signals of FIG. 6b for four processor cycles - fetch cycle, reset cycle, read cycle, and write cycle. FIG. 6a shows a three-instruction test program written in microprocessor assembly language that is simulated by the present invention during a test cycle. During this test cycle, functional tester 16 tests one of the microprocessor generated input/output signals for appropriate response. The first instruction MVI of this test program is hexadecimal 55
is sent directly to the accumulator A, and the second
The command INR A is to increment the contents of the A-accumulator. Also the third and final command
STA, B5E3 is to store the contents of the A-accumulator in the memory location with hexadecimal address B5E3. Also shown in FIG. 6a are operation codes stored in six consecutive main memory addresses that are normally accessed by the microprocessor to execute three instructions of a test program. FIG. 7a shows a test program written in the language of the in-circuit digital test equipment.
CPU 10 converts the instructions of the test program into instructions for processor 30 which executes during the test cycle to generate the necessary test signals and causes the microprocessor under test to execute the test program. The program of this processor 30 appears in the protocol controller memory 32 as shown in FIG. 7b. To begin testing, a microprocessor reset cycle is first performed. The reset cycle initializes (initializes) the internal circuitry of the microprocessor. In order for the microprocessor to obtain the first instruction in the test program, it must perform a fetch cycle. The purpose of this instruction is to tell the microprocessor on its address/data bus to
This is to input the operation code to be executed by the internal circuit of the processor. Upon completion of this microprocessing cycle, instruction MVI55,A terminates. The next instruction in the microprocessor's test program must be found in the second fetch cycle. Since instruction INR A does not require any further input or output cycles by the microprocessor, at the end of the execution of the A-accumulator step, another fetch cycle must be performed to obtain the third instruction of the test program. Must be. That is, two consecutive fetch cycles must occur to obtain the second and third instructions. 7th
The tester program shown in Figure a supports this function.
Shown as REPEAT FETCH TWO TIMES. The third command is the command STA to store the contents of the accumulator in memory. This command is a command
The contents of the next two consecutive memory addresses following the location where STA is stored must be read to obtain the address B5E3 of the location where the contents of the accumulator are stored. Therefore, at the end of the third fetch cycle to obtain the third instruction of the test program, it is necessary to generate two consecutive read cycles to obtain the contents of the second and third memory addresses following that instruction. be. These two read cycles are REPEAT READ TWO
This is done in the test program when TIMES is executed (see Figure 7a). As part of the execution of instruction STA, it begins a write cycle to transfer the contents of the accumulator to a specified memory address, e.g.
Must be stored in B5E3. At the end of the write cycle, the microprocessor test program is complete and processor 30 enters a looping state upon execution of the test program instruction HALT. FIG. 7b shows the protocol controller memory 32.
It shows the contents of. The 12th to 15th bit opcodes of this controller memory word are binary codes for instructions to be executed by processor 30 and are machine executable. Corresponding to this instruction opcode, an assembly language instruction to processor 30 to be executed is shown. Each protocol controller memory 32
The data part of the word (bits 0 to 10) is shown after being converted into a decimal number. For example, address number 0 of the protocol controller memory 32 is an instruction.
Stores the decimal number 26 in the data section of LOAD FIFO40. This instruction reads the contents 26 of the data section of the instruction.
This is to load the FIFO buffer memory device 40. FIG. 7c shows the contents of the proto-memory 54 and the protocol sequence length memory 38. Since these memories are addressed by the output of protocol address counter 44, the data in the two memories is shown alongside each other as a function of protocol memory address. For this embodiment, data bit D of protocol memory 54 (FIG. 7d)
(also for data memory 52 shown in FIG. 1) is shown only because the data enable bits E for the protocol memory are all logic ones. Although this enable bit E is a logic 1 in this embodiment, the control and data bit signals may be provided open circuit with the E enable bit being a logic 1. This is desirable when testing a DMA controller for some logical device, such as a microprocessor. The in-circuit digital test equipment simulates several control inputs during part of the test cycle, and the DMA circuit simulates several control inputs during another part of the test cycle. There is a need to. For the protocol/data mode, the digital test signal to be generated by the driver means 56 should follow the logic state of the data in the memories 52, 54, rather than producing a transition in the test signal when the data bit is a logic one ( Gray code operating mode). Furthermore, the sixth
The four microprocessor cycles shown in Figure c are stored in protocol memory 54 starting at address 0 and ending at address 33. For fetch cycles, the starting address is protocol memory address 0 and the ending address is protocol memory address 9. Similarly, for the read cycle, the starting address is 10 and the ending address is 17, and for the writing cycle, the starting address is 18, and the ending address is 25,
Additionally, for the reset cycle, the starting address is 26 and the ending address is 33. FIG. 7d shows the data stored in the data memory 52. As shown in FIG. 6b, the signals on address/data bus lines A0-A7 are generated by data stored in data memory 52. Since the microprocessor should be tested separately from its main memory, data memory 52 generates a data bus signal supplied from its main memory when performing a read or fetch cycle. Also shown in FIG. 7d is the hexadecimal equivalent of the binary code stored in the data memory address. As can be seen, the hexadecimal equivalents of the data stored at addresses 0, 2, and 3 of data memory 52 correspond to the opcodes of the microprocessor test program instructions shown in FIG. 6a. Referring to FIG. 7b, the first instruction executed by processor 30 of protocol sequence controller 28 is to load FIFO 40 with the starting address of the reset cycle. In this embodiment, the start address of the reset cycle is address 26. With the starting address now present in the FIFO 40, the synchronization means 42 loads that address 26 into the protocol address counter 44, which immediately causes the protocol memory 54 and its corresponding driver means 56 to be programmed with the RESET of the microprocessor under test. IN input (test terminal 3)
Generates a logic low level for The protocol address counter 44 continues to increment its address until it reaches the final address 33. At this point, the contents of the protocol sequence length memory 38 output a logical 1 for the last address (see Figure 7c);
Causes the synchronization means 42 to load the next starting address of the next protocol sequence if OUTPUT READY is true. As mentioned above, processor 3
Since 0 executes instructions at a faster rate than the increment of protocol address counter 44, the next protocol sequence start address is contained in FIFO 40 and the OUTPUT READY signal is true. Still referring to FIG. 7b, the contents of the second address of protocol controller memory 32 include an instruction LOAD FIFO 40 with the starting address of the fetch protocol cycle. In this example, this address is decimal zero. The next instruction in protocol controller memory 32 is to load FIFO 40 with the starting address of the read cycle, decimal 10. The instructions stored at addresses 3-5 of protocol controller memory 32 perform a looping function to produce two fetch cycles in a row. The instruction at address 4 loads the start address of the fetch cycle, address 0 in this embodiment, into FIFO 40.
Instructions at addresses 3 to 5, PUSH/LOAD
CNR, LOAD FIFO40, REP LOOP/CNR0
The result is to repeat the fetch cycle twice. Similarly, instructions at addresses 6-8 perform two read cycles. At the end of these two read cycles, the protocol controller memory 32 stores the start address of the write cycle, in this example at address 18.
Outputs the command LOAD FIFO40. At the end of that instruction, the protocol controller memory 32
provides a jump instruction to processor 30 that causes it to execute the instruction at address 10 continuously and repeatedly. In other words, the processor is forced to loop endlessly over similar instructions. As each instruction of the processor 30 is executed, the protocol address counter generates a predetermined series of protocol memory addresses, and the data address counter sequentially generates a predetermined series of data memory addresses in the sequence length memory 38. make it happen. Upon completion of each protocol sequence, FIFO 40 provides a new starting address to the protocol address counter. As long as FIFO 40 is not full, processor 30 continues to execute its instructions and load FIFO 40 with its starting address. Since the starting addresses for various protocol sequences are loaded into the FIFO 40,
Programmable sequence controller 18 continues to operate as described above until FIFO 40 is empty.
Generates various protocol sequences until the HALT signal is generated. To determine that the microprocessor is generating the correct response signal as a result of the generation of the input signal, the protocol sequence length memory 38 stores the digital information on the response line 17 to which the functional tester 16 should respond.
Generate LISTEN signal. For example, fetish,
At the beginning of a read or write cycle, the microprocessor connects its address/data bus line A0.
~ Outputs the memory address to A7 (see Figure 6c). This data is the response signal that the functional tester should test. Therefore, the protocol sequence length memory 38 can output a logic 1 in response to the LISTEN signal, allowing the functional tester to monitor the response line 17. Additionally, during the write cycle, the microprocessor outputs the critical data to be tested on address/data buses A0-A7 under test. Figure 7c shows that during each cycle,
This shows the case when the LISTEN signal is true. In FIG. 6c, for each fetch, read, and write cycle, there is a point at which data is provided to its address/data bus lines A0-A7. At this time, the protocol sequence length memory 38 outputs a logic 1 in response to the DATA ENABLE signal when the driver amplifier of the driver means 56 supplies a digital data signal to the data bus. Before the start of a test cycle, data address counter 36 is reset to address zero.
(Figure 7d shows the contents of the various data memory 52 addresses.) Even if the data memory 52 supplies its contents to address 0, it will only do so until the DATA ENABLE signal from the protocol sequence length memory 38 becomes true. , any digital data signals are generated by driver means 56 corresponding to the data memory 52. As shown in Figure 7c,
The contents of address 0 of data memory 52 are supplied to the microprocessor and are transferred to two consecutive memory addresses 6, 7 of protocol memory 54 corresponding to the fourth cycle of microprocessor clock signals X1 and X2 during the fetch cycle. is memorized.
DATA ENABLE signal is memory address 6,7
is true for At protocol memory address 7, protocol sequence length memory 38 is DATA
A logic 1 is output in response to the ADDRESS ADVAMCE signal, and the data address counter 36 is incremented by one address to the next consecutive address 1. The DATA ENABLE signal goes to logic 0 at the end of protocol memory address 7. Data address counter 36 now indicates that even if addressed memory location 1 of data memory 52 is DATA
Since the ENABLE signal is at logic zero, no digital test signal is output by driver means 56. Data address counter 36 receives DATE from protocol sequence length memory 38.
It does not increment to the next consecutive address until the ADDRESS ADVAMCE signal next becomes a logic one. The programmable sequence controller 18 is
The contents of the FIFO 40 are continued to be transferred to the protocol address counter 44, and various sequences are generated until the FIFO 40 is empty. At this point, the test cycle is complete and the contents of functional tester 16 are
0, whereupon the microprocessor performs further evaluation to determine whether it did so correctly. Although the invention has been described in terms of preferred embodiments, it will be apparent to one skilled in the art that other modifications may be made within the scope of the claimed invention by one skilled in the art. (Effects of the Invention) Since a given sequence of instructions only needs to be stored in one memory location, many sequences of test signals can be executed on the device under test without the need for large buffer memories. be. Therefore, the memory size required for testing the device under test can be reduced. Further, the protocol control sequence can be called repeatedly as needed, and the hardware of the test device can be reduced.

【table】

【table】

[Brief explanation of drawings]

FIG. 1 is a block diagram of an in-circuit digital test device to which the present invention is applied, and FIG. 2 is a more detailed block diagram of the programmable sequence controller and driver/receiver board of the in-circuit digital test device shown in FIG. It is.
3a is a more detailed circuit diagram of the data memory and driver means of the driver/receiver shown in FIG. 2, and FIG. 3b is a more detailed circuit diagram of the data bus test signal for generating the data bus test signal. FIG. 4 is a diagram showing how generated data is stored in a data memory and a data enable memory, FIG. 4 is a pin memory map of the data memory and protocol memory shown in FIG. 2, and FIG. 6A is a detailed circuit diagram of the synchronization means and buffer memory device of the controller shown in FIG. 6A, and FIG. 6B is an explanatory diagram of a test program for testing the microprocessor shown in FIG. 6 is a diagram showing the pin arrangement of control signals and data bus signals of the microprocessor, and FIG. 6c is a timing diagram of control and data bus signals for various cycles of the microprocessor shown in FIG. 6b. It is. Furthermore, FIG. 7a is an explanatory diagram of the memory contents of the program of the programmable sequence controller that can cause the program controller to execute the program of FIG. 6a, and FIG.
FIG. 7c is a memory map of the data and sequence length memory that generates the timing signal shown in FIG. 7c, FIG. 7d is a memory map of the data memory shown in FIG. 1 illustrates the contents of a typical data memory for generating data bus test signals necessary to simulate a particular microprocessor program; FIG. 1... In-circuit digital test device, 1
4...Test head controller, 16...Function tester, 18...Programmable sequence controller, 20, 22...Driver/receiver board, 24...Nelvette, 26...Device under test.

Claims (1)

[Scope of Claims] 1. An in-circuit digital test device for testing the electrical performance of components of a circuit under test having a plurality of data bus lines during a test cycle using a central processing unit, ) a response line for monitoring digital response signals from the circuit under test; and (B) a functional desta for testing the signals on said response line during a test cycle to measure the electrical performance of the components of the circuit under test. (C) a set of test pins that make contact with selected electrical connection points of the circuit under test and provide input and output points for the circuit under test; and (D) generate test signals for the input points of the circuit under test. A plurality of test signal generators are provided corresponding to the test pins, each of which includes: (a) data bus test signal generation data for generating data bus test signals for a plurality of data bus lines; (b) a plurality of data memories provided corresponding to each of the test pins, which are output in response to predetermined consecutive data memory addresses, and which store these data bus test signal generation data, and (b) a predetermined consecutive protocol memory. each of a plurality of protocol sequences is defined by a plurality of protocol test signals generated in response to a starting address for generating a plurality of protocol test signals for such a plurality of protocol sequences; (c) a plurality of protocol memories provided corresponding to each of the test pins that store protocol test signal generation data starting and ending at the final address; (E) a plurality of test signal generators connected to the test pins and including a driver means for causing generation of a data bus test signal or a protocol test signal at the input point in response to signal generation data; (F) response signal selection means for supplying a signal on a selected one of the test pins to the response line in response to the device; generating the predetermined consecutive data memory addresses and protocol memory addresses in response to the central processing unit; An in-circuit digital test device, comprising a sequence controller for selectively enabling testing. 2. In claim 1, each of the data memories includes: (a) a plurality of data memories each coupled to a generated test signal and recording and outputting logic level generation data according to a memory address from the sequence controller; (b) coupled to each of said first memory sections to record and output signal level enable data in accordance with an address from said sequence controller to generate an output signal level from said corresponding driver means; an in-circuit digital test apparatus, comprising a second memory section connected to the data memory, the driver means further generating data bus test signals enabled by the sequence controller. 3. In claim 2, the sequence controller further generates a digital mode control signal having first and second states for controlling the mode of operation of the driver means, thereby controlling the mode of operation of the driver means. (a) when the specific logic level of the logic level generation data is output by the first memory unit and the mode control signal is in the first state, generating a specific logic level in the output test signal; and (b) generating a logic level transition in the output test signal when a particular logic level of the logic level generation data is output by the first memory unit and the mode control signal is in the second state; In-circuit digital test equipment. 4. In claim 1, the sequence controller comprises: (a) a protocol sequence control device that executes a series of test program instructions and generates a start address for each protocol sequence; (b) the protocol sequence control device a buffer memory device connected to the output of the device and temporarily storing and outputting a start address of a protocol sequence in the order of instructions; (c) a protocol address counter generating a protocol memory address in accordance with the output from the buffer memory device; d) a sequence length memory for outputting a signal in accordance with said protocol memory address to enable generation of a predetermined continuous protocol memory address and data memory address; and (e) a data memory address in accordance with said sequence length memory. (f) synchronization means for updating said protocol address counter with the start address of the next protocol sequence to occur in response to said sequence length memory and said buffer memory device; Digital test equipment.