US4903199A - Method of increasing the speed of test program execution for testing electrical characteristics of integrated circuits - Google Patents
Method of increasing the speed of test program execution for testing electrical characteristics of integrated circuits Download PDFInfo
- Publication number
- US4903199A US4903199A US07/183,195 US18319588A US4903199A US 4903199 A US4903199 A US 4903199A US 18319588 A US18319588 A US 18319588A US 4903199 A US4903199 A US 4903199A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/865—Monitoring of software
Definitions
- This invention relates to test systems for integrated circuits, and more particularly to a method for increasing the speed of interpretive code execution and for changing test codes.
- An application or high level language is a program written in a form which a user of a computing or test system is familiar, rather than a machine language, and includes a coded instruction stream which is convertible into a plurality of serially executable source statements, selected source statements including one or more operands in the form of symbolic addresses, and other selected source statements requiring conditional or unconditional branches to still another source statement identified by a label.
- a compiler is a program which operates in a computing system, taking as its input the machine readable instruction stream of a program written in a high level language, to interpret the source statements and produce object code.
- the object code is suitable for link editing into a load module which is directly executable by the computing system, and generally includes more than one object (machine language) instruction for each source statement.
- Commonly used high level languages include COBOL, FORTRAN, and BASIC. Each of these high level languages are written with a series of instructions that use English like statements, and in some instances mathematical notations. COBOL and FORTRAN programs are usually complied prior to program execution. BASIC can also be compiled, but in some computers BASIC is interpreted. The interpreter takes each BASIC statement or command and interprets or translates it to a machine language equivalent. The machine language equivalent is executed immediately. No machine language code is generated that can be used again as in a compiled program.
- the invention is useful in testers for testing integrated circuits and is a method of taking an interpreted language, a language similar to the BASIC language, that is used in device test programs, and after a single execution of a single test loop using a pseudo code representative of the the high level language in which the program is written, TPL (Test Program Language), the pseudo code is restructured to write a table and a short assembly language program that is executed for each successive loop of the test program.
- TPL Test Program Language
- the test system consists of several test heads, each controlled by a dedicated processor. Communicators between each test head and a controller is carried out through an I/O interface.
- the hardware for each test head is memory mapped into local address space of each test head processor board.
- the method of the invention is herein referred to as Turbo Processing or, Turbo Code, or Turboed.
- FIG. 1 is a diagram of a typical line of Test Program Language that has been translated into pseudo code
- FIG. 2 is a diagram of the pseudo code of FIG. 1 that has been restructured according to the present invention.
- TPL Test Program Language
- BASIC BASIC- like language developed for use in testing integrated circuits.
- Turbo code enhances the performance of TPL, allowing certain statements to execute faster in an interpreted environment than is possible in a compiled environment.
- test head hardware is memory mapped, so accesses to the test head hardware look just like local memory reads and writes;
- the TPL device test programs execute a single test loop continuously to test a large number of devices;
- TPL uses a pseudo code representative of each statement to control execution of the statement and is structured to allow the pseudo code to be altered at runtime to change the flow of execution; and
- a large percentage of the TPL statements compute values which do not change from one execution of the statement to the next, or compute variables which depend only on the selection of an array element where all possible values of the array can be determined the first time the statement is executed.
- IN:PINS is an array of pin numbers. This statement will program all of the Parametric Measurement Units specified in the array IN:PINS to one volt with 500 milliamps of current;
- pin cards All values being assigned must be constants.
- the pin cards must be specified by constants, an entire predefined array, or a predefined subscripted array. Also, if an array is used for the pin card specification, the values in the array may not change between executions of the turboed statement.
- Turbo code takes advantage of all of the features of the hardware and software to provide very high speed programming of the test head hardware while still maintaining the flexibility of an interpreted language.
- Turbo code uses the first execution of a statement in an interpreted environment to build a table of address-value pairs corresponding to the values computed by the statement. It then changes the pseudo code of the statement to use a short assembly language routine to write the values in the table to their appropriate addresses, using the memory mapped feature of the test head hardware.
- each TPL line As each TPL line is loaded, it s translated into pseudo code.
- the emulator mainline uses this pseudo code while executing the statement. For example, the statement
- the Test Program Language translator generates a group of records for each line as it is translated (See FIG. 1).
- the main record is called the parm -- rec. It contains a pointer to the pseudo code translation of the line (parm -- ptr).
- Each pseudo code record contains a pointer to the next record (next -- parm), the type of the pseudo code parameter (verb parm, hdw parm, etc), and the parameter itself.
- the parm -- rec also contains a pointer to the actual source code for the statement and a pointer to the interpreter routine which is used for the specified verb (verb -- ptr).
- the emulator uses the verb pointer to begin processing with the LET verb routine.
- the LET verb routine checks the parm -- ptr and determines that the first parameter is a hardware parm. It then calls pt -- hardware processing, which determines that the hardware parm is .PMUV and calls PMUV processing.
- PMUV processing calls a routine which looks for the variable PINS in the symbol table. It then checks the data area to determine all of the values in the array PINS. These logical pin numbers are translated into physical pin numbers to determine the pin boards being programmed in the LET statement.
- PMUV processing then calls a routine which checks the parameter list, sees the self -- defining constant 3.1V, and returns this value to be programmed as the PMU voltage.
- the routine is called again and returns the 100 ⁇ A to be programmed for the .PMU current.
- Each of these values is checked to make sure it is in the proper range and is then calibrated using gain and offset values stored in memory. This result is then translated into a 16 bit value which is written to the pin cards determined by the variable PINS.
- the values used to program the PMUs are also saved in memory for possible use later.
- the TURBO software for this simplest case is a short assembly language loop:
- the first five lines of this routine constitute a fixed overhead each time a turboed statement is executed, and the three line loop is executed once for each value that needs to be written by the routine. Because the test head hardware is memory mapped, no distinction needs to be made between data being saved by the software and data being written to the test head. Also, all error checking and calibration is done by the emulator code the first time the statement is executed and does not need to be repeated. Therefore, only three instructions are executed per value written, plus a small fixed overhead. In most cases, this code will execute faster than would code generated by a compiler since the compiled code needs to do most checking and calibration each time the statement is executed.
- min and max are constants or variables
- the comparison is one of .LT, .LE, .NE, .GT, or .GE
- the function is any function defined in TPL, such as .ADC or .ADCR;
- n evaluates to -1.
- the table generated contains (1) the address of the first variable (min); (2) the address of the second variable (max); (3) the type of comparison (LT); (4) a pointer to the function parameter; and (5) the address of the line to be executed if the statement is false.
- the verb pointer is changed to point to a turbo-if routine.
- the IF statement must search forward through the test program to find the corresponding ELSE or ENDIF statement when the expression in the IF statement evalutes to false.
- the turbo-if routine calls the normal interpreter routine to determine the function value, and gets the min and max values from the addresses specified in the table and makes the appropriate comparison. If the comparison is true, execution continues with the next statement. If it is false, the execution is continued at the address stored in the table. This eliminates the overhead of checking the statement syntax, determining the min and max values, and searching ahead for the address to jump to if the expression is false.
- the print statement is turboed to take care of the special case where the unit number is -1.
- Output from the PRINT routine can be sent to the terminal, line printer, or several other output ports. This is controlled by the unit number. When the unit number is -1, output is suppressed. This is used mainly in production test programs so that printing of some information can be dynamically controlled.
- a turbo table is built which contains the address of the variable used in the unit number (n).
- the verb pointer is then changed to point to a print-turbo routine. This routine checks the value of n. If it is still -1, the rest of the PRINT statement is ignored and execution continues with the next statement. If the value of n has changed, the normal PRINT verb processing is called.
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- Tests Of Electronic Circuits (AREA)
Abstract
Description
LET.VCCl=500mV,250mA
LET.PMUV(IN:PINS)=lV,500mA
LET.DRVL(IN:PINS(I))=250mV
______________________________________ LET var = .ADC( ) or ADC( ): Read selected ADC value ex: LET reading = .ADC(.VCCl(.ICCl)) PRINT .UNIT(n), . . . where n evaluates to -1; ex: PRINT .UNIT(P), `Passed IOH test` TMU: set Time Measurement Unit and read the TMU ex: TMU .TIMRNG(3nS,.DLYENA(Q(I))),.STOP (OUT:PINS(I)) CONVERT: Activate PMU broadcast CONVERT ALL strobe ex: CONVERT .PMUV(OUT:PINS) ENABLE: Enable selected board or circuit ex: ENABLE .VCCl, .PMU(OUT:PINS) DISABLE: Disable selected board or circuit ex: DISABLE .VCCl, .PMU(OUT:PINS) ______________________________________
______________________________________ LET .hdware( ) = constant values where ".hdware" is one of: .CPEDG: set compare edge delay generator on pin PWB .STEDG: set start edge delay generator on pin PWB .SPEDG: set stop edge delay generator on pin PWB .DRVL: set pin PWB `low` programming driver reference level .DRVH: set pin PWB `high` programming driver reference level .DRVP: set pin PWB PAL programming receiver reference level .RCVL: set pin PWB `low` programming receiver reference level .RCVH: set pin PWB `high` programming receiver reference level .IOL: set sourcing current for pin PWB .IOH: set sinking current for pin PWB .VTH: set programmable load threshold on pin PWB .PINFMT: set pin PWB format for drivers .PMUV: program voltage for Parametric Measurement Units .PMUI: program current for Parametric Measurement Units .RLY: set relays on pin PWB .HOTRLY: set relays on pin PWB when drivers, PMU or PLOAD are enabled .TPER: set system period generator period .VCC1: program voltage and current to VCC1 board .VCC2: program voltage and current to VCC2 board ex: LET .VCC1 = 1V, 500 mA LET .DRVL(IN:PINS) = 250 mV ______________________________________
LET.PMUV(PINS)=3.1V, 100UA
______________________________________ MOVE.L (A5),A1 Get address of turbo table ADDQ.L #6,A1 Point A1 to the number of entries MOVE.W (A1),D1 Load number of entries SUBI.W #1,D1 Subtract 1 for use as a loop counter ADDQ.L #2,(A1) Point A1 at beginning of array LOOP: MOVE.L (A1)+,A0 Get address of write MOVE.W (A1)+,(A0) Write value DBF D1,LOOP Branch until done ______________________________________
LET.PMUV(PINS)(I)=3.1V, 100uA
IF min .LT function .LT max
PRINT .UNIT(n), expression
Claims (11)
Priority Applications (1)
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US07/183,195 US4903199A (en) | 1988-04-19 | 1988-04-19 | Method of increasing the speed of test program execution for testing electrical characteristics of integrated circuits |
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US07/183,195 US4903199A (en) | 1988-04-19 | 1988-04-19 | Method of increasing the speed of test program execution for testing electrical characteristics of integrated circuits |
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Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0388077A2 (en) * | 1989-03-15 | 1990-09-19 | Texas Instruments Incorporated | Method of optimizing the execution speed of an interpreted test language |
US5150048A (en) * | 1990-09-12 | 1992-09-22 | Hewlett-Packard Company | General purpose, reconfigurable system for processing serial bit streams |
US5668947A (en) * | 1996-04-18 | 1997-09-16 | Allen-Bradley Company, Inc. | Microprocessor self-test apparatus and method |
US5928334A (en) * | 1997-03-28 | 1999-07-27 | International Business Machines Corporation | Hardware verification tool for multiprocessors |
US6091897A (en) * | 1996-01-29 | 2000-07-18 | Digital Equipment Corporation | Fast translation and execution of a computer program on a non-native architecture by use of background translator |
US20020170030A1 (en) * | 2001-05-09 | 2002-11-14 | Halcomb Herbert Wayne | Method and apparatus for emulating a processor |
US6618853B1 (en) * | 1998-10-10 | 2003-09-09 | Advantest Corporation | Program production system for semiconductor tester |
US20040044988A1 (en) * | 2002-08-29 | 2004-03-04 | Schene Christopher Robin | Generation of compiled code for simulator speed up |
US20090055803A1 (en) * | 2005-05-20 | 2009-02-26 | Advantest Corporation | Semiconductor test program debug device |
US9740601B2 (en) | 2015-12-01 | 2017-08-22 | International Business Machines Corporation | Globalization testing management service configuration |
US9767011B2 (en) | 2015-12-01 | 2017-09-19 | International Business Machines Corporation | Globalization testing management using a set of globalization testing operations |
US10157057B2 (en) | 2016-08-01 | 2018-12-18 | Syntel, Inc. | Method and apparatus of segment flow trace analysis |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4339819A (en) * | 1980-06-17 | 1982-07-13 | Zehntel, Inc. | Programmable sequence generator for in-circuit digital testing |
-
1988
- 1988-04-19 US US07/183,195 patent/US4903199A/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4339819A (en) * | 1980-06-17 | 1982-07-13 | Zehntel, Inc. | Programmable sequence generator for in-circuit digital testing |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0388077A3 (en) * | 1989-03-15 | 1993-10-13 | Texas Instruments Incorporated | Method of optimizing the execution speed of an interpreted test language |
EP0388077A2 (en) * | 1989-03-15 | 1990-09-19 | Texas Instruments Incorporated | Method of optimizing the execution speed of an interpreted test language |
US5150048A (en) * | 1990-09-12 | 1992-09-22 | Hewlett-Packard Company | General purpose, reconfigurable system for processing serial bit streams |
US6502237B1 (en) | 1996-01-29 | 2002-12-31 | Compaq Information Technologies Group, L.P. | Method and apparatus for performing binary translation method and apparatus for performing binary translation |
US6091897A (en) * | 1996-01-29 | 2000-07-18 | Digital Equipment Corporation | Fast translation and execution of a computer program on a non-native architecture by use of background translator |
US5668947A (en) * | 1996-04-18 | 1997-09-16 | Allen-Bradley Company, Inc. | Microprocessor self-test apparatus and method |
US5928334A (en) * | 1997-03-28 | 1999-07-27 | International Business Machines Corporation | Hardware verification tool for multiprocessors |
US6285974B1 (en) | 1997-03-28 | 2001-09-04 | International Business Machines Corporation | Hardware verification tool for multiprocessors |
US6618853B1 (en) * | 1998-10-10 | 2003-09-09 | Advantest Corporation | Program production system for semiconductor tester |
US20020170030A1 (en) * | 2001-05-09 | 2002-11-14 | Halcomb Herbert Wayne | Method and apparatus for emulating a processor |
US7072824B2 (en) * | 2001-05-09 | 2006-07-04 | Lucent Technologies Inc. | Method and apparatus for emulating a processor |
US20040044988A1 (en) * | 2002-08-29 | 2004-03-04 | Schene Christopher Robin | Generation of compiled code for simulator speed up |
US20090055803A1 (en) * | 2005-05-20 | 2009-02-26 | Advantest Corporation | Semiconductor test program debug device |
US8132161B2 (en) * | 2005-05-20 | 2012-03-06 | Advantest Corporation | Semiconductor test program debug device |
US9740601B2 (en) | 2015-12-01 | 2017-08-22 | International Business Machines Corporation | Globalization testing management service configuration |
US9767011B2 (en) | 2015-12-01 | 2017-09-19 | International Business Machines Corporation | Globalization testing management using a set of globalization testing operations |
US10157057B2 (en) | 2016-08-01 | 2018-12-18 | Syntel, Inc. | Method and apparatus of segment flow trace analysis |
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