JPH05297911A - Sequence control circuit for sequence controller - Google Patents

Abstract

PURPOSE:To obtain the sequence control circuit which can change the physical addresses of a sequence program after compilation. CONSTITUTION:This sequence control circuit has an address pointer group 4 for identifying the storage ranges of respective programs, a program counter which indicates a program place being executed, an address comparing circuit group 5 which compares them to identify the sequence program being executed, and a register file 6 stored with a coordinate table (address conversion table) wherein plural physical addresses and actual physical addresses are made to correspond to each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence control circuit for a sequence controller capable of changing the physical address of a sequence program after compilation.

[0002]

2. Description of the Related Art Conventionally, in a ladder diagram for describing the operation of a sequence controller, as a method of describing an address which is an object of the instruction, it is general to describe an actual physical address. However, this method has a drawback that the program description cannot be started unless the physical address is determined at the time of writing the program. Furthermore, when changing the physical address, it is necessary to search the entire ladder program and rewrite all the parts in which the physical address to be changed is described. In order to reduce this work, the method of describing the logical address and describing the correspondence table that associates the logical address with the physical address in one place on the ladder program is adopted, and the conversion from the physical address to the logical address is performed. In recent years, a sequence controller having a system structure in which a sequence program of an execution format obtained by compiling a ladder diagram and executed as a result of the compilation is loaded into an execution memory portion of the sequence controller has come to be seen. FIG. 2 shows a block of a sequence processing unit in a conventional example. In FIG. 2, reference numeral 1 is a sequence processing CPU, 2 is an execution format sequence program storage memory, 3 is a data memory for storing data, and the state of an input relay is captured in the memory 3 as data. It is divided into an input relay image section, an output relay image section in which data to be written in the output relay as a result of the sequence processing is stored, and an internal relay data section in which the state of the internal relay is stored as data. In the sequence processing, the sequence processing CPU 1 outputs an address, reads the program as data from the execution-type sequence program memory 2, outputs a physical address to the data memory 3 based on the content, and reads the relay state as data. After performing the sequence processing, the relay data is written in the data memory 3 in this order.

[0003]

However, in the conventional sequence controller, since the physical address is determined at the time of compilation, it is necessary to correct the ladder diagram and compile again when changing the physical address. . In view of the above problems, it is an object of the present invention to provide a sequence control circuit for a sequence controller that changes the physical address of a compiled sequence program.

[0004]

To achieve this object, a sequence control circuit according to the present invention includes an address pointer for identifying the storage range of each sequence program and a program counter indicating the location of the program currently being executed. And a comparison circuit for comparing these to identify the sequence program currently being executed, and a correspondence table (hereinafter referred to as address conversion table) that associates a plurality of logical addresses with actual physical addresses. It has a register file.

[0005]

According to the present invention, the addresses of the input / output relay unit and the internal relay unit can be changed to arbitrary addresses by the function of the address conversion table in the register file in executing the program after compilation. Furthermore, the address range in which the program counter and the address of the execution program are set and the address range of the execution program in which the change is executed can be set by the operation of the address comparator.

[0006]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block of a sequence processing section of a sequence control circuit in an embodiment of the present invention. In FIG. 1, reference numeral 1 is a sequence processing CPU, 2 is an execution-type sequence program storage memory, 3 is a data memory for storing data, and the state of an input relay is captured as data in the memory. It is divided into an input relay image part, an output relay image part in which data to be written in the output relay as a result of sequence processing is stored, and an internal relay data part in which the state of the internal relay is stored as data. An address pointer group 4 contains the start and end addresses of the executable format sequence program in each address pointer. Reference numeral 5 is an address comparison circuit group, and each comparison circuit compares the address held by the corresponding address pointer with the address output by the program counter of the sequence processing CPU 1 and uses the comparison result as a selection signal of the register file 6. Supply. The contents of the sequence processing will be described below. First, before starting the sequence processing, in the address pointer group 4,
Load the start and end addresses of each block of the sequence program. Data of the address conversion table used in the corresponding sequence program is loaded in each file of the register file 6 selected by the selection signal corresponding to the address pointer group and the address comparison circuit group 5. As a result, when the sequence program is executed, the address conversion table corresponding to the address being executed by the sequence program is automatically selected. The physical address can be changed by rewriting the contents of this address conversion table.

[0007]

As is apparent from the above-described embodiments, the present invention compares the address pointer for identifying the storage range of each program with the program counter indicating the location of the program currently being executed, and compares them with each other. By having a register file that contains a comparison circuit for identifying the sequence program being executed and a correspondence table (address conversion table) that associates multiple logical addresses with actual physical addresses, The sequence control circuit capable of changing the physical address can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a sequence processing unit of a sequence control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a sequence processing unit in a conventional example.

[Explanation of symbols]

1 ... Sequence processing CPU, 2 ... Execution format sequence program storage memory, 3 ... Data memory, 4 ... Address pointer group, 5 ... Address comparison circuit group, 6 ... Register file.

Claims (1)

[Claims] 1. A sequence control circuit for storing a plurality of sequence processing programs on a memory and executing the programs, an address pointer for identifying a storage range of each program, and a program counter indicating a location of a program currently being executed, Sequence controller having a comparison circuit for comparing these to identify the sequence program currently being executed, and a register file having a correspondence table (address conversion table) for associating a plurality of logical addresses with actual physical addresses Sequence control circuit.