GB2099618A

GB2099618A - Algorithmic word generator

Info

Publication number: GB2099618A
Application number: GB8210683A
Authority: GB
Original assignee: Tektronix Inc
Current assignee: Tektronix Inc
Priority date: 1981-06-02
Filing date: 1982-04-13
Publication date: 1982-12-08
Also published as: CA1189191A; GB2099618B; JPS57204955A; NL8202113A; DE3217024A1; FR2506973A1

Abstract

A microprogrammable word generation system for circuit simulation and stimulation is disclosed. A microcode memory 22 stores instructions consisting of command and address signals, and a vector memory 26 stores words. A control circuit 32, 34 provides address information from the microcode memory to the microcode and vector memories for generating the next instruction from the microcode memory and the word from the vector memory. An output counter 28 receives the word from the vector memory and acts selectively as a register or a counter for generating a word pattern, in response to a signal from control logic 32. The system is able to generate a large number of vectors using a short instruction sequence, by repetition using the output connector 28. <IMAGE>

Description

SPECIFICATION Algorithmic word generator Background of the invention The present invention relates to an algorithmic word generator which generates a logic word pattern for stimulating or simulating a digital circuit or system.

It is becoming a common practice to incorporate microprocessors into digital electronic apparatus to provide intelligent functions. For stimulating or simulating such apparatus, knowledge of emulators, editors, compilers or assemblers is required in general. Obtaining such knowledge, however, is troublesome and burdensome for digital designers, evaluators and manufacturing personnel.

It is known to utilize word generators which allow the user to stimulate and debug the digital apparatus by easily simulating logic blocks or bus structures. Known good hardware can be used to simulate defective or unavailable hardware in a manner which does not require the knowledge of the emulators, editors, compilers or assemblers.

The ability to simulate most bus structures provides a tool for system debugging which is otherwise unavailable.

A conventional word generator is shown in Fig.

1. Address counter 10 counts the clock signal from clock generator 12 to provide an address signal to memory circuit 14, such as a random access memory which receives the clock signal.

Control circuit 16 presets and resets counter 10, and controls the read/write mode of memory circuit 14. In the write mode, control circuit 16 writes predetermined words in memory circuit 14 in accordance with the address signal. In the read mode, the stored word in memory circuit 14 is read out in accordance with the address signal and applied through driver 18 to PUT (product under test).

For example, suppose the operator wants following 8 bit-words (hexadecimal): 01,02,03, 04,05, F7, C3, 08,09, 0A, OB, C2, C4, 08,09, OA, OB, and C9. The first word 01 (0000 0001) is stored in the address 0 of memory circuit 14, and the second word 02 (0000 0010) is stored in the address 1. The third through seventeenth words are stored in the addresses 2 through 17 of memory circuit 14 as shown in Fig. 2. In this drawing, the left-hand numbers indicate the addresses of memory circuit 14, and the righthand alphanumerics indicate the contents of the memory at the respective addresses.

As understood from the foregoing description, the conventional word generator is not suitable to generate a long vector consisting of many words, because it must store all of the words sequentially. It is cumbersome and tedious for the operator to set each word in the word generator.

Moreover, a large memory capacity is necessary for the long vector.

Summary of the invention According to the present invention, a micro programmable word generation system is provided. The present invention uses two highspeed memories, such as a microcode (first) memory and a vector (second) memory, and an output counter. The microcode memory contains instructions which are processed by a control logic circuit and are used to generate a number designated as a programming code (PC). The PC may be generated in an algorithmic manner using advance, jump, call and return instructions. This allows the vector memory to be addressed in the algorithmic manner. The vector memory stores the words as the components of the vector. Thus, a short instruction sequence may generate thousands of vectors.Since the vector memory outputs are passed through an output counter instead of a register, the counter allows one instruction to provide the vector and then increases it a predetermined number of times. In addition to the vector outputs, the word generator of the present invention may provide programmable strobe outputs which enables the PUT to simulate various bus structures.

It is therefore one object of the present invention to provide an algorithmic word generator which employs a microprogrammable technique.

It is another object to provide a word generator which has an easily understood instruction set suitable for stimulation and simulation of digital circuits and systems.

It is a further object to provide a word generator including microcode and vector memories and an output counter.

It is an additional object to provide a word generator which can generate thousands of vectors with a short instruction sequence.

It is another object to provide a word generator which does not need large memory capacity for generating a large number of vectors.

Other objects and advantages of the present invention will become apparent to those having ordinary skill in the art when taken in conjunction with the accompanying drawings.

Drawings Fig. 1 shows a block diagram of a conventional word generator; Fig. 2 shows a content of a memory circuit used in Fig. 1; Fig. 3 shows a simplified block diagram of the present invention; Fig. 4 shows a detailed block diagram of the present invention; Fig. 5 shows a program for explaining the operation of Fig. 4; Figs. 6A and 6B show contents of microcode and vector memories used in Fig. 4; Fig. 7 shows a circuit schematic of the microcode memory used in Fig. 4; Fig. 8 shows a circuit schematic of the vector memory and output counter used in Fig. 4; and Fig. 9 shows a circuit schematic of the "PC+1" circuit used in Fig. 4.

Detailed description of the invention Referring to Fig. 3, there is shown a simplified block diagram of the present invention. Control circuit 20 consisting of microcode memory section 22 and control section 24 applies the PC to vector memory 26, and the output from vector memory 26 is a parallel-bit signal to be applied to output counter 28. Control circuit 20 controls load/counting mode of output counter 28. Clock generator 12 applies the clock signal to control circuit 20, vector memory 26 and output counter 28 for synchronizing operations. The output from counter 28 is applied through driver 18 to a product under test.

If the desired word pattern is determined, instructions and words are stored in microcode memory 22 and vector memory 26 respectively using a conventional technique in accordance with the desired word pattern. The instructions stored in memory 22 are decoded to the PC and a control signal by control section 24. The PC is used as the address signal for memories 22 and 26. If the vector is not sequential numbers, control section 24 applies the load instruction as the control signal to output counter 28, and the word stored in the appointed address of memory 26 is loaded to counter 28. The loaded word is applied to driver 18.If the vector comprises sequential numbers, the word stored in the appointed address of vector memory 26 presets output counter 28, and control section 24 applies the counting instruction as the control signal to counter 28 for the predetermined period determined by the instruction in microcode memory 22. Counter 28 starts to count the clock signal from the preset number, and stops counting when the counting instruction ends.

Thus, the output from counter 28 is the sequential numbers, and is applied to driver 18. Since counter 28 generates the sequential vector (numbers) by counting the clock signal, long sequential words can be produced with only one instruction in microcode memory 22 and one start word in vector memory 26. Thus, the present invention can save the memory capacity.

When microcode memory 22 receives the PC as the address signal from control section 24, memory 22 applies the next instruction to control section 24. The next instruction is decoded and used in the same manner as the former instruction described hereinbefore. If the vector words include the same pattern consisting of a plurality of words at different times, a subroutine technique is available. This pattern is stored in the predetermined addresses of vector memory 26, and is called by the instruction in microcode memory 22. Moreover, the present invention can use a jump technique. Thus, the present invention can further save the memory capacity, and can generate a large number of vectors with a short instruction sequence.

The present invention will be further described in detail with reference to Fig. 4. The instruction (consisting of a plurality of bits) in microcode memory 22 is transferred to instruction register 30 which divides the instruction into the upper bits as the command signal and the lower bits as the address signal. The command signal is applied to control logic 32 which decodes it into many control signals, and the address signal is applied to instruction multiplexer 34 as a jump or call address. The output from multiplier 34 is the PC which is applied to program counter 36 and microcode memory 22. Counter 36 acts as a pipe line for synchronizing and adjusting the timing of the PC. The PC from counter 36 determines the address of vector memory 26 and is applied to "PC+ 1 " circuit 38 which produces the next address ("PC+1") of the present address (PC).

The output from circuit 38 is stored in stack memory 40. Instruction multiplexer 34 receives the output from "PC+1" circuit 38 as an advance address and the output from stack memory 40 as a return address. The word stored in vector memory 26 is applied to output counter 28 acting as the counter or register as described hereinbefore. The output from counter 28 is applied through driver 18 to the product under test. Control logic circuit 32 produces four control signals, namely, an input selection signal for instruction multiplexer 34, a stack control signal for stack memory 40, a load/counting control signal for output counter 28 and a strobe control signal for strobe circuit 42 in accordance with the instruction from register 30. Strobe circuit 42 generates a strobe signal to be applied to the product under test, and clock generator applies the clock signal to each block.Blocks 30 through 40 correspond to control section 24 of Fig. 3.

As described hereinbefore, microcode memory 22 stores the instruction and address information, and vector memory 26 stores the word information. This information is stored in a conventional manner, and the present invention uses conventional computer techniques such as subroutine, jump or the like. When the read out signal of microcode memory 22 includes the advance instruction, this instruction is applied through instruction register 30 to control logic circuit 32. On the other hand, "PC+ 1 " circuit 38 produces the advance address (the next address of the present address). Instruction multiplexer selects this advance address in response to the control signal from control logic circuit 32, and applies the output (PC) to vector memory 26 through program counter 36 and to microcode memory 22. The word in the advance address of vector memory 26 is applied to output counter 28 which acts as the register because it receives the load instruction from control logic circuit 32. The output from counter 28 is applied to driver 1 8. If the instruction in microcode memory 22 includes the counting command, control logic circuit 32 applies this command to output counter 28 so that it counts the predetermined number of the clock pulses determined by the instruction from microcode memory 22. In this instance, output counter 28 is preset by the word from vector memory 26 as described hereinbefore. Microcode memory 22 generates the next instruction in accordance with the PC from instruction multiplexer 34.

When the read out signal of microcode memory 22 includes a jump instruction and address signal, instruction register 30 applies the jump address and the jump instruction to instruction multiplexer 34 and control logic circuit 32 respectively. In accordance with the control signal from control logic circuit 32, instruction multiplexer 34 selects the jump address and applies it to vector memory 26 through program counter 36 and to microcode memory 22. The word in the jump address of vector memory 26 is applied to output counter 28 which receives the load instruction from control logic circuit 32. The output from counter 28 is applied to driver 18.

When microcode memory 22 receives the jump address, it may produce the next instruction stored in the address.

When the read out signal of microcode memory 22 includes the call instruction and address signal, instruction register 30 applies the call instruction and call address to control logic circuit 32 and instruction multiplexer 34 respectively. Multiplexer 34 selects the call address in response to the control signal from control logic circuit 32, and applies it to vector memory 26 through program counter 36 and to microcode memory 22. On the other hand, in accordance with the control signal from control logic circuit 32, stack memory 40 stores the next address of the present address because of "PC+ 1 " circuit 38. Microcode and vector memories 22 and 26 store the instructions and words as the subroutine at the addresses starting from the call address. The last instruction of the subroutine in microcode memory 22 is a return command.When control logic circuit 32 receives the return command via instruction register 30, instruction multiplexer 34 selects the return address stored in stack memory 40 which corresponds to the next address of the former address before the call operation. The return address is applied to microcode memory 22 and vector memory 26, and the normal operation restarts.

The operation of the present invention will be further described with reference to Figs. 5 and 6.

In this instance, the word generator of the present invention generates the following word pattern (8 bits, hexadecimal) as one example: 01, 02, 03, 04,05, F7, C3, 08,09, 0A, OB, C2, C4, 08,09, OA, OB, C9. It should be noted that this word pattern is the same as the pattern shown in Fig. 2.

Fig. 5 shows the program for the word pattern.

The first line "01 COUNT 05" means that output counter 28 counts from "01" to "05". The second line "F7" is the next vector, and third line "C3 CALL X" means that the subroutine "X" is called after the vector "C3". The fourth line "C2" is the next vector, and the fifth line "C4 CALL X" means that the subroutine 'X" is called after the vector "C4". The sixth line "C9 HALT" means that this word pattern ends after the vector "C9". The seventh line "X" means the subroutine, and "08" thereof is the first word of the subroutine. "09", "OA" and "OB" are the second through fourth words of the subroutine. "RETURN" means to return the next address of "CALL". As understood from Fig. 5, the present invention has an easily understood instruction.

Fig. 6A and 6B show the contents of microcode memory 22 and vector memory 26 respectively. The numbers outside the rectangles indicate the addresses of memories 22 and 26, and the alphanumerics inside the rectangles are the instructions and words stored in memories 22 and 26. These instructions and words are written in the memories in a conventional manner.

At the first time, the content "01" in the address 0 of vector memory 26 is loaded to output counter 28, and the counting instruction (until 5) in the address 0 of microcode memory 22 is applied to control logic circuit 32. Counter 28 counts from 01 to 05 in accordance with this instruction. After the count operation, instruction multiplexer 34 selects the advance address "1" from "PC+ 1 " circuit 38. (In this instance, the PC is 0 and PC+ 1=1.) The word "F7" in the address 1 of vector memory 26 is loaded to output counter 28, and microcode memory 22 generates the advance instruction from the address 1.

Instruction multiplexer 34 selects the output (2) from "PC+ 1 " circuit 38, and the PC (2) is applied to vector memory 26 and microcode memory 22.

The word "C3" in the address 2 of vector memory 26 is loaded to output counter 28. Microcode memory 22 generates the call instruction and address X from the address 2. Stack memory 40 stores 3 (2+1) from "PC+1 " circuit 38, and instruction multiplexer 34 selects the call address (X). The word "08" in address X of vector memory 26 is loaded into output counter 28, and microcode memory 22 generates the advance instruction. "PC+1" circuit 38 generates "X+ 1", and instruction multiplexer 34 selects the advance address (X+1). Similar operations are repeated.

When instruction multiplexer 34 generates the advance address (X+3), the word "OB" in the address X+3 of vector memory 26 is loaded into output counter 28, and microcode memory 22 produces the return instruction. Instruction multiplexer 34 selects the output from stack memory 40, and generates the address "3" as the PC. The word "C2" in address 3 of vector memory 26 is loaded to output counter 28, and the advance instruction is produced from the address 3 of microcode memory 22. Similar operations are repeated, and then the predetermined word pattern "01, 02,03, 04, 05, F7, C3, 08, 09, OA, OB, C2, C4, 08, 09, OA, OB, C9" would be obtained. As can be understood by those skilled in the art, the counting, jump, call and advance instructions are very useful for generating large numbers of vectors with a short instruction sequence.It should be noted that strobe circuit 42 generates the strobe signal for each word.

Fig. 7 shows a circuit schematic of microcode memory 22 used in Fig. 4. There are two microcode memory sections 44 and 46 each including address decoder 48 and memories 50.

Memory section 44 is for the 5-bit-parallel instruction, and memory section 46 is for the 8bit-parallel instruction. These sections 44 and 46 may be combinations of many IC's such as type 1044. The address signal (PC) from instruction multiplexer 34 is loaded into registers 52 and 54 such as type 10176 and 10131. The PC from registers 52 and 54 is applied to terminals AO through A7 of address decoders 48. In the read mode, write enable terminals WE of sections 44 and 46 receive "High" from a microprocessor system (#P, not shown in Fig. 4), and the data stored in the appointed address of memories 50 are applied from terminals DO to instruction register 30.In the write mode, write enable terminals WE of memory sections 44 and 46 are "Low", and the predetermined data are applied to terminal DIN of memories 50 from ,uP in accordance with the program such as Fig. 5.

Fig#. 8 shows a circuit schematic of vector memory 26 and output counter 28 used in Fig. 4.

Vector memory 26 consists of memory sections 56 and 58 each including address decoder 48 and memories 50 similarly to Fig. 7. Write enable terminals WE of memory sections 56 and 58 are same as memory sections 44 and 46 of Fig. 7. In the write mode, #P (not shown) applies the predetermined data to terminals DIN of memories 50 in accordance with the address signal. In the read mode, terminal AO through A7 of address decoders 48 receive the address signal (PC) from programmable counter 36, and the stored data are applied from terminals DO of memories 50 to terminals DO through D3 of output counter 28 consisting of four counters 60 through 66. Load terminals of counters 60 through 66 receive the load/counting control signal from control logic circuit 32.When the control signal is "Low", the counters are in the load mode. When the control signal is "High", the counters are in the counting mode. The outputs from terminals Q0 through Q3 are applied to driver 18. The clock signal is applied to the clock terminal of the counters from clock generator 12.

The counters 60 through 66 may be IC's such as type 10136.

Fig. 9 shows a circuit schematic of "PC+1" circuit 38 used in Fig. 4. The PC from program counter 36 is applied to terminals DO through D3 of arithmetic logic units 68 and 70, such as type 10181 IC, and is incremented by one. Units 68 and 70 add 0000 (binary) to the PC, but the carry is activated. The outputs from units 68 and 70 are clocked through registers 72 and 74 such as type 10131 and 10176 IC's. The outputs from registers 72 and 74 are used by the advance address to increase the value of program counter 36 by one, and are applied to stack memory 40.

While I have shown and described herein the preferred embodiment of my invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from my invention in its broader aspects. For example, control logic circuit 32 may be included in the microprocessor system comprising a microprocessor, a read only memory for firmware, a random access memory as a temporary memory, and a keyboard as an input device. The contents of microcode memory 22 and vector memory 26 may be written with this microprocessor system. In the preferred embodiment, output counter 28 acts as both the register and the increment counter. However, counter 28 may act as both the register and a decrement counter or both the register and an updown counter. The instructions stored in microcode memory 22 further include repeat and hold instructions. According to the repeat instruction, the words stored in the predetermined addresses of vector memory 26 are read repeatedly the predetermined times. According to the hold instruction, the output word is held.

Claims

1. An algorithmic word generator, comprising; first memory means for storing instructions; second memory means for storing words; and control means for generating address information for said first and second memory means in accordance with an instruction from said first memory means; wherein said first and second memory means generate a next instruction and a word respectively in accordance with the address information.

2. A word generator according to claim 1 further including logic means receiving a word from said second memory means, said logic means selectively operable as one of a register and a counter in accordance with a control signal from said control means.

3. A word generator according to claim 2, wherein said control signal from said control means is provided in accordance with an instruction from said first memory means.

4. A word generator according to claim 2, wherein said logic means acts as one of an increment, decrement and up-down counter when said logic means receives a control signal so as to operate as the counter.

5. A word generator according to claim 1, wherein said control means comprises; an instruction register for dividing the output from said first memory means into command and address signals; a multiplexer to receive said address signal from said first memory means; adding means for adding one to the output from said multiplexer and applying the output to said multiplexer; a stack memory for storing the output from said adding means and applying the output to said multiplexer; and control logic means for decoding said command signal into control signals for said multiplexer and said stack memory; wherein the output from said multiplexer is further applied to said first and second memory means.

6. A word generator according to claim 5, wherein said control logic means is a microprocessor system.

7. A word generator according to claim 1 further including a strobe circuit for generating a strobe signal in accordance with a control signal from said control means.

8. A word generator according to claim 1 further including writing means for writing the instructions and words in said first and second memory means.

9. An algorithmic word generator, comprising; a microcode memory for storing instructions consisting of command and address signals; a vector memory for storing words; an output counter receiving the output from said vector memory and acting as one of a register and a counter in accordance with a selectable operating mode; and a control circuit receiving the output from microcode memory and applying address information and a control signal to said microcode and vector memories and said output counter, respectively; wherein said microcode and vector memories provide the next instruction and the word respectively, and said control signal from said control circuit selects said operating mode.

1 0. An algorithmic word generator substantially as hereinbefore described witn reference to and as illustrated in the accompanying drawings.