NL8202113A - ALGORITHMIC WORD GENERATOR. - Google Patents

Description

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Short designation: Algorithmic word generator

The invention relates to an algorithmic word generator which generates a logical word pattern for stimulating or simulating a digital chain or digital system.

It has become common practice to incorporate microprocessors in order to provide intelligent functions in digital electronic equipment. In general, stimulation or simulation of such devices requires knowledge of emulator, editing, translation or assembling programs. However, obtaining such knowledge is difficult and presents problems for digital designers, developers and production personnel.

It is known in practice to use word generators that allow the user to simulate and debug digital equipment by simply simulating logical blocks or bus structures. Hardware known per se can be used to simulate defective or unavailable hardware such that no knowledge of the emulator, editing, translation or assembly programs is required. The possibility of simulating most bus structures provides a vehicle for debugging a system that is not otherwise available.

The word generators known in practice are not suitable for generating a long vector consisting of many words, because it has to store all words successively. It is difficult and extremely annoying for the operator to place every word in the word generator. In addition, a long vector requires greater memory capacity.

The object of the invention is to eliminate the drawbacks of the known hardware and to that end provide a microprogrammable word generator system. The system includes two very fast-acting memories, such as a (first) micro-code memory and a (second) vector memory and an output counter. The microcode memory contains instructions which are processed by a logic control circuit and which are used to generate a number indicated as programming code (PC). The PC can be generated algorithmically using progress, jump, call and return instructions. As a result, the vector memory can be addressed in the algo- 8202113 ♦ i -2 rhythmic manner. The vector memory stores the words as components of the vector. Thus, a short instruction set can generate thousands of vector torea. Because the challenge area of the vector memory is increased with a challenge counter, rather than with a register, the counter can construct the vector latea provider and the predetermined number of malea allowance. In addition to the vector outgrowth signal, the word generator according to the invention can be programmed with strohe-outgrowth signal liverea, which allows the oader test side product (PUT) to simulate various structures.

The invention day therefore aims to provide an algorithmic word generator which uses microprogrammable technology.

The present invention aims to provide a word generator which has an easy to understand instruction set suitable for the stimulerea ea simulerea va digit ale keteas ea systemea.

Furthermore, a word generator is provided including the microcode, etc., vector memory axis, etc., a challenge marker.

The inventive day provides a word generator with which deaeadea vectorea with a short sequence series aerated kuaaea wordea.

Boveadia is provided with a word generator that does not require large memory capacity for the genera of many large vectors.

The invention day is explained to the haad vaa of the drawing layer. In the teiag shows:

Pig. 1 a block diagram of a word generator known from practice; Fig. 2 shows a form of the contents of a memory chain of the generator shown in Fig. 1; Fig. 3 is a simplified block diagram of the generator according to the invention; Fig. a detailed block diagram of a generator according to the invention; Fig. 5 a program for explaining the operation of the diagram next axis fig. K; FIGS. βΑ and βΒ are content forms of the microcode and vector memories shown in FIG. 1; FIG. 7 is an electrical schematic of the memory code array shown in FIG. U; FIG. 8 is an electrical schematic of the vector memory and others of the trip counter shown in FIG. k; and 8202113 * 1 * * -3- FIG. 9 is an electrical schematic of the "PC + 1" circuit shown in FIG. U.

Of the word generator shown in FIG. 1 and seen in practice, an address counter 10 counts the clock signal from Tran and a clock generator 12 before supplying Tran with an address signal to a memory circuit 1, such as a random access memory, which also disrupts the clock signal.

The control circuit 16 provides a preset and reset of the counter 10 and controls the read / write mode of the memory circuit 1U. In the write mode, the control circuit 16 writes predetermined words into the memory circuit 11 in accordance with the address signal. In the read mode, the stored word is read from the memory circuit 14 in accordance with the address signal and passed through the drive circuit 18 to the product to be tested (PUT).

For example, suppose the operator wants the following eight bit words (hexa-decimal): 0, 1, 02 »03, 0 ^ -, 05, FT, C3, 08, 09, 0A, 0B, C2, Cif, 08, 15 09, 0A, 0b and C9 · The first word 01 (0000 0001) is stored in the location of the memory chain 1U with the address 0 · and the second word 02 (0000 0010) is stored in the address 1, The third t / The seventeenth words, as shown in Fig. 2, are stored in the locations with addresses 2 to 17 of the memory circuit 1U. In Fig. 2, the numerals 20 on the left represent the addresses of the memory chain 1¾ and the alphanumeric numbers or wagons on the right represent the resp. addresses for memory contents.

From the foregoing, it follows that the known word generator is not suitable for generating a long vector with many words, because it has to store all 25 words consecutively. It is difficult and tedious for the operator to put every word in the word generator. In addition, long vectors require a large memory capacity.

Fig. 3 shows a simplified block diagram of a word generator according to the invention. A control circuit 20 comprising a microcode-30 memory portion 22 and a control portion 2b supplies the PC to the vector memory 26, the output of which is a parallel bit signal which is fed to an output counter 28. The control circuit 20 controls the load / count mode of the output counter 28. A clock generator 12 supplies a clock signal to the control circuit 20 the vector memory 26 and to the output counter 28 to synchronize the operations. The output of the counter 28 is fed via a drive circuit 18 to a product to be tested.

If the desired word pattern has been determined, the instructions 8202113 f »* r -k- and words are stored in the microcode memory 22 resp. in the vector memory 26 using techniques known per se in accordance with the desired word pattern. The instructions stored in memory 22 are decoded in the PC and a control signal by the control part 2k. The PC is used as the address signal for the memory 22 and 26. If the vector does not contain consecutive numbers, the control part 2b supplies the loading instructions as the control signal to the output counter 28 and is stored at the designated address of the memory 26 word loaded into counter 28. The loaded word is fed to the drive circuit 18. If the vector comprises consecutive numbers, the word stored at the designated address of the vector memory 26 gives a preset of the output counter 28 and the control part 2k carries the counting instruction as the control signal to the counter 28 for a predetermined period determined by the instruction in the microcode memory 22. The counter 28 starts counting the pulses of the clock signal from the preset number and stops counting when the counting instruction ends. It. The output of the counter 28 is thus formed by the consecutive numbers and is fed to the drive circuit 18. Because counter 28 generates the sequential vector (numbers) by counting the clock signal, long sequential words can be supplied with a single instruction in the microcode memory 22 and a start word in the vector memory 26. In the generator of the invention thus memory capacity is saved.

When the microcode memory 22 receives the PC as the address signal from the control part 2k, the memory 22 supplies the following instruction to the control part 2k. The next instruction is decoded and processed in the same manner as the previous instruction described above. If the vector words comprise the same pattern consisting of a number of words at different times, a subroutine technique is available. This pattern is stored in the predetermined addresses of the vector memory 26 and is recalled by the instruction in the microcode memory 22. In addition, according to the invention a jumping technique can be applied. Thus, further savings can be made on the memory capacity and a large number of vectors can be generated with a short instruction series.

The generator according to the invention will be further elucidated with reference to fig. The multi-bit instruction 8202113 '* m * - -5-' in the micro-code memory 22 is transferred to the instruction register 30, which divides the instruction into the highest bits as the command signal and the lowest bits as the address signal . The ammo signal is fed to the control logic 32, which decodes it into many control 5 signals, while the address signal is fed as a jump or call signal to an instruction multiplexer 3¾. The output signal of the multiplexer 3¼ forms the PC, which goes to the program counter 36 and fed to the miero code memory 22. Counter 36 acts as a pipeline for synchronizing and adjusting the temper of the PC. The PC from the counter 36 determines the address of the vector memory 26-and is fed to the "PC + 1" circuit 38, which provides the next address ("PC + 1") of the current address (PC). The output of the circuit 38 is stored in a stack memory Uo. The instruction multiplexer 3 ^ receives the output signal from the "PC + 1" circuit 38 as a progress signal and the output signal from the stack memory ^ 0 as a return address. The word stored in the vector memory 26. is passed to the output counter 28, which functions as the previously described counter or register. The output of the counter 28 is fed to the product to be tested via a driving circuit 18. The logic control circuit 32 provides four control signals, namely an input select signal for the instruction multiplexer 3 ^, a stack control signal for the stack memory ^ 0, a load / count control signal for the output counter 28, and a strobe control signal for the strobe circuit k2 in correspondence. with the instruction from the register 30. The strobe circuit k2 generates a strobe signal to be fed to the product to be tested, and the clock generator carries the clock signal to each block. The blocks 30 to 0 correspond to the control part 2k of Fig. 3.

As explained above, the microcode memory 22 handles the storage of the instruction and address information and the vector memory 26 handles the storage of the word information. This information is stored in a manner known per se and according to the invention known computer techniques are used such as subroutines and jumps. If the signal read from the microcode memory 22 includes the progress instruction, this instruction is passed through the instruction register 30 to the logic control circuit 32. On the other hand, the "PC + 1" circuit 38 provides the progress 35 address (the address following the current address). The instructional multiplexer selects this progress address in response to the control signal from the logic control circuit 32 and feeds the output signal (PC) to 8202113 * * -6- «with the vector memory 26 through the program counter 36 and to the microcode memory 22. The word in the progress address from the vector memory 26 is fed to the output counter 28 which functions as the register because it receives the loading instruction from the logic control circuit 32.

The output signal from the counter 28 is fed to the drive circuit 18. If the instruction in the microcode memory 22 includes the counting command, the logic control circuit 32 outputs this command to the output counter 28 so that it has the predetermined number of clock pulses determined by the instruction from the microcode memory 22. At this time, the output counter 28 is the manner described above preset by the word from the vector memory 26. The microcode memory 22 generates the following instruction in accordance with the PC from the instruction multiplexer 3 ^.

When the signal read from the microcode memory 22 includes a jump instruction and address signal, the instruction register 30 feeds the jump address and the jump instruction to the instruction multiplexer 3, resp. to the logic control circuit 32. In accordance with the control signal from the logic control circuit 32, the instruction multiplexer 3 ^ selects the jump address and passes it to the vector memory 26 through the program counter 36 and to the microcode memory 22. The word in the jump address of the vector memory 26 is fed to the output counter 28, which receives the load instruction from the logic control circuit 32. The output of the counter 28 is fed to the drive circuit 18. When the microcode memory 22 receives the jump address, it can issue the next instruction stored in the address.

When the signal read from the microcode memory 22 includes the call instruction and the address signal, the instruction register 30 carries the call instruction and the call address to the logic control circuit 32, respectively. to the instructional multiplexer 3 ^. The multiplexer 3 ^ selects the call-30 address in response to the control signal from the logic control circuit 32 and feeds it to the vector memory 26 via the program counter 36 and to the micro-code memory 22. On the other hand, the stack 20 stores in accordance with the control signal. from the logic control circuit 32, the next address of the current address at 35 due to the presence of the "PC + 1" circuit 38. The microcode and vector memories 22 and 26 provide storage of the instructions and the words as the subroutine at the address starting from the call address. The last instruction of the subroutine in the microcode memory 22 is a return command. When the logic control circuit 32 receives the return command via the instruction register 30, the instruction multiplexer 3 selects the return address stored in the stack U0 corresponding to the next address of the previous address prior to the call operation. The return address is fed to the microcode memory 22 and the vector memory 26 and normal operation restarts.

The operation of the generator will be further explained in detail on the band of FIGS. 5 and 6. The word generator thereby generates, for example, the following word pattern (8 bits hexadecimal): 01, 02, 03 »0 ^ -, 05, F7, C3, 08, 09, 0A, 0B, C2, 0 ^, 08, 09, 0Α» 0B, C9. It is noted that this word pattern is similar to the pattern shown in Fig. 2. Fig. 5 shows the program for the word pattern. The first line "01 COUNT 05" means that the output counter 28 counts from "01" to "05". The second line "FT" is the next vector, and the third line "C3 CALL X" means that the subroutine "X" is called after the vector "C3". The fourth line "C2" is the next vector and the five fth line "cU CALL X" means that the subroutine "X" is called after the vector "CV. The sixth line" C9 HALT "means that this word pattern ends after the vector" C9 ". The seventh line 20" X "means that the subroutine and "08" thereof is the first word of the subroutine. "09", "0A" and "0B" are the second to fourth words of the subroutine. "RETURN" means return to the next address of "CALL". FIG. 5 shows that according to the invention, an easy-to-understand instruction is obtained.

FIG. 6A and 6b show the contents of the microcode memory 22, respectively. the vector memory 26. The numbers at the right angles indicate the addresses of the memories 22 and 26 and the alphanumeric values within the law books represent the instructions and words stored in the memories 22 and 26. These instructions and words are written in the memory in known manner.

First, the content "01" in the address 0 of the vector memory 26 is fed to the output counter 28 and the counting instruction (through 5) in the address 0 of the microcode memory 22 is fed to the logic control circuit 32. The counter 28 counts in accordance with this instruction 35 from 01 to 05. After the counting operation, the instruction multiplexer 3 chooses the progress address "1" from the "PC + 1" circuit 38. At this time, the PC is 0 and PC + 1 is 1. The word "F7" in the address 1 of the vector memory 26 8202113

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-8- is fed to the output 28 and the microcode memory 22 supplies the progress instruction from the address 1. The instruction multiplexer 3b selects the output (2) from the "PC + 1" circuit 38 and the PC (2) is sent to the vector memory 26 and the microcode memory 22. The word "C3" 5 in the address 2 of the vector memory 26 is fed to the output 28. The microcode memory 22 generates the call instruction in the address X from the address 2. The stack 20 stores 3 (2 + 1) from the "PC + 1" circuit 38 and the instruction multiplexer 3 ^ selects the call address (X). The word "08" in address X of the vector memory 26 is loaded into the output 28 and the microcode memory 22 generates the progress instruction The "PC + 1" circuit 38 generates "X + 1" and the instruction multiplexer 3 ^ selects the progress address (X + 1). Similar operations are repeated.

When the instruction multiplexer 3 ^ generates the progress address (X + 3), the word "08" in the address X + 3 of the vector memory 26 is loaded into the output 28 and the microcode memory 22 provides the return instruction. The instruction multiplexer 3 chooses the output from the stack memory ^ 0 and outputs the address "3" as the PC. The word "C2" in address 3 of the vector memory 26 is loaded into the output 28 and the progress instruction is supplied from the address 3 of the microcode memory 22. Similar operations are repeated so that the predetermined word pattern becomes "01, 02, 03, 0U, 05, FT, C3, 08, 09, 0A, OB, C2, Cl, 08, 09, 0A, 0B, C9" obtained. It will be understood that the count, jump, call and progress instructions are very useful for generating large numbers of vectors with a short instruction sequence. It is noted that the strobe circuit k2 generates the strobe signal for each word.

Fig. T shows an electrical diagram of the microcode memory 22 shown in Fig. B. There are two microcode memory parts bb and b6 each comprising an address decoder U8 and memories 50. The memory part kb serves for the 5-bit parallel instruction and the memory part b6 serves for the 8-bit parallel instruction. These parts and b6 can be formed by combinations of a number of integrated chains such as the IC with type designation 10UU. The address signal (PC) from the instruction multiplexer 3 ^ is loaded into registers 52 and 5 ^ as of the type 101, 6 and 10131. The PC from registers 52 and 5 ^ - is fed to terminals A0 to AT of the address decoders U8. In the read mode, write allow terminals WE of the parts and b6 receive a "high" signal from a microprocessor system not shown in FIG. B 8202 and the data stored in the designated address of the memories 50 is the terminals D ^ are fed to the instruction register 30. In the write mode, the write enable terminals WE of the song parts kh and k6 receive a "low" signal and the predetermined data is fed to the terminals of the memories 50 from the microprocessor in accordance with a program as shown in FIG.

Fig. 8 shows an electrical diagram of the vector memory 26 shown in FIG. K and of the output counter 28. The vector memory 26 consists of the memory parts 56 and 58 each including an address decoder U8 and a memory 50 similar to those in FIG. 7. The write approval terminals WE of the memory parts 56 and 58 are the same as those of the memory parts kk and k6 of FIG. 7. In the write mode, the microprocessor set (not shown) feeds predetermined data to the terminal of the memories 50 in 15. accordance with the address signal. In the read mode, terminals A0 to A7 of the address decoders 1) 8 receive the address signal (PC) from the programming counter 36 and the stored data are transferred from the terminals D ^ of the memories 50 to the terminals DQ to D ^ from the output counter 28, which consists of four counters 60 to 66. The load terminals ID of the 20 counters 60 to 66 receive the load / count control signal from the logic control circuit 32. When the control signal "low the counters are in the charging mode. When the control signal is "high", the counters are in counting mode. The output signals from terminals Q0 to Q3 are fed to the drive circuit 18. The clock signal 25 is fed from the clock generator 12 to the clock terminal of the counter. The counters 60 to 66 may be integrated circuits of the type with the type designation 10136.

Fig. 9 shows an electrical diagram of the circuit shown in FIG. 1). shown "PC + 1" circuit 38. The PC from program counter 36 is fed to terminals DO through 30 D3 of arithmetic logic units 68 and 70, such as of type 10181, and is incremented. Units 68 and 70 count 0000 (binary) at the PC, but the transport output is enabled. The outputs of units 68 and 70 are clocked by registers 72 and 71 as of type 10131 and 10176. The output signals from registers 72 and 735 are used by the progress address for increasing the value of program counter 36, and are fed to stack memory 1) -0.

8202113 -10-

The logic control circuit 32 may form part of a microprocessor system comprising a microprocessor, a readable memory for "hard" stored software, and a keyboard as an input unit. The contents of the microcode memory 22 and of the vector memory 26 can be measured with. this microprocessor system is written. In a preferred embodiment. the output counter 28 performs both the function of register and of incrementally increasing counter. However, counter 28 can also perform the function of the register and of a step-countdown counter or simultaneously as a register and up-counter. The instructions stored in the microcode memory 22 may further include repeat and hold instructions. According to the repeat instruction, the words stored in the predetermined addresses of the vector memory 26 are repeatedly read the predetermined circuit. In the holding instruction, the output word is held.

8202113

Claims (6)

1. An algorithmic word generator characterized by first memory means for storing instructions, second memory means for storing words, and control means for generating address information for the first and second memory means in accordance with an instruction from the first memory means, wherein the first and the second memory means a subsequent instruction and resp. generate a word in accordance with the address information. 2. Word generator according to claim 1, characterized by logic means which receive a word from the second memory means and which selectively act as register and counter in accordance with a control signal from the control means. Word generator according to claim 2, characterized in that the control signal from the control means is provided in accordance with an instruction from the first memory means. k. Word generator according to claim 2, characterized in that the logic means function as step-by-step addition, step-by-step count-down or up-counter when the logic means receive a control signal for functioning as the counter. Word generator according to claim 1, characterized in that the control means consist of an instruction register for dividing the output signal of the first memory means into command and address signals, a multiplexer for receiving the address signal from the first memory means, addition means for adding up 25 of a unit at the output of the multiplexer and feeding the output signal to the multiplexer, a stack memory for storing the output signal from the adding means and for feeding the output signal to the multiplexer, and logic control means for decoding the command signal in control signals 30 for the multiplexer and the stack memory, the output signal from the multiplexer also being fed to the first and second memory means. Word generator according to claim 5, characterized in that the logic control means are formed by a microprocessor system. The word generator according to claim 1, characterized by an 8202113. . Strobe circuit for generating a strobe signal in accordance with a control signal from the control means. Word generator according to claim 1, characterized by writing means for writing the instructions and words in the first and second mixing means. ' 9. Algorithmic word generator characterized by a microcode memory for storing the instructions consisting of command and address signals, a vector memory for storing words, an output counter which receives the output signal from the vector memory and functions as a register or counter in accordance with a selectable processing mode, and a control circuit which receives the output of the microcode memory and address information and a control signal, respectively. to the microcode and vector memories and the output counter, the microcode and vector memories resp. supply the following instruction and the word 15 and the control signal from the control circuit selects the processing mode. 8202113