CA1189191A - Algorithmic word generator - Google Patents
Algorithmic word generatorInfo
- Publication number
- CA1189191A CA1189191A CA000404005A CA404005A CA1189191A CA 1189191 A CA1189191 A CA 1189191A CA 000404005 A CA000404005 A CA 000404005A CA 404005 A CA404005 A CA 404005A CA 1189191 A CA1189191 A CA 1189191A
- Authority
- CA
- Canada
- Prior art keywords
- memory
- instruction
- response
- address
- control logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
- G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/03—Digital function generators working, at least partly, by table look-up
- G06F1/035—Reduction of table size
Abstract
Abstract A microprogrammable word generation system for circuit simulation and stimulation is disclosed. A
microcode memory stores instructions consisting of com-mand and address signals and a vector memory stores words. A control circuit provides address information from the microcode memory to the microcode and vector memories for generating the next instruction by the microcode memory and the word by the vector memory. An output counter receives the word from the vector mem-ory and acts as a register or a counter for generating a word pattern.
microcode memory stores instructions consisting of com-mand and address signals and a vector memory stores words. A control circuit provides address information from the microcode memory to the microcode and vector memories for generating the next instruction by the microcode memory and the word by the vector memory. An output counter receives the word from the vector mem-ory and acts as a register or a counter for generating a word pattern.
Description
AL,GC)RITHMIC WORn GENERATOR
Backgrourld of the Invention The present invention relates to an algorithmic word generator which generates a logic word pattern for stimulating or simulating a digital circuit or systern.
It is becoming a common pract:ice to incorporate microprocessors .nto digital elecl-ronic apparatus to provide intelligen~ functions. For stimulating or simulating such apparatus/ knowledge of emulators editors compilers or assemblers is required in general~ Obtaining such knowledge~ however, is troub:Lesome and burdensome for digital designers~ evaluators and manufactu.ri.ng personnel.
It is known to utilize word generators which allow the user to stimulate and debug the digital apparatus by easily simulating logic blocks or bus structures~ Known good hardware can be used to simulate defective or unavailable hardware in a manner which does not require the knowledge of the emulators, editors, compilers or a~semblers. The ability to simulate most bus structures provides a tool for system debugging which is otherwise unavailable.
A prior art word generator will be described hereinbelow.
In accordance with an aspect of the invention there is provided a digital ~ord generating apparatus for providing a selectable sequence of digital output words for use in the testing of a product, said apparatus comprising a microcode memory means having a plurality of addressable memory locations for retaining a preselected sequence of microprogram words containing instruction and address information and for providing the contents of one of said addressable memory locations to a microcode memory output bus in response to programming code signals; an instruction regl.ster means for storing the contents of said microcode memory output bus and for dividing the stored microcode word into cornrnand and address signals;
control logic means coupled to the instruction register - la --means for generating control logic signa:Ls in resp~nse to the command signals of said instruction register;
instruction multiplexer means for providing the programming code signals in response to the address signal of said instruction register, said contro:l logic signals, a return signal, and an advance signal; program counter means coupled to said instruction multiplexer means for retaining the microcode memory address last provided by the programming code signals; advance counter means coupled to said program counter means and said instruction multiplexer means for providing sa.id advance signal in response to the contents of said program counter means;
stack means coupled to said advance counter means and instruction multiplexer means for storing the contents o~
said advance counter means in response to control logic signals indicative that a subroutine call instruction is in said instruction register means and for thereafter providing said return signal in response to the oontents stored therein; vector memory means coupled to said program counter means for having stored therein vector words corr sponding to said programming code signals and for providing a vector memory output signal in response thereto; output counter means coupled to said vector memory means and said control logic means for providing said digital out:put words in response to the contents of said vector memory means and said control logic signals~
According to one embodiment of the present invention, a microprogrammable word generation system is provided~
The present invention uses two high-speed memories, such as a microcode (first) memory and a vector (second) memory, and an output counter. The microcode memory contains instructions which are processed by a control logic circuit and are used to generate a number designated as a programming code (PC). The PC may be yenerated in an aLgorithmic manner using advance, ~lump, call and return instructions. This allows the vector memory to be addressed in the algorithmic manner. The vector memory stores the words as the components of the vector. Thus, a short instruction sequence may generate thousands of vectors~ Since ~he vector memory outputs are passed through an output counter instead of a register, the counter allows one instruction ~o provide the vector and then increases it a predetermined number of times. In addition to the vector outputs~ the word generator of the present invention may provide programmable s~robe outputs which enables the ~UT to simulate various bus structures~
It is therefore one object of the present invention to provide an algorithmic word generator which employs a microprogrammable technique.
It is another object to pro~ide a word generator which has an easily understood instruction set suitable for stimulation and simulation of digital circuits and systems.
It is a further object to provide a word generator including micrococle and vector memories and an output counter.
It is an additional object to provide a word generator which can generate thousands of vectors with a short instruction sequence.
It is another object to provide a word generator which does not need :Large memory capacity for generating a large number of vectors~
Other objects and advantages of the present invention will become apparent to those having ordinary skill in the art when taken in conjunction with the accompanying drawings.
.~.`
L~
~ 3 --Drawinqs FIG. 1 shows a block diagram of a conventional word generator;
FIG. 2 shows a content of a memory circuit used in FIG. l;
FIG. 3 shows a simplified block diagram of the present invention;
FIG. 4 shows a detailed block sli.agram of the present invention;
FIG. 5 shows a program for explaining the operation of FIG. 4;
~IGs~ ~A and 6B show contents of microcode and vector memories used in FIG~ 4;
Fig. 7 shows a circuit schematic of ~.he microcode memory used in FIG. 4;
FIG. 8 shows a circuit schematic of ~he vector memory and output counter used in FIG. 4; and FIG. 9 ~appearing on the same sheet of drawings as FIG. 5) shows a circuit schematic of the '1PC + 1" circuit used in FIG. 4.
Detailed Description of the Invention A conventional word generator is shown in FIG. 1.
Address counter 10 counts the clock signal from clock generator 12 to p~rovide an address signal to memc3ry circuit 14, such as a random access memory which receives the clock signalO Control circuit 16 presets and resets counter 10, and controls the read/write mode of memory circuit 14. In the wrlte mode, control circuit 16 writes predetermined words in memory circuit 14 in accordance with the address signal~ In the read mode, the stored word in memory circuit 14 is read out in accordance with the address signal and applied throuyh driver 18 to PUT
(product under test).
For example, suppose the operator wants following 8 bit-words ~hexadecimal): 01, 02, 03, 04, 05, F7, C3, 08, 09, OA, OB, C2, C4, 08, 09, OA, OB, and C9. The f irst ~1;
.
3~
4 _ i word 01 ~0000 0001) is stored in the address 0 of mernory circuit 14, and the second word 02 (0000 OOln) ls stored in the address lo The third through eighteen~ words are stored in the addresses 2 through 17 of memory circuit 14 S as shown in FIG. 2. In this drawing, the left~hand numbers indicate the addresses of memory circ~i~ 14, and the right-hand alphanumerics indicate the contents of the memory at the respective addresses.
As understood from the foregoing description, the conventional word generator is not suitable to generate a lony vector consisting of many words, because it must store all of the words sequentially. It is cumbersome and tedious for the operator to set each word in the word generator. Moreovery a large memory capacity is necessary for the long vector.
Referring to FIG. 3, there is shown a simplified block diagram of the present invention. Control circuit 20 consisting of microcode memory section 22 and control section 24 applies the PC to vector memory 26, and the output from vector memory 26 is a parallel-bit signal to ~e applied to output counter 28. Control circuit 20 controls load/counting mode of output counter 280 Clock generator 12 applies the clock signal to control circuit 20, vector memory ~6 and output counter 28 for synch-25 ronizing operationsD The output frorn counter 28 isapplied through driver 13 to a product under test.
If the desired word pattern i~ determined, instructions and words are stored in microcode memory 22 and vector memory 26 respectively using a conventional technique in accordance with the desired word pattern.
The instructions stored in memory 22 are decoded to the PC
and a control signal by control section 24. The PC is used as the address signal for memories 22 and 260 If the vector is not sequential numbers, control section 24 applies the load instruction as the control signal to output counter 28, and the word stored in the appointed - 4a -address of memory 26 is loaded to counter 28. The loaded word is applied to driver 18. If the vector comprises sequential numbers, the word stored in the appointed address of vector memory 26 presets output counter 28 t and control section 24 applies the counting instruction as the control signal to counter 28 for the predetermined period determined by the instruction in microcode memory 22.
Counter 28 starts to count the clock signal from the preset number, and stops counting when the counting instruction ends. Thus, the output from counter 28 is the sequential ~ 5 numbers, and is applied to driver 18. Since counter 28 generates the sequential vector (numbers) by counting the clock signal, Long sequential words can be produced with only one instruction in microcode memory 22 and one start word in vector memory 26. Thus ~ the present invention can save memory capacity.
When microcode memory 22 receives the PC as the address signal from control section 24, memory 22 applies the next instruction to cont.rol section 24. The next instruction i.s decoded and used in the same manner as the former instruction described hereinbefore. If the vector words i.nclude the sarne pattern consis~ing of a plurality of words at different times, a subroutine technique is available. This pattern is stored in the predetermined addresses of vector memory 26, and is called by the instruction in microcode memory 22.
Moreover, ~he present invention can use a jump technique~
Thus, the present invention can further save the mernory capacity, and can generate a large number of vectors wi~h a short instxuction sequence.
The present invention will be further described in detail with reference to FIG. 4. The instruction (consisting of a plurality of bits) in microcode memory 22 is transferred to instruction register 30 which divides the instruction into the upper bits as the command signal and the lower bits as the address signal. The command signal is applied to control logic 32 which decodes it into many control signals, and the address signal is applied to instruction multiplexer 34 as a jump call or call address. The output from multi-plexer 34 is the PC which is applied to program counter 36 and microcode memory 22. Counter 36 acts as a pipe line for synchronizing and adjusting the timing of the PC. The PC
from counter 36 cietermines the address of vector memory 26 and is applied to "PC + l" circuit 38 which produces the next address (~P + lN) of the present address (PC). The output from circuit 38 is stored in stack memory 40.
Instruction multi.plexer 34 ~~ 3~
receives the output from "PC ~ L" circuit 38 as art advance address and the output from stack memory 40 as a return address. The word stored in vector memory 26 is applied to output counter 28 act;ng as the counter or register as described hereinbefore. The output from counter 28 is applied through driver 18 to the product under test.
Control logic circuit 32 produces four control signals, namely, an input selection signal for instruction multi-plexer 34, a stack control signal for stack memory ~0, a load/counting control signal for output counter 28 and a strobe control signal for strobe circuit 42 in accordance with the instruction from register 30. Strobe circuit 42 generates a strobe signal to be applied to the product under test, and clock generator applies the clock signal to each block. Blocks 30 through 40 correspond to control section 24 of FIG. 3.
As described hereinbefore, microcode memory 22 stores the instruction and address information, and vector memory 26 stores the word information. This information is stored in a conventional manner, and the present invention uses conventional computer techniques such as subroutine, jump or the like. When the read out signal of microcode memory 22 includes the advance instruction, this instruction is applied through instruction register 30 to control logic circuit 32. On the other hand, "PC + l" circuit 38 produces the advance address (the next address of the present adclress) Instruction multiplexer selects this advance address in response to the control signal from control logic circuit 32, and applies the output (PC) to 3~ vector memory 26 through program counter 36 and to micro-code memory 22. The word in the advance address of vector memory 26 is applied to output counter 28 which acts as the register because it receives the load instruction from control logic circuit 32. The output from counter 28 is applied to driver 18. If the instruction in microcode memory 22 includes the counting command, control logic circuit 32 applies this command to output counter 28 so that it counts the predetermined number of the clock pulse~s determined by the instruction from microcode memory 22.
In this instance, output counter 28 is preset by the word from vector memory 26 as described hereinbefore. Microcode memory 22 generates the next instruction in accordance with the PC from instruction multiplexer 3~.
When the read out signal of microcode memory 22 includes a jump instruction and address signal, instruction register 30 applies the jump address and the jump instruc-l~ tion to instruction multiplexer 34 and control logiccircuit 32 respectively. In accordance with the control signal from control logic circuit 32, instruction multi-ple~er 34 selects the jump address and applies it to vector memory 26 through program counter 36 and to micro-code memory 22. The word in the jump address of vector memory 26 is applied to output counter 2~ which receivesthe load instruction from control logic circuit 32. The output from counter 28 is applied to driver 18. When microcode memory 22 receives the jump address, it may produce the next instruction stored in the address.
~ hen the read out signal of microcode memory 22 includes the call instruction and address signal, instruc-tion register 30 applies the call instruction and call address to control logic circuit 32 and instruction multi-plexer 34 respectively. Multiplexer 34 selects the call address in response to the control signal ~rom controllogic circuit 32, and applies it to vector memory 26 through program counter 36 and to microcode memory 22. On the other hand, in accordance with the control signal from 3~ control logic circuit 32, stack memory 40 stores th~ next address of the present address because of "PC + 1" circuit 38. Microcode and vector memories 22 and 26 ~tore the instructions and words as the subroutine at the addresses starting from the call address. 'rhe last instruction of the subroutine in microcode memory 22 is a return command. When control logic circuit 32 receives the return command via instruction register 30, instruction multiplexer 34 selects the return address stored in stack memory 40 which corresponds to the next address of the former address before the call operation.
The return address is applied to microcode memory 22 and vector memory 26, and the normal operation restarts.
The operation of the present invention will be further described with reEerence to `FIGS. 5 and 6. In this instance, the word generator of the present invention generates the following word pattern (~ bits, hexadecimal) lO as one e~ample: Ol, 02, 03, 04, 05, F7, C3, 08~09, OA, OB, C2, C4, 08, 09, OA, OB, C9. It should be noted that this word pattern is the same as the pattern shown in FIG. 2.
FIG. 5 shows the program for the word pattern. The first line "Ol COUNT 05" means that output counter 28 counts from "Ol" to "05". The second line "F7" is the next vector, and third line "C3 CALL X" means that the sub-routine "X" is called after the vector "C3". The fourth line "C2" is the next ~ector, and the fifth line '1C4 CALL
X" means that the subroutine "X" is called after the vector
Backgrourld of the Invention The present invention relates to an algorithmic word generator which generates a logic word pattern for stimulating or simulating a digital circuit or systern.
It is becoming a common pract:ice to incorporate microprocessors .nto digital elecl-ronic apparatus to provide intelligen~ functions. For stimulating or simulating such apparatus/ knowledge of emulators editors compilers or assemblers is required in general~ Obtaining such knowledge~ however, is troub:Lesome and burdensome for digital designers~ evaluators and manufactu.ri.ng personnel.
It is known to utilize word generators which allow the user to stimulate and debug the digital apparatus by easily simulating logic blocks or bus structures~ Known good hardware can be used to simulate defective or unavailable hardware in a manner which does not require the knowledge of the emulators, editors, compilers or a~semblers. The ability to simulate most bus structures provides a tool for system debugging which is otherwise unavailable.
A prior art word generator will be described hereinbelow.
In accordance with an aspect of the invention there is provided a digital ~ord generating apparatus for providing a selectable sequence of digital output words for use in the testing of a product, said apparatus comprising a microcode memory means having a plurality of addressable memory locations for retaining a preselected sequence of microprogram words containing instruction and address information and for providing the contents of one of said addressable memory locations to a microcode memory output bus in response to programming code signals; an instruction regl.ster means for storing the contents of said microcode memory output bus and for dividing the stored microcode word into cornrnand and address signals;
control logic means coupled to the instruction register - la --means for generating control logic signa:Ls in resp~nse to the command signals of said instruction register;
instruction multiplexer means for providing the programming code signals in response to the address signal of said instruction register, said contro:l logic signals, a return signal, and an advance signal; program counter means coupled to said instruction multiplexer means for retaining the microcode memory address last provided by the programming code signals; advance counter means coupled to said program counter means and said instruction multiplexer means for providing sa.id advance signal in response to the contents of said program counter means;
stack means coupled to said advance counter means and instruction multiplexer means for storing the contents o~
said advance counter means in response to control logic signals indicative that a subroutine call instruction is in said instruction register means and for thereafter providing said return signal in response to the oontents stored therein; vector memory means coupled to said program counter means for having stored therein vector words corr sponding to said programming code signals and for providing a vector memory output signal in response thereto; output counter means coupled to said vector memory means and said control logic means for providing said digital out:put words in response to the contents of said vector memory means and said control logic signals~
According to one embodiment of the present invention, a microprogrammable word generation system is provided~
The present invention uses two high-speed memories, such as a microcode (first) memory and a vector (second) memory, and an output counter. The microcode memory contains instructions which are processed by a control logic circuit and are used to generate a number designated as a programming code (PC). The PC may be yenerated in an aLgorithmic manner using advance, ~lump, call and return instructions. This allows the vector memory to be addressed in the algorithmic manner. The vector memory stores the words as the components of the vector. Thus, a short instruction sequence may generate thousands of vectors~ Since ~he vector memory outputs are passed through an output counter instead of a register, the counter allows one instruction ~o provide the vector and then increases it a predetermined number of times. In addition to the vector outputs~ the word generator of the present invention may provide programmable s~robe outputs which enables the ~UT to simulate various bus structures~
It is therefore one object of the present invention to provide an algorithmic word generator which employs a microprogrammable technique.
It is another object to pro~ide a word generator which has an easily understood instruction set suitable for stimulation and simulation of digital circuits and systems.
It is a further object to provide a word generator including micrococle and vector memories and an output counter.
It is an additional object to provide a word generator which can generate thousands of vectors with a short instruction sequence.
It is another object to provide a word generator which does not need :Large memory capacity for generating a large number of vectors~
Other objects and advantages of the present invention will become apparent to those having ordinary skill in the art when taken in conjunction with the accompanying drawings.
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L~
~ 3 --Drawinqs FIG. 1 shows a block diagram of a conventional word generator;
FIG. 2 shows a content of a memory circuit used in FIG. l;
FIG. 3 shows a simplified block diagram of the present invention;
FIG. 4 shows a detailed block sli.agram of the present invention;
FIG. 5 shows a program for explaining the operation of FIG. 4;
~IGs~ ~A and 6B show contents of microcode and vector memories used in FIG~ 4;
Fig. 7 shows a circuit schematic of ~.he microcode memory used in FIG. 4;
FIG. 8 shows a circuit schematic of ~he vector memory and output counter used in FIG. 4; and FIG. 9 ~appearing on the same sheet of drawings as FIG. 5) shows a circuit schematic of the '1PC + 1" circuit used in FIG. 4.
Detailed Description of the Invention A conventional word generator is shown in FIG. 1.
Address counter 10 counts the clock signal from clock generator 12 to p~rovide an address signal to memc3ry circuit 14, such as a random access memory which receives the clock signalO Control circuit 16 presets and resets counter 10, and controls the read/write mode of memory circuit 14. In the wrlte mode, control circuit 16 writes predetermined words in memory circuit 14 in accordance with the address signal~ In the read mode, the stored word in memory circuit 14 is read out in accordance with the address signal and applied throuyh driver 18 to PUT
(product under test).
For example, suppose the operator wants following 8 bit-words ~hexadecimal): 01, 02, 03, 04, 05, F7, C3, 08, 09, OA, OB, C2, C4, 08, 09, OA, OB, and C9. The f irst ~1;
.
3~
4 _ i word 01 ~0000 0001) is stored in the address 0 of mernory circuit 14, and the second word 02 (0000 OOln) ls stored in the address lo The third through eighteen~ words are stored in the addresses 2 through 17 of memory circuit 14 S as shown in FIG. 2. In this drawing, the left~hand numbers indicate the addresses of memory circ~i~ 14, and the right-hand alphanumerics indicate the contents of the memory at the respective addresses.
As understood from the foregoing description, the conventional word generator is not suitable to generate a lony vector consisting of many words, because it must store all of the words sequentially. It is cumbersome and tedious for the operator to set each word in the word generator. Moreovery a large memory capacity is necessary for the long vector.
Referring to FIG. 3, there is shown a simplified block diagram of the present invention. Control circuit 20 consisting of microcode memory section 22 and control section 24 applies the PC to vector memory 26, and the output from vector memory 26 is a parallel-bit signal to ~e applied to output counter 28. Control circuit 20 controls load/counting mode of output counter 280 Clock generator 12 applies the clock signal to control circuit 20, vector memory ~6 and output counter 28 for synch-25 ronizing operationsD The output frorn counter 28 isapplied through driver 13 to a product under test.
If the desired word pattern i~ determined, instructions and words are stored in microcode memory 22 and vector memory 26 respectively using a conventional technique in accordance with the desired word pattern.
The instructions stored in memory 22 are decoded to the PC
and a control signal by control section 24. The PC is used as the address signal for memories 22 and 260 If the vector is not sequential numbers, control section 24 applies the load instruction as the control signal to output counter 28, and the word stored in the appointed - 4a -address of memory 26 is loaded to counter 28. The loaded word is applied to driver 18. If the vector comprises sequential numbers, the word stored in the appointed address of vector memory 26 presets output counter 28 t and control section 24 applies the counting instruction as the control signal to counter 28 for the predetermined period determined by the instruction in microcode memory 22.
Counter 28 starts to count the clock signal from the preset number, and stops counting when the counting instruction ends. Thus, the output from counter 28 is the sequential ~ 5 numbers, and is applied to driver 18. Since counter 28 generates the sequential vector (numbers) by counting the clock signal, Long sequential words can be produced with only one instruction in microcode memory 22 and one start word in vector memory 26. Thus ~ the present invention can save memory capacity.
When microcode memory 22 receives the PC as the address signal from control section 24, memory 22 applies the next instruction to cont.rol section 24. The next instruction i.s decoded and used in the same manner as the former instruction described hereinbefore. If the vector words i.nclude the sarne pattern consis~ing of a plurality of words at different times, a subroutine technique is available. This pattern is stored in the predetermined addresses of vector memory 26, and is called by the instruction in microcode memory 22.
Moreover, ~he present invention can use a jump technique~
Thus, the present invention can further save the mernory capacity, and can generate a large number of vectors wi~h a short instxuction sequence.
The present invention will be further described in detail with reference to FIG. 4. The instruction (consisting of a plurality of bits) in microcode memory 22 is transferred to instruction register 30 which divides the instruction into the upper bits as the command signal and the lower bits as the address signal. The command signal is applied to control logic 32 which decodes it into many control signals, and the address signal is applied to instruction multiplexer 34 as a jump call or call address. The output from multi-plexer 34 is the PC which is applied to program counter 36 and microcode memory 22. Counter 36 acts as a pipe line for synchronizing and adjusting the timing of the PC. The PC
from counter 36 cietermines the address of vector memory 26 and is applied to "PC + l" circuit 38 which produces the next address (~P + lN) of the present address (PC). The output from circuit 38 is stored in stack memory 40.
Instruction multi.plexer 34 ~~ 3~
receives the output from "PC ~ L" circuit 38 as art advance address and the output from stack memory 40 as a return address. The word stored in vector memory 26 is applied to output counter 28 act;ng as the counter or register as described hereinbefore. The output from counter 28 is applied through driver 18 to the product under test.
Control logic circuit 32 produces four control signals, namely, an input selection signal for instruction multi-plexer 34, a stack control signal for stack memory ~0, a load/counting control signal for output counter 28 and a strobe control signal for strobe circuit 42 in accordance with the instruction from register 30. Strobe circuit 42 generates a strobe signal to be applied to the product under test, and clock generator applies the clock signal to each block. Blocks 30 through 40 correspond to control section 24 of FIG. 3.
As described hereinbefore, microcode memory 22 stores the instruction and address information, and vector memory 26 stores the word information. This information is stored in a conventional manner, and the present invention uses conventional computer techniques such as subroutine, jump or the like. When the read out signal of microcode memory 22 includes the advance instruction, this instruction is applied through instruction register 30 to control logic circuit 32. On the other hand, "PC + l" circuit 38 produces the advance address (the next address of the present adclress) Instruction multiplexer selects this advance address in response to the control signal from control logic circuit 32, and applies the output (PC) to 3~ vector memory 26 through program counter 36 and to micro-code memory 22. The word in the advance address of vector memory 26 is applied to output counter 28 which acts as the register because it receives the load instruction from control logic circuit 32. The output from counter 28 is applied to driver 18. If the instruction in microcode memory 22 includes the counting command, control logic circuit 32 applies this command to output counter 28 so that it counts the predetermined number of the clock pulse~s determined by the instruction from microcode memory 22.
In this instance, output counter 28 is preset by the word from vector memory 26 as described hereinbefore. Microcode memory 22 generates the next instruction in accordance with the PC from instruction multiplexer 3~.
When the read out signal of microcode memory 22 includes a jump instruction and address signal, instruction register 30 applies the jump address and the jump instruc-l~ tion to instruction multiplexer 34 and control logiccircuit 32 respectively. In accordance with the control signal from control logic circuit 32, instruction multi-ple~er 34 selects the jump address and applies it to vector memory 26 through program counter 36 and to micro-code memory 22. The word in the jump address of vector memory 26 is applied to output counter 2~ which receivesthe load instruction from control logic circuit 32. The output from counter 28 is applied to driver 18. When microcode memory 22 receives the jump address, it may produce the next instruction stored in the address.
~ hen the read out signal of microcode memory 22 includes the call instruction and address signal, instruc-tion register 30 applies the call instruction and call address to control logic circuit 32 and instruction multi-plexer 34 respectively. Multiplexer 34 selects the call address in response to the control signal ~rom controllogic circuit 32, and applies it to vector memory 26 through program counter 36 and to microcode memory 22. On the other hand, in accordance with the control signal from 3~ control logic circuit 32, stack memory 40 stores th~ next address of the present address because of "PC + 1" circuit 38. Microcode and vector memories 22 and 26 ~tore the instructions and words as the subroutine at the addresses starting from the call address. 'rhe last instruction of the subroutine in microcode memory 22 is a return command. When control logic circuit 32 receives the return command via instruction register 30, instruction multiplexer 34 selects the return address stored in stack memory 40 which corresponds to the next address of the former address before the call operation.
The return address is applied to microcode memory 22 and vector memory 26, and the normal operation restarts.
The operation of the present invention will be further described with reEerence to `FIGS. 5 and 6. In this instance, the word generator of the present invention generates the following word pattern (~ bits, hexadecimal) lO as one e~ample: Ol, 02, 03, 04, 05, F7, C3, 08~09, OA, OB, C2, C4, 08, 09, OA, OB, C9. It should be noted that this word pattern is the same as the pattern shown in FIG. 2.
FIG. 5 shows the program for the word pattern. The first line "Ol COUNT 05" means that output counter 28 counts from "Ol" to "05". The second line "F7" is the next vector, and third line "C3 CALL X" means that the sub-routine "X" is called after the vector "C3". The fourth line "C2" is the next ~ector, and the fifth line '1C4 CALL
X" means that the subroutine "X" is called after the vector
2~ "C4". The sixth line "C9 HALT" means that this word pattern ends after the vector "C9". The seventh line "X"
means the subroutine, and "08" thereof is the first word of the subroutine. "09", "OA" and "OB" are the second through fourth words of the subroutine. "RETURN" means to return the next address of "CALL". As understood from FIG. 5, the present invention has an easily understood instruction.
FIG. 6A and 6B show the contents of microcode memory 22 and vector memory 26 respectively. The numbers outside the rectangles indicate the addresses of memories 22 and 26, and the alphanumerics inside the rectangles are the instructions and words stored in memories 22 and 260 These instructions and words are written in the memories in a conventional manner.
At the first time, the content "Ol" in the address O
of vector memory 26 is loaded to output counter 2~, and the counting instruction (until 5~ in I ~
the address O of microcode memory 22 is applied to control logic circuit 32. Counter 28 counts frcm 01 to 05 in accordance with this instruction. After the count operation t instruction multiplexer 34 selects the advance address ~
from "PC ~ 1~ circuit 38. (In this instance, the PC is O
and PC + 1 = 1)~ The word 'IF7" in the address 1 of vector memory 26 is loaded to output counter 28, and microcode memory 22 generates the advance instruction from ~he address 1. Instruction multiplexer 34 selects the output (2~ from "PC ~ 1" circuit 38, and the PC (2) is applied to vec~or memory 26 and microcode memory 22. The word "C3" in the address 2 of vector memory 26 is loaded to output counter 28. Microcode memory 22 generates the call instruction and address X from the address 2. Stack memory 40 stores 3 (2 -~ 1) from "PC + 1" circuit 38, and instruction multiplexer 34 selects the call address (X). The word "08~ in address X
of vector memory ~6 is loaded into output ~ounter 28, and microcode memory 22 generates the advance instruc ionO
"PC ~ 1" circuit 38 generates ~X ~ 1", and instruction multiplexer 34 selects the advance address (X ~ 130 Similar operations are repeated.
When instruction multiplexer 34 generates the advance address (X + 3), the word "OB" in the address X + 3 of vector memory 26 is loaded into outpu~ counter 28, and microcode memory 22 produces the return instruction~
Instruction multiplexer 34 selects the output from stack memory 40, and generates the address "3" as the PC~ The word "C2" in address 3 of vector memory 26 is loaded to output counter 28, and the advance instruction is produced from the address 3 of microcode memory 22. Similar operations are repeated, and then the predetermined word pattern "01, 02t 03, 04, 05t F7~ C3, 08, 09, OA, OB, C2, C4, 08, 09, OA, OB, C9" would be ohtained. As can be understood by those skillecl in the art, the counting, jump, call and advance instruct:ions are very useful for generating large numbers of vectors with a short instructio~ sequence.
It should be noted that strobe circuit 42 generates the strobe signal for each word.
FlG. 7 shows a circuit schematic of microcode memory 22 used in FIG. 4. There are two microcode memory sections 44 and 46 each including address decoder 48 and memories 50. Memory section 44 is for the 5-bit-parallel instruc-tion, and memory section 46 is for the 8-bit-parallel instruction. These sections 44 and 46 may be combinations of many IC's such as type 1044. The address signal ~PC) from instruction multiplexer 34 is loaded into registers 52 and 54 such as type 10176 and 10131. The PC from registers 52 and 54 is applied to terminals A0 through A7 of address decoders 48. In the read mode, write enable terminals WE of sections 44 and 46 receive "High" from a microprocessor system ( ~P, not shown in FIG. 4), and the data stored in the appointed address of memories 50 are applied from terminals D to instruction register 30.
In the write mode, write enable terminals WE of memory 2~ sections 44 and 46 are "Low", and the predetermined data are applied to terminals DIN of memories 50 from ~P in accordance with the program such as FIG. 5.
FIG. 8 shows a circui~ schematic of vector memory 26 and output counter 28 used in FIG. 4. Vector memory 26 consists of memory sections 56 and 58 each including address decoder 48 and memories 50 similarly to FIG. 7.
Write enable terminals WE of memory sections 56 and 58 are same as memory sections 44 and ~6 of FIG. 7. In the write mode, ~P ~not shown) applies the predetermined data to terminals DIN of memories 50 in accordance with the address signal. In the read mode, terminals A0 through A7 of address decoders 48 receive the address signal (PC) from programmable counter 36, and the stored data are applied from terminals D of memories 50 to terminal D0 through D3 of output counter 28 consisting of four counters 60 through 66. Load terminals LD of counters 60 through 66 receive the load/counting control signal from control logic circuit 32. Wllen the control signal is "Low", the counters are in the load mode. When the control signal is "High", the counters are in the counting mode. The outputs from terminals Q0 through Q3 are applied to driver 18. The clock signal is applied to the clock terminal of the counters from clock generator 12. The counters 60 through 66 may be IC's, such as type 10136.
FIG. 9 shows a circuit schematic of "PC ~ 1" circuit 38 used in FIG. 4. The P~ from program counter 36 is applied to terminals D0 through D3 of arithmetic logic units 68 and 70, such as type 10181 IC, and is incremented by one. Units 68 and 70 add 0000 (binary) to the PC, but the carry is activated. The outputs from units 68 and 70 are clocked through registers 72 and 74 such as type 10131 15 and 10176 ICIs. The outputs from register 72 and 7~ are used by the advance address to increase the value of program counter 36 by one, and are applied to stack memory 40.
While I have shown and described herein the preferred embodiment of my invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from my invention in its broader aspects. For example, control logic circuit 32 may be included in the microprocessor system comprising a micro-processor, a read only memory for firmware, a random access memory as a temporary memory, and a keyboard as an input device. The contents of microcode memory 22 and vector memory 26 may be written with this microprocessor system.
In the preferred embodiment, output counter 28 acts as both the register and the increment counter. However, counter 28 may act as both the register and a decrement counter or both the register and an up-down counter. The instructions stored in microcode memory 22 further include repeat and hold instructions. According to the repeat instruction, the words stored in the predetermined addresses of vector memory 26 are read repeatedly the pre-determined times. According to the hold instruction, the output word is held.
means the subroutine, and "08" thereof is the first word of the subroutine. "09", "OA" and "OB" are the second through fourth words of the subroutine. "RETURN" means to return the next address of "CALL". As understood from FIG. 5, the present invention has an easily understood instruction.
FIG. 6A and 6B show the contents of microcode memory 22 and vector memory 26 respectively. The numbers outside the rectangles indicate the addresses of memories 22 and 26, and the alphanumerics inside the rectangles are the instructions and words stored in memories 22 and 260 These instructions and words are written in the memories in a conventional manner.
At the first time, the content "Ol" in the address O
of vector memory 26 is loaded to output counter 2~, and the counting instruction (until 5~ in I ~
the address O of microcode memory 22 is applied to control logic circuit 32. Counter 28 counts frcm 01 to 05 in accordance with this instruction. After the count operation t instruction multiplexer 34 selects the advance address ~
from "PC ~ 1~ circuit 38. (In this instance, the PC is O
and PC + 1 = 1)~ The word 'IF7" in the address 1 of vector memory 26 is loaded to output counter 28, and microcode memory 22 generates the advance instruction from ~he address 1. Instruction multiplexer 34 selects the output (2~ from "PC ~ 1" circuit 38, and the PC (2) is applied to vec~or memory 26 and microcode memory 22. The word "C3" in the address 2 of vector memory 26 is loaded to output counter 28. Microcode memory 22 generates the call instruction and address X from the address 2. Stack memory 40 stores 3 (2 -~ 1) from "PC + 1" circuit 38, and instruction multiplexer 34 selects the call address (X). The word "08~ in address X
of vector memory ~6 is loaded into output ~ounter 28, and microcode memory 22 generates the advance instruc ionO
"PC ~ 1" circuit 38 generates ~X ~ 1", and instruction multiplexer 34 selects the advance address (X ~ 130 Similar operations are repeated.
When instruction multiplexer 34 generates the advance address (X + 3), the word "OB" in the address X + 3 of vector memory 26 is loaded into outpu~ counter 28, and microcode memory 22 produces the return instruction~
Instruction multiplexer 34 selects the output from stack memory 40, and generates the address "3" as the PC~ The word "C2" in address 3 of vector memory 26 is loaded to output counter 28, and the advance instruction is produced from the address 3 of microcode memory 22. Similar operations are repeated, and then the predetermined word pattern "01, 02t 03, 04, 05t F7~ C3, 08, 09, OA, OB, C2, C4, 08, 09, OA, OB, C9" would be ohtained. As can be understood by those skillecl in the art, the counting, jump, call and advance instruct:ions are very useful for generating large numbers of vectors with a short instructio~ sequence.
It should be noted that strobe circuit 42 generates the strobe signal for each word.
FlG. 7 shows a circuit schematic of microcode memory 22 used in FIG. 4. There are two microcode memory sections 44 and 46 each including address decoder 48 and memories 50. Memory section 44 is for the 5-bit-parallel instruc-tion, and memory section 46 is for the 8-bit-parallel instruction. These sections 44 and 46 may be combinations of many IC's such as type 1044. The address signal ~PC) from instruction multiplexer 34 is loaded into registers 52 and 54 such as type 10176 and 10131. The PC from registers 52 and 54 is applied to terminals A0 through A7 of address decoders 48. In the read mode, write enable terminals WE of sections 44 and 46 receive "High" from a microprocessor system ( ~P, not shown in FIG. 4), and the data stored in the appointed address of memories 50 are applied from terminals D to instruction register 30.
In the write mode, write enable terminals WE of memory 2~ sections 44 and 46 are "Low", and the predetermined data are applied to terminals DIN of memories 50 from ~P in accordance with the program such as FIG. 5.
FIG. 8 shows a circui~ schematic of vector memory 26 and output counter 28 used in FIG. 4. Vector memory 26 consists of memory sections 56 and 58 each including address decoder 48 and memories 50 similarly to FIG. 7.
Write enable terminals WE of memory sections 56 and 58 are same as memory sections 44 and ~6 of FIG. 7. In the write mode, ~P ~not shown) applies the predetermined data to terminals DIN of memories 50 in accordance with the address signal. In the read mode, terminals A0 through A7 of address decoders 48 receive the address signal (PC) from programmable counter 36, and the stored data are applied from terminals D of memories 50 to terminal D0 through D3 of output counter 28 consisting of four counters 60 through 66. Load terminals LD of counters 60 through 66 receive the load/counting control signal from control logic circuit 32. Wllen the control signal is "Low", the counters are in the load mode. When the control signal is "High", the counters are in the counting mode. The outputs from terminals Q0 through Q3 are applied to driver 18. The clock signal is applied to the clock terminal of the counters from clock generator 12. The counters 60 through 66 may be IC's, such as type 10136.
FIG. 9 shows a circuit schematic of "PC ~ 1" circuit 38 used in FIG. 4. The P~ from program counter 36 is applied to terminals D0 through D3 of arithmetic logic units 68 and 70, such as type 10181 IC, and is incremented by one. Units 68 and 70 add 0000 (binary) to the PC, but the carry is activated. The outputs from units 68 and 70 are clocked through registers 72 and 74 such as type 10131 15 and 10176 ICIs. The outputs from register 72 and 7~ are used by the advance address to increase the value of program counter 36 by one, and are applied to stack memory 40.
While I have shown and described herein the preferred embodiment of my invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from my invention in its broader aspects. For example, control logic circuit 32 may be included in the microprocessor system comprising a micro-processor, a read only memory for firmware, a random access memory as a temporary memory, and a keyboard as an input device. The contents of microcode memory 22 and vector memory 26 may be written with this microprocessor system.
In the preferred embodiment, output counter 28 acts as both the register and the increment counter. However, counter 28 may act as both the register and a decrement counter or both the register and an up-down counter. The instructions stored in microcode memory 22 further include repeat and hold instructions. According to the repeat instruction, the words stored in the predetermined addresses of vector memory 26 are read repeatedly the pre-determined times. According to the hold instruction, the output word is held.
Claims (4)
1. A digital word generating apparatus for providing a selectable sequence of digital output words for use in the testing of a product, said apparatus comprising:
a microcode memory means having a plurality of addressable memory locations for retaining a preselected sequence of microprogram words containing instruction and address information and for providing the contents of one of said addressable memory locations to a microcode memory output bus in response to programming code signals;
an instruction register means for storing the contents of said microcode memory output bus and for dividing the stored microcode word into command and address signals;
control logic means coupled to the instruction register means for generating control logic signals in response to the command signals of said instruction register;
instruction multiplexer means for providing the programming code signals in response to the address signal of said instruction register, said control logic signals, a return signal, and an advance signal;
program counter means coupled to said instruction multiplexer means for retaining the microcode memory address last provided by the programming code signals;
advance counter means coupled to said program counter means and said instruction multiplexer means for providing said advance signal in response to the contents of said program counter means;
stack means coupled to said advance counter means and instruction multiplexer means for storing the contents of said advance counter means in response to control logic signals indicative that a subroutine call instruction is in said instruction register means and for thereafter providing said return signal in response to the contents stored therein;
vector memory means coupled to said program counter means for having stored therein vector words corresponding to said programming code signals and for providing a vector memory output signal in response thereto;
output counter means coupled to said vector memory means and said control logic means for providing said digital output words in response to the contents of said vector memory means and said control logic signals,
a microcode memory means having a plurality of addressable memory locations for retaining a preselected sequence of microprogram words containing instruction and address information and for providing the contents of one of said addressable memory locations to a microcode memory output bus in response to programming code signals;
an instruction register means for storing the contents of said microcode memory output bus and for dividing the stored microcode word into command and address signals;
control logic means coupled to the instruction register means for generating control logic signals in response to the command signals of said instruction register;
instruction multiplexer means for providing the programming code signals in response to the address signal of said instruction register, said control logic signals, a return signal, and an advance signal;
program counter means coupled to said instruction multiplexer means for retaining the microcode memory address last provided by the programming code signals;
advance counter means coupled to said program counter means and said instruction multiplexer means for providing said advance signal in response to the contents of said program counter means;
stack means coupled to said advance counter means and instruction multiplexer means for storing the contents of said advance counter means in response to control logic signals indicative that a subroutine call instruction is in said instruction register means and for thereafter providing said return signal in response to the contents stored therein;
vector memory means coupled to said program counter means for having stored therein vector words corresponding to said programming code signals and for providing a vector memory output signal in response thereto;
output counter means coupled to said vector memory means and said control logic means for providing said digital output words in response to the contents of said vector memory means and said control logic signals,
2. Digital word generating apparatus as in claim 1 and further comprising:
strobe circuit means coupled to said control logic means for generating a strobe output signal to be applied to the product under test in response to said control logic signals.
strobe circuit means coupled to said control logic means for generating a strobe output signal to be applied to the product under test in response to said control logic signals.
3. Digital word generating apparatus as in claim 2 wherein said output counter means performs a predetermined modifying operation upon its contents and provides the modified contents as the digital output signal in response to said control logic signals.
4. Digital word generating apparatus as in claim 2 wherein said output counter means operates as a register and a counter in response to said control logic signals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US26944381A | 1981-06-02 | 1981-06-02 | |
| US269,443 | 1981-06-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1189191A true CA1189191A (en) | 1985-06-18 |
Family
ID=23027271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000404005A Expired CA1189191A (en) | 1981-06-02 | 1982-05-28 | Algorithmic word generator |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS57204955A (en) |
| CA (1) | CA1189191A (en) |
| DE (1) | DE3217024A1 (en) |
| FR (1) | FR2506973A1 (en) |
| GB (1) | GB2099618B (en) |
| NL (1) | NL8202113A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2543709B1 (en) * | 1983-03-30 | 1985-08-09 | Centre Nat Rech Scient | PROGRAMMABLE APPARATUS FOR GENERATING DIGITAL SEQUENCES FOR TESTING DIGITAL CIRCUITS |
| FR2553540B1 (en) * | 1983-10-13 | 1986-01-03 | Centre Nat Rech Scient | RANDOM TEST DEVICE FOR LOGIC CIRCUITS, ESPECIALLY MICROPROCESSORS |
| GB2149159B (en) * | 1983-10-28 | 1987-07-08 | Membrain Ltd | Method and apparatus for generating sequence of multibit words |
| US4764925A (en) * | 1984-06-14 | 1988-08-16 | Fairchild Camera & Instrument | Method and apparatus for testing integrated circuits |
| DE3515802A1 (en) * | 1985-05-02 | 1986-11-06 | Siemens AG, 1000 Berlin und 8000 München | ARRANGEMENT FOR FAST GENERATION OF LARGE TESTING DATA WORDS IN A TESTING DEVICE |
| US5454088A (en) * | 1985-11-15 | 1995-09-26 | Mitsubishi Denki Kabushiki Kaisha | Microprogram control device for controlling data path section including designation of instruction cycle values |
| JPS62117038A (en) * | 1985-11-15 | 1987-05-28 | Mitsubishi Electric Corp | Microprogram controller |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3641331A (en) * | 1969-11-12 | 1972-02-08 | Honeywell Inc | Apparatus for performing arithmetic operations on numbers using a multiple generating and storage technique |
| US3720820A (en) * | 1971-03-18 | 1973-03-13 | Tektranex Inc | Calculator with a hierarchy control system |
| US4108358A (en) * | 1977-03-22 | 1978-08-22 | The Bendix Corporation | Portable circuit tester |
-
1982
- 1982-04-13 GB GB8210683A patent/GB2099618B/en not_active Expired
- 1982-05-06 DE DE19823217024 patent/DE3217024A1/en not_active Withdrawn
- 1982-05-24 NL NL8202113A patent/NL8202113A/en not_active Application Discontinuation
- 1982-05-28 CA CA000404005A patent/CA1189191A/en not_active Expired
- 1982-05-28 JP JP57092069A patent/JPS57204955A/en active Pending
- 1982-06-01 FR FR8209831A patent/FR2506973A1/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| FR2506973A1 (en) | 1982-12-03 |
| GB2099618B (en) | 1985-07-03 |
| JPS57204955A (en) | 1982-12-15 |
| NL8202113A (en) | 1983-01-03 |
| DE3217024A1 (en) | 1982-12-23 |
| GB2099618A (en) | 1982-12-08 |
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