GB2184578A

GB2184578A - A microprogram control device

Info

Publication number: GB2184578A
Application number: GB08627257A
Authority: GB
Inventors: Hiromasa Nakagawa; Tsunenori Umeki
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1985-11-15
Filing date: 1986-11-14
Publication date: 1987-06-24
Also published as: GB2184578B; CA1270572A; JPS62117038A; GB8627257D0

Abstract

The device includes an instruction register 2 for storing an instruction code which is taken in from a data bus, (1) the means for generating an address for accessing microprogram memory 12 from the output of said instruction register including a first address decoder 5 for decoding an instruction type AD10 from a particular part of said instruction code of said instruction register and a second address decoder 6 for decoding the addressing mode AD20 of said instruction from the other particular bit of said instruction code; and a third address decoder 7 to function as an address signal generator for designating the microprogram cycle addresses AD30 for accessing said microprogram memory at each cycle of the instruction. The device controls a data path section 25 provided in a CPU via nano-ROM devices 17-20 which also receive instruction directly from instruction register 2. <IMAGE>

Description

SPECIFICATION Microprogram control device Field of the invention The present invention relates to a microprogram control device, and more particularly to that in which the address designation ofthe microprogram ROM bya successive address designating method is simplified by converting onlythe instruction cycle value of the successive address from the microprogram ROM.

Background art Figure 3 is a blockdiagramshowingthe microprogram control by the computer using the conventional successive address designating method recited in Electronics January 27, 1981,pp 107 to pp 111. This microprocessorisan 8 bit microcomputer. In Figure 3, the reference numeral 1 designates an 8 bit data bus, the reference numeral 2 designates an instruction register, the reference numeral 3 designates an address signal linefor sending the content of the instructions register 2 to the multiplexer and address decoder 5. The reference numeral 8 designates an 8 bit signal line to the microprogram ROM 12. The reference numeral 11 designates a successive address 8 bit signal ofthe microprogram ROM 12 of the next cycle which is output from the microprogram ROM 12.The reference numeral 13 designates a 43 bit control line between the data path section 25 and the microprogram ROM 12. The reference numeral 26 designates a selector signal line for controlling the multiplexer 5.

Figure 4 shows a timing chart of the operation of the microprogram control device of Figure 3. In Figure 4, the reference character * designates a system clock, the reference character IF designates an instruction fetch signal fortaking in the instruction code to the instruction register 2 from the data bus 1. The reference character IR designates the content of the instruction register 2 such as an operation code taken in from the data bus 1 by the IF.

The reference character AD1 designates an address ofthe microprogram ROM, and this address has an 8 bit width. The reference characters S1 to S3 designate the output of the microprogram ROM 12 for controlling the control line 13 of the data path section 25.

The operation of the microprogram control will be described with reference to Figures 3 and 4. The timing chart of Figure 4 is that in a case where an instruction (fourcycle instruction) is executed bythe microprogram control of Figure 3 Suppose thatthe instruction code is a provisional instruction such as AAh (hereinafter the h designates the hexadecimal representation).

In Figure4,when the IF signal is "H", an 8bit instruction code is taken in into the instruction register 2 from the data bus 1. At the next first cycle the output from the successive address designating signal line 11 1 which is a portion of the microcode from the microprogram ROM 12 is halted to be taken in into the multiplexer and address decoderS by the signal of the selector signal line 26, which signal is a portion ofthe same microcode. In this case, the content of the instruction register 2, that is, the 8 bit instruction code becomes the address of the microprogram ROM 12 through the multiplexer 5 (AAh in Figure 4), and it outputs a control signal to the data path section 25 in accordance with the microcode.

At the second cycle, as the address to be inputto the microprogram ROM 12 the previous cycle 8 bit successive address from the microprogram ROM 12 is obtained caused by that the input of the multiplexer 5 is switched in accordance with the selector signal 26. By this method it is possible to obtain a random value as the successive address.

In the cycles subsequent thereto the address output atthe previous cycle is input to the microprogram ROM 12 to conduct a control successively until this instruction is concluded. In Figure 4, as the AD1 AAheA3h~B4heC5h can be output in turn from the first cycle.

In such a prior art successive address designating system, in a case where the bit width ofthe instruction code falls in the 8 bit class the control cannot be conducted when the number of combination of the control pattern (control lines of 43 bit) for controlling the CPU becomes larger than 256.

Accordingly, in a case where a bit width ofthe instruction code of a microcontroller or microprocessor is one largerthan an 8 bit, for example, a 16 bit, it is quite ineffective to utilize the access method against the microprogram ROM 12 in which the successive address has a 16 bitwidth similarly as the prior art method of Figure 3.

Furthermore in this case, as the control pattern for controlling the data path section 25216 kinds of successive addresses can be output, but such a system is not practical. Furthermore,the instruction code in the microcontroller or the microprocessor are often constituted by such as an instruction type designating bit such as an operation instruction, a transfer instruction, or a jump instruction, or an addressing mode designating bit. Especially when the instruction code width falls a in 16 bit class, the instruction type and the addressing mode are used quite often, and a sufficient performance cannot be accomplished bythe priorartsuccessiveaddress designating method.

Summary ofthe invention An object of the present invention is to provide an improved microprogram control device wherein a successive address designating method ofthe microprogram ROM is simply realized on an integrated circuit even if the bit number ofthe instruction code and the number of the data bus control (the number of the control pattern) are increased.

Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the artfrom this detailed description.

According to the present invention,there is provided a microprogram control device for controlling a data path section provided in a CPU with the use of the microcode which is stored in a microprogram memory by a microprogramming method in a computer conducting a microprogram control, which comprises: an instruction register for storing an instruction code which is taken in from a data bus; means for generating an addressfor accessing said microprogram memory from the output of said instruction register including a first address decoder for decoding an instruction type from the particular bit of said instruction code of said instruction register and a second address decoder for decoding the addressing mode of said instruction from the other particular bit of said instruction code; and a third address decoder to function as an address signal generator for designating the timing for accessing said microprogram memory at each cycle of the instruction.

Brief description ofthe drawings Figure 1 is a block diagram showing a microprogram control device utilizing a successive addressing method as an embodiment of the present invention; Figure2isatimingchartforexemplifyingthe operation thereof; Figure 3 is a block diagram showing the prior art successive addressing system microprogram control device; and Figure4is a timing chartforexemplifying the operation thereof.

Detailed description ofthe preferred embodiments In order to explain the present invention in detail, reference will be particularly made to Figure 1.

In Figure 1,the reference numeral 1 designates a data bus, the numeral 2 designates an instruction register, the numeral 12 designates a microprogram ROM, the numerals 5 and 6 designate a first and a second address decoder which receives the instruction code in the instruction register 2 and generates addressesforthe microprogram ROM 12.

The reference numerals 17 to 20 designate circuits for decoding the output microcode ofthe microprogram ROM 12 against each control bit on the data path section 25 (hereinafter reffered to as nano-program memory; nROM). The reference numerals 21 to24designateoutputsignal linesfrom the nROM to the data path section 25. The reference numerals 13 to 16 designate output signal lines from the microprogram ROM l2tothe nROMs 17to 20.

The reference numeral 7 designates a decoder for receiving the output of the microprogram ROM 12 and designating the successive address for designating the cycle value ofthe instruction.

Furthermore, the reference numeral 11 designates a successive address signal line from the microprogram ROM 12, and the reference numerals 8 to 10 designate address output lines (AD1 0, AD20, AD30) from the address decoders 5 to 7 to the microprogram ROM 12. In this embodimentthe successive address designation is conducted by the address decoder 7. The reference numeral 4 designates a signal line for sending the instruction code from the instruction register 2 to the nROMs 17 to 20.

Next, the operation of this microprogram control device will be described. Figure 2 shows a timing chart in executing an instruction (4 cycle instruction) as the microprogram control of Figure 1. Suppose that the instruction code is a provisional instruction of AAAAh.

In Figure 2,when the IFsignal is "H",a 16 bit instruction code from the data bus 1 is taken in into the instruction register 2. At the next cycle components relating to the instruction type and the addressing mode are extracted from the instruction code which is taken in into the instruction register 2, and it is made an address of the microprogram ROM 12. In Figure 2, the first cycle outputs are made, for example, AOh and BOh. This value is held until the instruction is concluded. Thefirstcycle address decoder 7 takes out a microcode from the microprogram ROM 12 so as to enable of setting the address at a cycle value (1 h in Figure 2) at which the instruction is started.

In the cycles subsequentthereto, that is, in the second, the third, and the fourth cycle the successive addressesareoutputfrom a portion ofthe microprogram ROM 12successively. For example, the successive addresses are 3h#5h#6h as shown in Figure 2. At each cycle the output from the microprogram ROM l2issenttothenROMs 17to20, and these are combined with a portion ofthe instruction code of the instruction register 2 to generate a control signal to be sentto the data path section 25.

In this embodiment the address input of the microprogram ROM comprises three components of an instruction type, an addressing mode both separated from the instruction code, and an instruction cyclevalueoutputfromthe microprogram ROM, and the successive address designation from the microprogram ROM is conducted by only the instruction cycle value.

Accordingly, it is possible to preventthe increase in the bit number of the microcodes for designating the successive addresses of the microprogram ROM even ifthe bit number of instruction codes of a microcomputer or microcontroller is increased in a case where the successive address designating method is used. This results in that a microcomputer ormicrocontrollerwhich utilizes the successive address designating method with an increased bit number of instruction codes is easily realized on integrated circuits. Furthermore, it results in a tremendously efficient development of a microcomputer.

Claims

1. A microprogram control device for controlling a data path section provided in a CPU with the use of the microcode which is stored in a microprogram memory by a microprogramming method in a computer conducting a microprogram control, which comprises: an instruction registerforstoring an instruction code which is taken in from a data bus; means for generating an addressforaccessing said microprogram memory from the output of said instruction register including a first address decoder for decoding an instruction type from the particular bit of said instruction code of said instruction register and a second address decoderfordecoding the addressing mode of said instruction from the other particular bit of said instruction code; and a third address decoder to function as an address signal generator for designating the timing for accessing said microprogram memory at each cycle of the instruction.

2. A microprogram control device as defined in Claim 1, which further comprises decoding means for decoding the microcode comprising the combination of the microcode read out from the microprogram memory by the address designation from the three address decoders and the bit of a portion of the instruction code from said instruction registertocontrol each blockofsaiddata path section.

3. A microprogram control device as defined in Claim 1, wherein the microprogram memory is accessed for each cycle of instruction by a successive address designating method in which a portion of the previous cycle output of said microprogram memory constitute a portion of the address component ofthe next cycle.

4. A microprogram control device as defined in Claim 1, wherein the respective circuits of said control device are provided on a semiconductor integrated circuit.

5. A microprogram control device substantiate hereinbefore described to reference to Figures 1 and 2.