JPS60167034A - Auxiliary control memory for upgrading performance of cpu pipeline - Google Patents

Abstract

g An entry control store in a central processing unit (CPU) is addressed by the next macroinstruction to be executed by the CPU and fetches the microcode for the first line of that macroinstruction.The apparatus includes an entry point table (42) and a control store (58) wherein, in macroinstruction access a pointer in the entry point table is used to obtain microcode from the control store (58) and place it on a bus (62) connected to output lines of the control store (58). An auxilliary control store (48), containing the first line of microcode for each macroinstruction, is accessed by the microinstructions and has output lines which are selectably connected to the bus (62) by bus selection means (84) for selectively disconnecting the output lines of the control store (58) from the bus (62) when the output lines of auxilliary control store (48) are selectably connected to the bus (62). The selection means (84) are arranged to respond to microcode indicia (80) indicating whether the control store (58) or the auxilliary control store (48) are to be connected to the bus (62).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to data processors and central processing units present in data processors. In particular, the present invention relates to a control storage architecture used in executing a macroinstruction using a series of microinstructions in a pipelined microinstruction execution scheme.

BACKGROUND OF THE INVENTION Central processing units (CPtJs) that execute macroinstructions in a pipelined manner using a series of microinstructions are well known in the art. Pipelined microinstruction execution generally allows execution of an earlier rank of a second instruction to begin while a later phase or rank of a first instruction is being executed, resulting in faster overall instruction execution.

Conventional pipelined control storage devices are typically sourced from an entry point table that decodes the macroinstruction and generates a pointer to the first microinstruction. The pointer is placed in a hold register from which it is used to access control storage. Subsequent microinstructions either increment the value held in the hold register each clock period, or use fields in the microcode of the first microinstruction to address the next and subsequent microinstructions. address.

The process by which macroinstructions are used to fetch microinstructions is typically three clock periods for a two-rank microcode scheme. A first clock period sets the value of the entry point table into the hold register, a second clock period sets the rank 1 microcode field in the register, and a third clock period sets the rank 2 microcode field into the register. Set a field into a register. The register values are then used to perform microcode functions and actually execute instructions. Portions of the microcode that are executed after said consecutive clock cycles, such as ranks 3 or higher, are executed similarly.

Due to the nature of pipelining, multiple clock periods are required for a single line of microcode execution. This point in instruction execution is one of the factors that determines the instruction loop node in a data processing system. Because throughput and speed are important considerations in data processing systems, improvements in the instruction execution portion of data processing systems result in improved system performance.

Therefore, there is currently a need for control storage devices that can execute macro instructions in fewer clocks than are required to execute the macro instructions.

OBJECTS OF THE INVENTION It is therefore an object of the present invention to provide a control storage device capable of executing the microcode of the first line of macroinstructions in a bilined CPU in fewer clock periods than is possible with currently known systems. It's about doing.

Another object of the invention is to provide a control store with additional entries for providing clock periods to the first line of microcode earlier than is available using current systems.

These and other objects of the invention will be more clearly understood upon reference to the detailed description, accompanying drawings, and claims.

(Structure of the Invention) Control such that an entry point table is provided with a macro instruction from a next instruction register or similar device, and the table provides a pointer to a control storage containing microcode for a second line of the macro instruction. A storage device is obtained.

Also, the information addressing the entry point table is
Each macroinstruction also addresses an entry control store containing information for the first microinstruction. The control store contains, for each macroinstruction, all the microcode for subsequent microinstructions.

Preferably, the bit field located following the last line of microcode of each macroinstruction provides entry control storage rather than normal control storage, the contents of the latter executing the first line of microcode for a given macroinstruction. Activate the mechanism to connect to the shared bus only when necessary. In this manner, execution of each macroinstruction can begin one clock period earlier than with conventional control storage configurations.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to FIG. 1, a block diagram of a typical conventional control storage device is shown. A next instruction register 10 holds the instruction to be decoded with an entry point table 12 which generates an address pointing to the first line of the instruction's microcode. The output of the entry point table 12 is
On subsequent clock pulses from the system clock 16 after the valid contents of the next instruction register 10 are available,
Added to address register 14 of control store. After that clock pulse, the first line of encoded microcode is available as a pointer to the microcode contained in control store 18. The first line of microcode is shown schematically as a bit field 20. To access subsequent lines of microcode for macroinstructions, register 14 may be configured to increment the value it holds every clock period. Alternatively, additional sources for addressing control storage 18 may be provided in other ways. For example, control storage 18 may include, as is well known in the art,
It can be driven by a multiplexer sourced from the control store address register 14, a return stack, and a bit field from the microcode that controls the branch.

As is well known in the art, one or more registers (
(not shown) can be interposed, and especially if a pipeline method is used, at least two registers are used, one for rank 1 and one for rank 2. Therefore,
A minimum of three clock periods is required before rank 2 information is available at the output of the rank 2 register.

Referring now to FIG. 2, a block diagram of a control storage device in accordance with the present invention is shown.

The next instruction register 40 is the entry point table 42
Contains instructions decoded by . That is, the contents of next instruction register 40 address entry point table 42 via line 46.

However, unlike the conventional example, the entry point table 42 does not include a pointer pointing to the first line of microcode for the macro instruction being executed.

Instead, it contains a pointer to the second line of microcode for the macroinstruction being executed. Entry point table 42 may be comprised of sequential dedicated memory, random access memory, or a programmable logic array, as is well known in the art.

The first line of microcode for each macroinstruction is contained in entry control storage 48, which accesses the contents of next instruction register 40 via line 46 as well as entry point table 42. Alternatively, the system of FIG. 2 is described and claimed in pending U.S. patent application Ser. It can also be operated with additional control storage.

The execution of the second and subsequent lines of microcode will now be described, followed by a description of how to bring the first line of microcode into the pipeline earlier than is possible with conventional arrangements.

In the first clock period, the entry point table 42
The output of is clocked into the control storage address register 50 via line 52 and clock line 54 from the system clock 56. After the required access time has elapsed, the above output, which is a pointer to an address within vertical control store 58, is applied to vertical control store 58 via line 60. Subsequent microinstructions 3 use clock pulses from system clock 56 to increment the value stored in control storage address register 50, or to increment the output of control storage address register 50, as is well known in the art. This is obtained by driving line 6o with a multiplexer (not shown) included in the input, as well as a bit field from the microcode that controls the return stack and branches. After the required access time, the output of the vertical control store 58 is then provided via line 64 to the control store output line 62 where it is clocked into the rank l register in a second clock period by a clock pulse from the system clock 56. is input.

Some of the bit fields in the output of Rankle Cistero 6 are partially or fully decoded microcode, microcode bit field 700 rank 1
A microcode field section 68 is formed. In the preferred embodiment, another portion of the output of rank I register 66 is used as a pointer to address horizontal control store 72 through rank 74, but one skilled in the art will appreciate that the present invention functions properly. Understand that there is no special need for this. After the required access time, the output of horizontal control store 72 is routed via line 78 to rank 2 register 7.
It becomes possible to apply to the input of 6. Then, on the third clock period from system clock 56 via line 54, the output of horizontal control store 72 is applied to rank 2 register 76, which registers rank 2 of microcode bit field 7o.
It will be available as part 78. However, if you are a person skilled in the art,
It will be appreciated that in the third clock period N described above, it is the second rank of the first line of microcode that is being executed by the rank two register, rather than the rank two information.

Selected bit field 8o consisting of one or more bits in rank 1 bit field 68 in microcode field 7o is an entry control storage bag?
148 to execute the first line of microcode. The state of selected bit fields, decoded if necessary, is applied to an entry control storage enable (EC3) register 84 via line 82 each clock period from system clock 56.

The output of entry control store enable register 84 is provided via line 86 to each enable input of entry control store 48 and vertical control store 58. Input EN88 of entry control store 48 operates at a logic low and input EN90 of vertical control store 58 operates at a logic high.

Since entry control store 48 and vertical control store 58 both share control store output bus 62, their respective inputs EN and EN ensure that only one has control of the bus at any given time. Guarantee. This can be done, as is well known in the art, by multiplexing the two on bus 62 or by selectively disabling the output drivers of one or the other of vertical control store 58 and entry control store 48. It will be done. Most of the time, vertical control store 58 assumes control of the bus, which means that field 80 causes ECS register 84 to contain a logic high level (ie, "1"). However, when the next macro instruction is stored into the next instruction register 40,
Generally, during the execution of the second to last microinstruction of the currently executed macroinstruction, the entry control storage 4
8 takes control of the control store output bus 62 and provides the first line of microcode for the next macroinstruction onto the control store output bus 62. This process occurs at a faster clock period than the first line enters the output bus when entering the pipeline from the output of entry point table 42. In such a case, the instruction must be decoded in the entry point table 42 and the pointer must wait for the next clock cycle to be added to the control storage address register 5o. A pointer is then applied to the control store output line 62 before accessing the microcode from the vertical control store 58 and then allowing clocking into the runcle system 6.

Another selection bit field 91 operates via line 93 to inhibit clock pulses from entering the next instruction register 4o except during the period in which the next instruction is to be stored. This generates one or more clock pulses before bit field 80 enables entry control storage t48. Since timing is instruction dependent, those skilled in the art will recognize when the enable must occur for a given sequence of instructions.

To facilitate microbranching, operation of entry control store register 48 can be inhibited to continue execution of microinstructions from vertical control store 58. In a preferred embodiment, the results of the test used to make the micro-branch decision, shown schematically at 92, are used to inhibit entry control storage register 84 from selecting entry control storage W48. I can do it.

This feature is most important in executing macroinstructions containing less than three lines of macroinstructions.

If the number of lines of microinstructions is three or more, the system's microcoder can improve pipelining by providing instructions to fetch the next macroinstruction and then add it to one microinstruction line in the next instruction register. . But this, of course, cannot be done for instructions with fewer than three lines.

According to the present invention, even for a macroinstruction having two lines of microcode, a first pointer to the first line of microcode is passed through the control storage address register 50 to decode the instruction in the vertical control storage 58. While in progress, NOP space fillers can be inserted and performed with virtually no system downtime.

Those skilled in the art will recognize that the same apparatus that can reduce the execution time of a macroinstruction can also reduce the time required to execute a branch of the macroinstruction.

When performing a macro branch, the branch target is stored in the next instruction register 40, but the target macro instruction is stored in the target macro until the rank 1 portion of its first micromode appears on the control storage output line 62. Execution of the instruction cannot begin. According to the invention, accessing entry control storage 48 in the above case requires only one clock period. Other than the present invention,
Two clock periods are required to first access entry point table 42 and then to access vertical control storage 58 in one cycle.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a typical conventional control storage device. FIG. 2 is a block diagram of a control storage device constructed in accordance with the present invention. 42... Entry point table, 4th... Auxiliary (entry) control storage device, 58... Control storage device, 62... Control storage device output bus, 8°...
・Microcode display (selected bit field), 84
...Bus selection means (entry control storage device enable register. Procedural amendment (method) 1. Display of incident Patent Application No. 203896 of 1983 2
, Title of the invention: Auxiliary control storage device for improving the performance of cPU pipeline 3, Relationship with the amended party case: Applicant name: Tandem Computers Incorporated 4, Agent

Claims (1)

Claims: fil A central processing unit having hardware for executing instructions, including an entry point table and at least one control memory, which obtains microcode from the control memory and stores it in the control memory. Where a macroinstruction accesses a pointer in an entry point table used to feed a bus connected to an output line: Contains the first line of microcode for each macroinstruction, accessed by said microinstruction, and in which an auxiliary an output line selectively connected to bus selection means for selectively disconnecting the output line of the control storage device from the bus when the output line of the control storage device is selectively connected to the bus; An auxiliary control store, wherein said bus selection means corresponds to an indication in microcode indicating which of said control store or an auxiliary control store is to be connected to said bus.