JPH02201179A - Integrated circuit testing equipment - Google Patents

Abstract

PURPOSE:To execute a parallel action to simultaneously execute a test pattern for a logic and a test pattern for a memory by providing a pattern formatter part to select and edit the logic test pattern and memory test pattern. CONSTITUTION:A pattern formatter part 14 selectively edits the logic test pattern from a logic test pattern generating part 12 and the memory test pattern from a memory test pattern generating part 13 under the control of a pattern switching control signal from an address control part 11. A pin electronics part 15 received the test pattern to be selectively edited impresses the test patterns to respective pins of a DUT board 16 and, simultaneously, takes out the response. The taken-out response is compared with an expected value prepared in the test pattern in the formatter part 14 beforehand, and the quality is decided based on the result.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an integrated circuit testing device for testing the functions and performance of logic ICs (integrated circuits), memory ICs, etc. The present invention relates to an integrated circuit testing device capable of real-time pattern switching and parallel operation in which a logic test pattern (logic test pattern) and a memory test pattern (memory test pattern) function simultaneously.

[Conventional technology]

Conventionally, in order to test integrated circuits, for example, in the case of random logic integrated circuits (standard gates, calculators, clocks, chip microcomputers, microprocessors and peripheral elements, custom logic, gate arrays, etc.), the tests shown in Figure 3 are used. A similar test equipment configuration is used. The test equipment in Figure 3 is
It consists of an address control section 31, a logic test pattern generation section 32, and a pin electronics section 33, and the address control section 31 generates pattern control signals including timing signals necessary for logic test pattern generation.

The logic test pattern generation section 32 generates a logic test pattern for the IC under test (DUT) under the control of the pattern control signal from the address control section 31, and generates a logic test pattern for the IC under test (DUT) via the pin electronics section 33 to the OUT board 34 to which the DtlT is attached. input bin.

OUT's response to this logic test pattern is OU
Pin electronics section 3 from output bin of T board 34
3 and compared with the expected value in the logic test pattern, and evaluation is performed based on the comparison data.

On the other hand, in the case of a memory IC, as shown in FIG.
, a test device consisting of a pin electronics section 43 was used. This test device has the same configuration and functions as the logic test device shown in FIG. 3, except that it uses a memory test pattern generator 42 that generates patterns for memory tests in place of the logic test pattern generator 32. has.

Furthermore, the test apparatuses shown in FIGS. 3 and 4 are combined as shown in FIG. A general-purpose integrated circuit test in which a memory test system consisting of an address control section 53 and a memory test pattern generation section 54 is switched by a setting switching device 55 and connected to a pin electronics section 56, and can be used for both logic testing and memory testing. equipment is also used.

[Problem to be solved by the invention]

However, in any case, the conventional integrated circuit test equipment described above can only perform logic tests or memory tests at a time.
Full custom, semi-custom, user programmable f
Conventional methods are used to test integrated circuits that have both memory and logic functions (such as integrated circuits for specific applications such as In general-purpose equipment, switching between logic patterns and memory patterns can only be performed by switching test patterns as shown in Figure 2 (b), and this switching takes time, making it difficult to test integrated circuits such as the one described above. This method is difficult to apply in practice because it takes a long time. Therefore, testing of this type of integrated circuit requires a specially prepared dedicated testing device, which poses a problem of extremely high costs.

This invention was made in view of the above circumstances, and its purpose is to be able to switch test patterns for each bin in real time, and to perform parallel operations that simultaneously execute test patterns for logic and test patterns for memory. possible,
An object of the present invention is to provide a general-purpose integrated circuit testing device suitable for testing ASICs.

[Means to solve the problem]

In order to achieve the above object, the integrated circuit testing device of the present invention has the following features:
an address control section that generates various control signals necessary for test pattern generation according to a set sequence; a logic test pattern generation section that generates logic test patterns according to the pattern control signals from this address control section; A memory test pattern generation section that generates a test pattern for memory, a pattern formatter section that selects and edits the logic test pattern and memory test pattern according to the pattern switching control signal, and an integrated circuit under test (DUT) are installed. [This device is equipped with a pin electronics section that supplies the test pattern output from the pattern formatter section to the IUT board and captures the response of OUT to the application of the test pattern.

[Effect]

In the integrated circuit testing apparatus of the present invention having the above configuration, the address control section has a sequence program prepared for the IC under test, and uses this program to generate various control signals necessary for generating test patterns;
It is supplied to the logic test pattern generation section, memory test pattern generation section and pattern formatter section. The logic test pattern generation section and the memory test pattern generation section operate various control functions simultaneously based on control information of various pattern control signals from the address control section.
A logic test pattern and a memory test pattern are respectively supplied to the pattern formatter section.

The pattern formatter section selectively edits these logic test patterns and memory test patterns by executing a pattern control function under the control of the pattern switching control signal, and supplies the test patterns thus selectively edited to the pin electronics section. . The pin electronics section applies a test pattern to each bin of the OUT board and retrieves the OUT's response to the application of the test pattern.

The response of the DUT extracted in this way is compared in advance with the expected value prepared in the test pattern in the pattern formatter section, and a pass/fail judgment is made based on the result.

In addition, the data of the logic test pattern and memory test pattern transferred to the pattern formatter section can be used individually to create a logic test pattern or It is also possible to operate the test pattern independently, and it is also possible to operate the logic test pattern and the memory test pattern in parallel.

Furthermore, control functions using various control signals are executed simultaneously for the logic test pattern generation section and the memory test pattern generation section, and switching between logic test patterns and memory test patterns is performed instantly, making it possible to change test patterns in real time. As a result, a sequence waveform of a test pattern as shown in FIG. 2 is also possible, and even an integrated circuit such as an ASNC having both a memory function and a logic function can be easily and efficiently tested.

〔Example〕

Hereinafter, an embodiment of the integrated circuit testing apparatus of the present invention will be described with reference to FIG.

The integrated circuit testing apparatus of the illustrated embodiment includes an address control section 111, a logic test pattern generation section 12, a memory test pattern generation section 13, and a pattern formatter section 14.
, pin electronics section 15, and DUT board 16
It is made up of. Address control section ■ is DUT
Various control signals are generated by a sequence program corresponding to the IC under test (DUT) installed on the board 16,
The signal is supplied to a logic test pattern generation section 12, a memory test pattern generation section 13, and a pattern 7 pattern generation section 14.

The logic test pattern generator 12 is composed of a sequential pattern generator or a random pattern generator, and generates pattern iii+! A logic test pattern is generated under the control of the +1 signal and supplied to the pattern formatter section 14. Memory test pattern generator 1
3 is an algorithmic pattern generator which generates a memory test pattern under the control of a pattern control signal and also supplies it to the pattern formatter section 14.

The pattern formatter section 14, under the control of the pattern switching control signal from the address control section l],
Select and edit the logic test pattern from the logic test pattern generation section 12 and the memory test pattern from the memory test pattern generation section 13, and generate a test pattern corresponding to each OUT installed on the 111T board 16, 15. The pin electronics section 15 is comprised of a large number of interface circuit boards, one block for each bin of the DUT board 16, and applies the data of each bin of the test pattern from the pattern formatter section to each bin of the DUT board 16. .

The response of the DUT to the application of the test pattern is taken out by the pin electronics section 15 and compared with expected value data prepared in advance in the test pattern by the pattern 7-ohmatsu section 14, and the quality of the DUT is determined based on the result.

The logic test pattern generation section 12 and the memory test pattern generation section 13 respectively store various logic test patterns and various memory test patterns in advance, and the pattern formatter section 14 stores these in accordance with the program of the address control section 11. Select and edit the logic test pattern and memory test pattern as appropriate for each DUT.
By creating test patterns according to the However, it can be done efficiently and easily.

Incidentally, in this embodiment, the time required to execute the l-step memory test pattern or logic test pattern is extremely short, about 20 ns, and the pattern formatter section 14 outputs such logic test patterns and memory test patterns simultaneously and in parallel. Alternatively, it is also possible to output the logic test pattern and memory test pattern by switching them at high speed, supply them to the logic section and memory section of an ASIC, etc. (see Figure 2 fa)), and test their response operations. It is possible to test various integrated circuits, including evaluation, in an extremely short time.

〔Effect of the invention〕

As explained above, the integrated circuit testing device of the present invention has the following features:
an address control section that generates various control signals necessary for test pattern generation according to a set sequence; a logic test pattern generation section that generates logic test patterns according to the pattern control signals from this address control section; A memory test pattern generation section that generates a test pattern for memory, a pattern formatter section that selects and edits the logic test pattern and memory test pattern according to a pattern switching f#q control signal, and an integrated circuit under test (DUT). The configuration is equipped with a pin electronics section that supplies the test pattern output from the pattern formatter section to the DUT board to be mounted, and captures the OUT response to the application of the test pattern, ensuring versatility and high speed. January C, including logic IC, ASIC, 1
A wide variety of integrated circuits for various applications can be tested with high efficiency using a single test device, and there is no need to install separate dedicated test devices.As a result, it is possible to downsize equipment and reduce costs, increasing efficiency. Combined with improvements, this can make a significant contribution to integrated circuit production.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the integrated circuit testing apparatus of the present invention, FIG. 2 fat is a test pattern waveform diagram showing an example of its operation mode, and FIG. FIGS. 3 and 4 are test pattern waveform diagrams showing the operation mode of an example of a test device, and FIG. It is a block diagram of an example of a general-purpose integrated circuit testing device according to the prior art. 11... Address control section, 12... Logic test pattern Generation section, !3... Memory test pattern generation section, 14... Pattern formatter section, 15...・・・・Pin electronics department, 16・・・・・・・・・・・・DUT
Board, DUT......Integrated circuit under test.

Claims (1)

[Claims] (1) An address control section that generates various control signals necessary for test pattern generation according to a set sequence; A logic test pattern generation section that generates logic test patterns according to pattern control signals from this address control section; The above pattern a memory test pattern generation section that generates a test pattern for the memory according to the control signal; a pattern formatter section that selects and edits the logic test pattern and the memory test pattern in real time (without switching waiting time) according to the pattern switching control signal; an integrated circuit comprising: a pin electronics section that supplies the test pattern output from the pattern formatter section to the DUT board on which the integrated circuit under test (DUT) is mounted, and captures the response of the DUT to the application of the test pattern; Circuit testing equipment.