JPH08114649A - Apparatus and method for testing semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To shorten the developing period, reduce the cost, and effectively use engineering (CAE) data for a computer by comparing the operation result by an actual chip simulator with a logical simulation result. CONSTITUTION: In a CAE1 for logical simulation, a test pattern generating circuit 4 forms an input pattern necessary for a test and a semiconductor model 3 is simulated on the basis of the input pattern and the result of simulation is stored in a measuring part 5. The input pattern formed by the pattern generating circuit 4 is also sent to an actual chip simulator 2 to be processed by a pattern controller 7 and a timing generator 8 to be converted into an electric signal by a signal generator 9. A test object (MCM) 6 is operated by this electric signal and this operation result is sent to the measuring part 5. The expect value by the simulation result of the model 3 and the actual operation result of the MCM6 are compared in the measuring part 5 to judge the quality of the MCM6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test technology for semiconductor integrated circuit devices, and more particularly to CAE for logic simulation.
TECHNICAL FIELD The present invention relates to a technique effectively applied to a test device and method of a semiconductor integrated circuit device in which a test device using (Computer Aided Engineering) can improve the testability of a functional test by interfacing with an actual chip simulator.

[0002]

2. Description of the Related Art Conventionally, in a test technique for a semiconductor integrated circuit device, an MC as an example of the semiconductor integrated circuit device is used.
The function test of M (Multi Chip Module) is performed by, for example, a test program, a test microcomputer,
It is performed by using a dedicated test jig corresponding to an MCM to be tested, which is composed of a test pattern generating circuit, a measuring unit, and the like.

That is, in the test method using this dedicated test jig, a test circuit is provided around the MCM to be tested, and in this test circuit, a ROM containing a test program and a test program for executing the test program are provided. A microcomputer microprocessor is provided.

First, a test signal is input to the MCM through the test pattern generation circuit of the test circuit, and the MC
The M returns the output signal corresponding to this test signal to the measurement section of the test circuit, and the measurement section determines the timing and voltage level of this signal, and compares it with the preset expected value to test the MCM. Be seen.

[0005]

However, in the test technique using the dedicated test jig as described above, since the test jigs corresponding to the different types of semiconductor integrated circuit devices are required, the hardware and It takes time to develop software, requires a lot of manpower, and raises the cost of the test jig.

When a semiconductor integrated circuit device is designed by a CAE or the like in which a manual work is aided by a computer in each design process as in recent years, the design data existing on the CAE is utilized for a test. There is also the problem of being unable to do so.

Therefore, the object of the present invention is to shorten the development period, reduce the cost, and make the CAE data effective in consideration of not using a dedicated test jig as in the past, and considering a consistent test method from CAE. Test apparatus and method for semiconductor integrated circuit device, which can be utilized, improved defective portion identification rate of semiconductor integrated circuit device, solved easiness of test circuit change, and improved testability of functional test using CAE To provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the test apparatus for a semiconductor integrated circuit device according to the present invention is characterized by using a CAE, and a CAE for logic simulation for creating a test circuit for the semiconductor integrated circuit device to be tested, and this CAE. A real chip simulator of a semiconductor integrated circuit device connected to a CAE for logic simulation, a semiconductor integrated circuit device to be tested is mounted on the real chip simulator, and the operation result and the operation by the test circuit of the CAE for logic simulation are mounted. The function of the semiconductor integrated circuit device is measured by comparing the result with the result.

In this case, the logic simulation CA
The test circuit E is composed of a test pattern generating means and a measuring means, and particularly when a semiconductor integrated circuit device is selected, a semiconductor model having the same function as the semiconductor integrated circuit device based on the information of the test pattern generating means. Is used as the expected value, or information equivalent to this is input from the outside, and the result value of operating the semiconductor integrated circuit device in the actual chip simulator by the information of the test pattern generating means is returned to the measuring means. In this measuring means, the expected value obtained by the simulation result is compared with the result value obtained by operating the semiconductor integrated circuit device.

Further, particularly in the case of evaluating the manufacturing stage of the semiconductor integrated circuit device, based on the result value of operating the semiconductor integrated circuit device in the actual chip simulator,
When changing the parameter values of the test pattern generating means and the semiconductor model, or when selecting in the analog function, measure the result value of operating the semiconductor integrated circuit device in the actual chip simulator with a semiconductor tester or the like. It is the one.

Further, according to the semiconductor integrated circuit device testing method of the present invention, a test pattern generating means for the semiconductor integrated circuit device to be tested is created on the logic simulation CAE, and an actual chip simulator capable of interfacing with the logic simulation CAE. To operate the semiconductor integrated circuit device and return the output result to the measuring means created on the CAE for logic simulation. In this measuring means, a semiconductor model having the same function as the semiconductor integrated circuit device on the CAE for logic simulation is obtained. The function measurement of the semiconductor integrated circuit device is performed by comparing the simulation result used with the operation result of the semiconductor integrated circuit device in the actual chip simulator.

[0014]

According to the above-described semiconductor integrated circuit device testing apparatus and method, in addition to the actual chip simulator of the semiconductor integrated circuit device to be tested, a logic simulation CA for creating a test circuit of this semiconductor integrated circuit device is also provided.
By having E, the test circuit of the semiconductor integrated circuit device to be tested can be created on the CAE for logic simulation.

That is, CAE for logic simulation
Then, a test circuit is created, and this test circuit includes a test pattern generating means and a measuring means. In this test pattern generating means, a signal required for the test is created, and in the measuring means, the signal output from the actual chip simulator is measured, and the expected value of the test is stored in this measuring means. Compare with the output of the chip simulator.

On the CAE for logic simulation, a semiconductor model of a semiconductor integrated circuit device is simulated and the result is used as an expected value, or information corresponding to this is externally input and used as an expected value. .

On the other hand, the real chip simulator receives a signal required for a test from the CAE for logic simulation, generates a signal corresponding to the signal, and operates the semiconductor integrated circuit device. The signal resulting from this operation is output to the CAE for logic simulation or the semiconductor tester. The signal is output as it is to the semiconductor tester.

In the semiconductor tester, the signal received from the real chip simulator or the real chip is measured, and the simulation result received from the logic simulation CAE in this case is used as an expected value.

From the above, the CA for logic simulation
In the measuring means of E, by comparing the operation result by the semiconductor integrated circuit device in the real chip simulator and the expected value by the CAE for logic simulation,
The quality of the semiconductor integrated circuit device can be determined.

Further, by changing the parameter values of the test pattern generating means and the semiconductor model on the basis of the operation result of the semiconductor integrated circuit device in the actual chip simulator, it is possible to evaluate the semiconductor integrated circuit device at the production stage. Further, by measuring the operation result of the semiconductor integrated circuit device with the semiconductor tester, it is possible to perform pass / fail selection in the analog function of the semiconductor integrated circuit device.

As a result, the logic simulation CA
By effectively utilizing the design data of E, it is possible to shorten the period for creating the test circuit of the semiconductor integrated circuit device to be tested, and to easily change the test circuit,
Furthermore, the cost for each product can be reduced compared to the conventional production of a dedicated test jig.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a functional block diagram showing a test device for a semiconductor integrated circuit device which is Embodiment 1 of the present invention.

First, the configuration of the test device for the semiconductor integrated circuit device of this embodiment will be described with reference to FIG.

The semiconductor integrated circuit device test apparatus according to the present embodiment is a semiconductor integrated circuit device test apparatus using, for example, CAE, which is a logic simulation CA for creating a test circuit of a semiconductor integrated circuit device to be tested.
E1 and the real chip simulator 2 of the semiconductor integrated circuit device connected to the logic simulation CAE1. The operation result by the real chip simulator 2 is compared with the operation result by the logic simulation CAE1 to compare the semiconductor integrated circuit. The function of the device is measured.

The CAE 1 for logic simulation includes a semiconductor model 3 having a function equivalent to that of a semiconductor integrated circuit device,
It is composed of a test pattern generating circuit (test pattern generating means) 4 as a test circuit and a measuring section (measuring means) 5. The test pattern generation circuit 4 creates input patterns and timing information necessary for the test, outputs this test information to the real chip simulator 2, and uses this test information to generate the semiconductor model 3
Is simulated.

Further, in the measuring section 5, the simulation result of the semiconductor model 3 is treated as an expected value of the test, and in the measuring section 5, comparison with the output pattern and timing information output from the actual chip simulator 2 is carried out. Then, the semiconductor integrated circuit device of the actual chip simulator 2 is measured.

Incidentally, this CAE for logic simulation is used.
In No. 1, the test patterns, expected values, etc. in this are all CAE data, and are not owned by individual circuits.

The real chip simulator 2 includes an MCM (semiconductor integrated circuit device) 6 to be tested and the MCM 6
Pattern controller 7 for simulation of
It is composed of a timing generator 8 and a signal generator 9. In this real chip simulator 2, the input pattern and timing information inputted from the CAE 1 for logic simulation are received, and an electric signal matching them is generated through the pattern controller 7, the timing generator 8 and the signal generator 9.

The MCM 6 is operated by electric signals from the timing generator 8 and the signal generator 9, and the output pattern and timing information as the result of this operation are output to the CAE 1 for logic simulation. Note that this MCM6 has several to several tens of ICs (In
integrated circuit) Chips are connected to each other in the same package to form one module.

Next, regarding the operation of this embodiment, M
A case of measuring the function of the CM 6 will be described.

First, in the CAE 1 for logic simulation, the test pattern generating circuit 4 creates the input pattern and timing information required for the test. And
The semiconductor model 3 is simulated by this input pattern and timing information, and the result is stored in the measurement unit 5 as an expected value of the MCM 6 which is the test target of the real chip simulator 2.

On the other hand, the input pattern and timing information created by the test pattern generating circuit 4 of the CAE 1 for logic simulation are sent to the real chip simulator 2.
Then, in the actual chip simulator 2, the input pattern and the timing information are received, processed by the pattern controller 7 and the timing generator 8, and then converted into an electric signal by the signal generator 9.

Further, the MCM 6 to be tested is actually operated by this electrical signal, and the output pattern and timing information as the result of this operation are sent from the real chip simulator 2 to the measuring section 5 of the CAE 1 for logic simulation. Then, in the measuring unit 5, the expected value based on the simulation result of the semiconductor model 3 and the actual MC
The output pattern and timing information as the operation result of M6 are compared.

As a result, in the function measurement of the MCM 6, it is possible to select the good product or the defective product of the MCM 6 by the function test based on the quality judgment based on the comparative measurement by the measuring unit 5.

Therefore, according to the test apparatus for the semiconductor integrated circuit device of the present embodiment, the test pattern generation circuit 4 as the test circuit of the MCM 6 to be tested on the CAE 1 for logic simulation connected to the real chip simulator 2. And the measurement unit 5 is created to compare the operation result of the MCM 6 in the real chip simulator 2 with the expected value of the operation result of the semiconductor model 3 in the CAE 1 for logic simulation in the measurement unit 5 of the CAE 1 for logic simulation. By MCM6
It is possible to measure the function of the quality selection.

In this case, the test circuit generated by the test pattern generating circuit 4 and the measuring section 5 can be created on the CAE1 for logic simulation. Therefore, the design data by the CAE1 for logic simulation can be effectively utilized and the test circuit can be further used. Not only can it be easily created, but the time for creating this test circuit can be shortened. Further, the cost required for each MCM 6 can be reduced as compared with the case where a conventional dedicated test jig is created.

(Embodiment 2) FIG. 2 is a functional block diagram showing a test device for a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

The test apparatus for the semiconductor integrated circuit device according to the present embodiment is the test apparatus for the semiconductor integrated circuit device using CAE as in the case of the first embodiment, and is the MCM to be tested.
(Semiconductor integrated circuit device) 6 is composed of a logic simulation CAE 1a for creating a test circuit and an MCM 6 real chip simulator 2 connected to the logic simulation CAE 1a.
The point is that information corresponding to the simulation result of the semiconductor model in the first embodiment is input from the outside.

That is, the CAE 1a for logic simulation of this embodiment is composed of a test pattern generating circuit (test pattern generating means) 4a as a test circuit and a measuring section (measuring means) 5a, as shown in FIG. The expected value on the logic simulation CAE 1a can be set not from the simulation result of the semiconductor model but from the outside of the CAE 1a for logic simulation, information equivalent to the simulation result of the semiconductor model can be set.

Therefore, also in this embodiment, by comparing the operation result of the MCM 6 in the real chip simulator 2 with the expected value input from the outside to the CAE 1a for logic simulation in the measuring section 5a of the CAE 1a for logic simulation. It is possible to perform a function measurement of pass / fail selection of the MCM 6, and even in this case, a test circuit can be created on the CAE 1a for logic simulation as in the case of the first embodiment. Therefore, effective use of design data by the CAE 1a for logic simulation is possible. It is possible to facilitate the production of the test circuit, shorten the production period, and reduce the cost.

(Embodiment 3) FIG. 3 is a functional block diagram showing a test device for a semiconductor integrated circuit device which is Embodiment 3 of the present invention.

The test apparatus for a semiconductor integrated circuit device according to the present embodiment is a test apparatus for a semiconductor integrated circuit device using CAE as in the first and second embodiments, and is an MCM (semiconductor integrated circuit device) to be tested. 6 includes a logic simulation CAE 1b for creating a test circuit 6 and an MCM 6 real chip simulator 2 connected to the logic simulation CAE 1b.
The difference is that the function measurement for evaluation in the preparation stage is performed, not the function measurement for quality selection of the MCM 6 as in the first and second embodiments.

That is, as shown in FIG. 3, the CAE 1b for logic simulation of this embodiment has a semiconductor model 3b of the MCM 6, a test pattern generating circuit (test pattern generating means) 4b as a test circuit, and a measuring section (measuring means). In addition to 5b, a parameter changing section 10 is further added, and the result of comparison by the measuring section 5b is fed back to the test pattern generating circuit 4b and the semiconductor model 3b, and these parameters are changed by the parameter changing section 10. Thus, the parameters of the test pattern generating circuit 4b and the semiconductor model 3b can be set.

Therefore, in the present embodiment, in the measuring section 5b of the CAE 1b for logic simulation, the operation result of the MCM 6 in the real chip simulator 2 and the semiconductor model 3 in the CAE 1b for logic simulation are shown.
By comparing the operation result of b with the operation result of b, it is possible to perform the functional measurement of the evaluation in the production stage of the MCM 6, and in this case as well, similar to the first and second embodiments, the test circuit is produced on the CAE 1b for logic simulation. Therefore, in addition to effective use of design data by the CAE1b for logic simulation, facilitation of test circuit creation and shortening of the creation period, and cost reduction, it becomes easier to identify defective parts of the MCM and to perform testing. The circuit can be easily changed.

(Embodiment 4) FIG. 4 is a functional block diagram showing a test device for a semiconductor integrated circuit device which is Embodiment 4 of the present invention.

The semiconductor integrated circuit device test device of this embodiment is a semiconductor integrated circuit device test device using CAE as in the case of the first to third embodiments.
It is composed of a CAE1c for logic simulation that creates a test circuit of an M (semiconductor integrated circuit device) 6 and a real chip simulator 2 of the MCM6 connected to the CAE1c for logic simulation. The point is to perform function measurement for selection of analog functions.

That is, the test apparatus of this embodiment has the configuration shown in FIG.
In addition to the logic simulation CAE 1c and the real chip simulator 2, as shown in FIG.
CAE for logic simulation
1c has a semiconductor model 3 with the same function as MCM6
c and a test pattern generation circuit (test pattern generation means) 4c as a test circuit, and the semiconductor tester 11 has an MCM12 equivalent to the MCM6 to be tested by the real chip simulator 2 and the first embodiment. A measurement section (measurement means) 13 as a test circuit equivalent to the measurement section of the CAE for logic simulation is provided.

As a result, the CA for logic simulation is
At E1c, the semiconductor model 3c is simulated by the input pattern and timing information created by the test pattern generation circuit 4c, the result is sent to the measuring unit 13 of the semiconductor tester 11, and the input pattern and timing information is sent to the real chip simulator 2. Send, MC
The operation result of M6 is sent to the measuring unit 13 of the semiconductor tester 11, and the measuring unit 13 compares the expected value based on the simulation result of the semiconductor model 3c with the output pattern and timing information as the actual operation result of the MCM6. It is possible to perform digital function measurement.

At the same time, CAE1 for logic simulation
The input pattern and timing information are directly input from the test pattern generating circuit 4c of the semiconductor tester c of the MCM1 of the semiconductor tester 11.
It is also possible to perform analog function measurement such as a current value that cannot be measured by simulation.

Therefore, in this embodiment, in the measuring section 13 of the semiconductor tester 11, the actual chip simulator 2 is used.
By comparing the operation result of the MCM 6 in the above and the operation result of the semiconductor model 3c in the CAE 1c for logic simulation, it is possible to perform a digital pass / fail function measurement of the MCM 6 and at the same time, perform an analog operation such as a current value. Functional measurement can also be performed, and in this case, as in the first to third embodiments, the logic simulation C
Since a test circuit can be created on the AE1c,
In addition to effective utilization of design data by the CAE1c for logic simulation, facilitation of test circuit creation and shortening of creation time, cost reduction, and easiness of test circuit change, the CAE1c for logic simulation and the semiconductor tester 11 are combined. A new test method by can be realized.

Although the invention made by the present inventor has been specifically described based on the first to fourth embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, with respect to the test apparatus for the semiconductor integrated circuit device of the above-described embodiment, the case where the MCM 6 as an example is used as a test target has been described, but the present invention is not limited to the above-mentioned embodiment, and other embodiments. The present invention is also widely applicable to semiconductor integrated circuit devices, particularly semiconductor integrated circuit devices having a more multifunctional and complicated structure.

[0054]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). CAE for logic simulation for creating a test circuit of a semiconductor integrated circuit device to be tested
And an actual chip simulator of the semiconductor integrated circuit device connected to the CAE for logic simulation, the operation result by the actual chip simulator and the operation result by the test circuit of the CAE for logic simulation are compared, and the semiconductor integrated circuit Since the function of the circuit device can be measured, the test circuit of the semiconductor integrated circuit device can be created on the CAE for logic simulation.

(2) In the above (1), the simulation result using the semiconductor model based on the information of the test pattern generating means of the CAE for logic simulation is used as an expected value, or information corresponding to this is input from the outside. By comparing the expected value with the result value obtained by operating the semiconductor integrated circuit device in the real chip simulator based on the information of the test pattern generating means, the design data of the CAE for logic simulation in the function measurement of the selection of the semiconductor integrated circuit device. Can be used effectively and a test circuit can be easily created, the time required for creating this test circuit can be shortened, and the cost can be reduced compared to the case where a dedicated test jig is created. .

(3) In the above (1), by changing the parameter values of the test pattern generating means and the semiconductor model based on the result value of operating the semiconductor integrated circuit device in the actual chip simulator, the semiconductor integrated circuit It is possible to perform evaluation function measurement at the circuit device creation stage, and in this case, in addition to the effect of (2) above, it is easier to identify defective parts of the semiconductor integrated circuit device and the test circuit is changed. Is easily possible.

(4) In the above (1), by measuring the result value of the operation of the semiconductor integrated circuit device in the actual chip simulator by the semiconductor tester, particularly the function of digital selection of the semiconductor integrated circuit device can be measured. In addition to the effect of (3) above, in addition to the effect of (3), a new test method can be realized by combining the CAE for logic simulation and the semiconductor tester. It will be possible.

(5) Due to the above (1) to (4), the development period is shortened and the development is shortened by eliminating the need for the conventional dedicated test jig and considering the consistent new test method from CAE. A semiconductor capable of reducing costs, effectively utilizing CAE data, improving the defect identification rate of semiconductor integrated circuit devices, and improving the ease of changing test circuits, and improving the testability of functional tests using CAE. A test technique for an integrated circuit device can be obtained.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a test device for a semiconductor integrated circuit device that is Embodiment 1 of the present invention.

FIG. 2 is a functional block diagram showing a test device for a semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 3 is a functional block diagram showing a test device for a semiconductor integrated circuit device which is Embodiment 3 of the present invention.

FIG. 4 is a functional block diagram showing a test device for a semiconductor integrated circuit device which is Embodiment 4 of the present invention.

FIG. 5 is a functional block diagram showing a dedicated test jig for a semiconductor integrated circuit device, which is an example of a conventional technique.

[Explanation of symbols]

1, 1a to 1c CAE for logic simulation 2 Real chip simulator 3, 3b, 3c Semiconductor model 4, 4a to 4c Test pattern generating circuit (test pattern generating means) 5, 5a, 5b Measuring unit (measuring means) 6 MCM (semiconductor) Integrated circuit device) 7 Pattern controller 8 Timing generator 9 Signal generator 10 Parameter changing unit 11 Semiconductor tester 12 MCM 13 Measuring unit (measuring means)

Claims (6)

[Claims] 1. A test apparatus for a semiconductor integrated circuit device using a CAE, comprising: a logic simulation CAE for creating a test circuit of the semiconductor integrated circuit device to be tested; and a logic simulation CAE connected to the CAE. A real chip simulator of the semiconductor integrated circuit device is provided, and the function of the semiconductor integrated circuit device is measured by comparing the operation result of the real chip simulator with the operation result of the test circuit of the CAE for logic simulation. A test device for a semiconductor integrated circuit device, which is characterized by: 2. A test circuit of the CAE for logic simulation is composed of a test pattern generating means and a measuring means, and a semiconductor model having a function equivalent to that of the semiconductor integrated circuit device based on the information of the test pattern generating means is used. Using the simulation result as an expected value, the result value obtained by operating the semiconductor integrated circuit device in the real chip simulator based on the information of the test pattern generating means is returned to the measuring means, and the expected value according to the simulation result is obtained in the measuring means. 2. The test apparatus for a semiconductor integrated circuit device according to claim 1, wherein the test result is compared with a value obtained by operating the semiconductor integrated circuit device. 3. The test apparatus for a semiconductor integrated circuit device according to claim 2, wherein information corresponding to an expected value obtained from a simulation result of the semiconductor integrated circuit device is input from the outside. 4. The parameter value of the test pattern generating means and the semiconductor model is changed based on a result value of operating the semiconductor integrated circuit device in the real chip simulator. A test device for a semiconductor integrated circuit device according to claim 1. 5. A semiconductor tester is used to measure a result value of operating the semiconductor integrated circuit device in the actual chip simulator.
A test device for a semiconductor integrated circuit device according to claim 1. 6. A method of testing a semiconductor integrated circuit device using a CAE, comprising forming a test pattern generating means of the semiconductor integrated circuit device to be tested on the CAE for logic simulation, and then the CAE for logic simulation.
The semiconductor integrated circuit device is operated by an actual chip simulator capable of interfacing with the semiconductor integrated circuit device, and the output result is returned to the measuring means created on the CAE for logic simulation. In this measuring means, the semiconductor integrated circuit device is operated on the CAE for logic simulation. Simulation results using a semiconductor model having the same function as the circuit device,
A method for testing a semiconductor integrated circuit device, comprising: comparing a result of operation of the semiconductor integrated circuit device in the real chip simulator to measure a function of the semiconductor integrated circuit device.