JPH09171056A - Test design method and device, test method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a test device capable of determining a test specification for judging good or bad of a product as a state reducing test design manday by producing each design specification and reflecting the test condition controlled by a test system to the test condition memorized in advance. SOLUTION: Included as elements are a test board input processing part 1, a test board figure producing part 2, a test program producing part 3, a test specification producing part 4, a test content template memory part 5, a test condition data memory part 6, a test hard model data memory part 7, a test method memory part 8, a grammar model memory part 9, an actual machine control data extraction part 10, an actual machine control data register processor part 11. By this, a test designer only needs to determine the condition considering the function of part of products, setting of test conditions considering an LSI tester becomes unnecessary, a test program, a test board and a test specification are automatically produced and design manday can be reduced.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an LS as a product.
The present invention relates to a test design method and an apparatus therefor, which determines a test specification for determining the quality of a product when the operation test is performed in the shipping inspection of I, and further to a test method and the apparatus.

[0002]

2. Description of the Related Art When an operation test is carried out in the shipping inspection of an LSI as a product, the test specifications usually include the function and test order of the product, test items, operating conditions, environmental conditions,
Pass / fail judgment condition, expected value (test result, expected operation)
It consists of. In this, the function defines the operation of the product and describes the specific contents of the operation test. Conventionally, in these test specifications, after the function of the product is subdivided based on the product standard and the experience of the product designer, after determining the necessary test conditions for each function, designing the necessary peripheral circuits, The fact is that the test specifications and test boards (circuits that interface with the test system) for the product were created by putting these together.

By the way, in the past, as an attempt to reduce the number of test design steps, as described in Japanese Patent Application Laid-Open No. 4-276652, the product standard of the LSI is used as input data.
A method of creating a product standard table, a test specification, a test peripheral circuit diagram (test board), and a test program is known. Further, as described in JP-A-1-195381, a test specification described in a dedicated test description language is once converted into an intermediate language, and the intermediate language is converted into a test program for a specific test system. A method of creating a test board and a test specification is also known.

[0004]

As described above, in the past, the test designer considers the test condition and the test peripheral circuit for each function of the DUT (test target), and performs the test based on these. I am creating a program and a test board, but since this work involves a huge amount of work, not only the development man-hours increase, but also the possibility of human error in the test specifications is increasing. In particular, the peripheral circuits for testing have different circuit configurations for each function, and they are grouped on a single test board that interfaces with the test system. It is necessary to consider the control conditions such as the selection of the target route. Further, since the number of functions realized in one product is increasing year by year, it is the actual situation that the amount of test design work is increasing accordingly.

On the other hand, in the case of the above-mentioned Japanese Patent Laid-Open No. 4-276572, it is necessary to make the relation between the product standard, the test specification and the test board circuit into a rule.
There are many parts that depend on the type of test system and LSI product, and when the target product is a large variety of products, it is necessary to review the rules for each product type, which makes it difficult to develop the product. Is. In addition, Japanese Patent Laid-Open No. 1-
According to Japanese Patent Laid-Open No. 195381, since it is assumed that the test engineer inputs the test conditions, the test order, and the test board circuit diagram, the test engineer not only tests the hardware of the tester but also the test specifications and the test board. It was necessary to create a test specification while being aware of the relationship of the LSI tester.

The first object of the present invention is to provide LS as a product.
There is provided a test design method and an apparatus thereof, which can determine a test specification for judging quality as a product when the operation test is performed in the shipping inspection of I as a state where the test design man-hour is reduced. A second object of the present invention is to determine a test specification for judging whether the product is good or bad when the operation test is performed in the shipping inspection of the LSI as the product, in a state where the test design man-hours are reduced. , A test method capable of testing the LSI and a device therefor are provided.

[0007]

The first purpose is basically to store a test condition for each function of an LSI as a test target and a test peripheral circuit for realizing the function as an input result. At the same time, the hardware specification data of the test system for inspecting the LSI and the grammar rules of the program for controlling the test system are stored, and based on the input result, the hardware specification data and the grammar rule. Based on the input result of the test program input for each function, a test board that interfaces the above test system and the above LSI,
By generating test conditions, test peripheral circuits, and design specifications of the test system control program based on the above input results, while reflecting the test conditions adjusted by the test system in the test conditions stored in advance, The device configuration is achieved by an input unit for inputting a test condition and a test peripheral circuit for realizing the function for each function of the LSI as a test target, as its constituent elements, and the input unit. Input result storage means for storing the input test conditions for each function and the test peripheral circuit as input results, specification data storage means for storing the hardware specification data of the test system for inspecting the LSI, and the test system A grammar rule storing means for storing a grammar rule of a program for controlling A test program generating means for generating a test program based on the software specification data and the grammar rules; and a means for generating a test board that interfaces the test system with the LSI based on the input result input for each function. , A test condition, a test peripheral circuit, a specification generation unit for generating a design specification of a test system control program based on the input result, and a test condition adjusted by the test system as a pre-stored test condition. It is achieved by configuring to include means for reflecting.

The second purpose is that the test condition and the test peripheral circuit for realizing the function are stored as the input result for each function of the LSI as the test target, and based on the input result. A test board for interfacing the test system with the LSI is generated, and board control data for selecting a path on the test board necessary for each test is generated, and the test condition input result and the board control are generated. When the LSI is tested for each function based on the control code of the test equipment generated based on the data, the test peripheral circuits are divided into partial circuits, and the isomorphism judgment is performed by circuit merging of all pins of the LSI. When generating a test board,
After the circuit connection information is analyzed, it is stored based on the analysis result in association with the component and the signal line to which the component is connected, and the feature of each component is represented based on the type of each component and the unique value of the component. The value is calculated, and the value representing the characteristic of the connection relation of the signal line is calculated based on the calculation result of the component connected to each signal line, and the calculation is performed a plurality of times based on the connection information, and then the calculation is performed. This is achieved by calculating a signature value that represents the characteristics of the circuit based on the result, and performing the isomorphism determination of the circuit based on the signature value. Further, the device configuration is as a component of the LSI to be tested. Input means for inputting a test condition and a test peripheral circuit for realizing the function, and the test condition and the test peripheral circuit for each function input by the input means are stored as an input result. Input result storage means and the input result Based on the test system and the LSI
Means for generating a test board for interfacing with, means for generating board control data for selecting a path on the test board necessary for each test, the test condition input result and the board control data At least a means for generating a control code for the test device based on the test peripheral circuit and dividing each of the test peripheral circuits into partial circuits.
When a test board is generated by the isomorphism determination means by circuit merging for all the pins of I, the isomorphism determination means is a means for analyzing circuit connection information and a component and the component are connected based on the analysis result. Means for storing in association with the signal line, first computing means for calculating a value representing the characteristic of each component based on the type of each component and the unique value of the component,
Second calculation means for calculating a value representing the characteristic of the connection relation of the signal line based on the calculation result of the parts connected to each signal line, and the first and second calculation means based on the connection information. Achieved by comprising processing means for performing a plurality of operations, means for calculating a signature value representing the characteristics of the circuit based on the operation processing result, and means for determining the isomorphism of the circuit based on the signature value. To be done.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The outline of the present invention will be described below before the detailed description of the present invention. That is, by providing a test peripheral circuit and means for inputting test conditions for each function of the LSI as the test target,
The test designer only has to decide the test conditions considering part of the operation of the product, and it is not necessary to set the test conditions considering the test system. At that time, by providing a means for synthesizing a test peripheral circuit required for each function by focusing on the pins of the LSI, one test board in which all the tests for the LSI are taken into consideration can be easily generated. is there. A means for generating test board control data for selecting a necessary peripheral circuit for each test from this test board is provided, and the test board control data, the test conditions input from the means, and the hardware data of the test system are provided. When a test program for controlling a test system is generated based on, the test design man-hour can be easily reduced.

Now, one embodiment of the present invention will be described with reference to FIGS. 1 to 27.
This will be described more specifically. First, an example of the configuration of the test design apparatus according to the present invention will be described with reference to FIG. As shown, the device 214 comprises a central processing unit 200,
A keyboard 201 and a pointing device 202 are used as input devices, and a display 20 is used as an output device.
3, a main storage device 204 for storing application programs and the like, an auxiliary storage device 212 for storing various data, and a memory 217 for work. Here, as the input / output device, in addition to the above, devices such as a floppy disk device and a printer can be added / replaced. Besides the memory 217, the storage device is divided into the main storage device 204 and the auxiliary storage device 212.
This is because, for convenience of description, the storage location of the application program that realizes the function of the present apparatus and the storage location of the data are distinguished. A test program generation unit 205, a test board diagram generation unit 206 as four processing units,
The test specification generation unit 207 and the test method registration processing unit 208 are both stored as application programs in the main storage device 204, and are called from the central processing unit 200 as necessary to perform processing. The processing contents of these processing units and the operation contents of the entire apparatus will be described later.

Next, the operation of the tester connected to this apparatus through the network will be described with reference to FIG.
The device 214 uses the tester 213 via the network 216.
The data is exchanged with each other while being connected to. However, the data may be exchanged not by the network 216 but manually or by exchanging data with a floppy disk. By the way, the tester 213 is roughly classified into a tester control device 225 that performs work such as compiling a test program and exchanging data with another computer connected via a network or the like, and a tester control device 225 according to the test program. Tester body 2 for performing processing such as application of a test signal to a test IC and evaluation of an output response signal from the IC under test
It is composed of 15 and. Normally, the tester 213 is composed of two modules as described above, but this increases the operating rate of the tester main body 215, and therefore the processing that does not directly require the function of the tester main body 215 is performed by the tester control device. This is because offline processing can be performed on the 225 side. The tester control device 225 for off-line processing is not a special one, and often uses a commercially available workstation. In this example, the tester 213 connected to the device 214 is the tester main body 2
15 and the tester control device 225, the present device 21 even if they both share the central processing unit.
The processing contents in 4 are the same.

First, the tester control device 225 will be described. The tester control device 225 connected to the device 214 includes the central processing unit 220, the keyboard 221 and the pointing device 222 as input devices, and the tester control device 225. , A display 223 as an output device
And a storage device 224. This configuration is basically the same as the configuration of the present device 214, and regarding the capacity of the storage device 224, etc., if the tester control device 225 is not restricted in any way, the main storage device 20
The application programs realizing the functions equivalent to those of the processing units 205 to 208 on 4 and the data stored in the auxiliary storage device 212 may be stored directly in the storage device 224.

Next, a tester 213 in a normal test
To describe the flow of the above process, first, the user inputs a test program to the tester 213 via an input device such as the keyboard 201 or the pointing device 202, or a storage medium such as a floppy disk. As a result, the tester control device 22
5 is stored in the storage device 224. After that, when the user gives an instruction to start compiling the test program to the central processing unit 220, the central processing unit 220 translates the test program into a machine language and stores it again in the storage device 224 as a machine language program. There is something. The processing up to this point is the processing on the tester control device 225 side. Thereafter, if the user gives an instruction to execute the test to the central processing unit 220, the central processing unit 220 that has received the instruction.
Through networks and other data transmission means,
The machine language program is expanded on the tester main body 215, and thereafter, under the control of the central processing unit 226 in the tester main body 215, a test signal is generated by the tester hardware according to the machine language instruction, and the tester channel is also generated. While the test signal is applied to the test head 227, the test head, and the test board 229, the IC under test 2
Processing such as evaluation of the output response signal from 30 is performed, and the quality of the IC under test 230 is determined. Finally, in the central processing unit 220, a series of processing is completed by displaying the pass / fail judgment result of the IC under test 230 on the display 223. The above is the flow of processing on the tester in the test.

Incidentally, an LSI test is generally carried out on a test system (hereinafter referred to as an LSI tester) on the LSI under test.
(Hereinafter referred to as DUT) is operated, the output response signal from the output pin is measured, and then the pass / fail judgment is performed. Specifically, the test is performed between the DUT and the LSI tester. It is performed under the control of a test program with the board interposed. The test board mentioned here is a board on which peripheral circuits required for actually operating the DUT are mounted.
It is required to establish an electrical interface with the LSI tester. A test program is an LSI for testing the DUT according to the test conditions.
It is defined as a tester control procedure. The test specifications described below describe the test contents of the DUT and the test program procedure.

The test program, which is the input data to the tester 213, will now be described. The test program is composed of one or more test items. Each test item is composed of an instruction for setting a test condition and an instruction for instructing execution of a test under the test condition. At the time of the test, as shown in FIG. 2, the test items are sequentially executed in a predetermined order. Each time the test item is executed, it is determined whether the DUT has passed or failed the test item. It is what If the DUT passes all the test items, it is judged as a non-defective product for the first time, and if it fails on the way, the execution of the subsequent test items is stopped. In addition, the DUT has been determined as a defective product. FIG. 2 shows an example of the test process. As shown in the figure, after the test is started, the tester first executes the first test item Test # 1 (231) and then determines whether or not the DUT has passed the test item Test # 1 (231). However, if the test fails, execution of all the subsequent test items is stopped and the DUT is determined as a defective product.
Also, if the test item Test # 1 (231)
If the test passes, the next test item Test # 2 for the first time
(232) is executed, and the DUT sets the test item T
A similar process is repeatedly performed thereafter, for example, it is determined whether or not est # 2 (232) is passed, and when all the test items are passed, it is first determined as a non-defective product.

FIG. 3 shows a general flow in designing an LSI. As shown in the figure, when there is a customer's required specifications (41), the LSI is based on the required specifications.
After the target specification of (4) is determined (41), the system design and circuit design are advanced (43, 44). When the circuit design is completed, the flow is the actual device creation (45-4
9) and test design. Of these, in test design, first, a test signal can be applied to the DUT and the output response signal from the DUT can be measured while considering the hardware constraints of the LSI tester. A test board is designed (50). After that, the test conditions are summarized as a specification for creating a test program (51), and then a test program is created based on this specification (52), and the test conditions, test board, and test program are debugged. (53). Each of the LSIs obtained by the device creation (45 to 49) is a DUT, and these DUTs are tested for various test items by a test program as described in FIG. 2 above. Is.

Here, the test design process (5
0 to 53), a DUT 61 including functional blocks such as an A / D conversion function, a DSP (digital signal processor) function, and a D / A conversion function is shown in FIG. 4 as an example. It shows in (A). The test design is to determine the test contents for guaranteeing the operation of each of these functional blocks, and usually D
It is based on the internal function of UT. At that time, in order to operate each of the functional blocks to be tested, the DUT
The peripheral circuit is designed around the outer circumference, and the application condition and the measurement condition are determined in consideration of the peripheral circuit. As shown in FIG. 4B, in order to test the A / D conversion function block 63, a peripheral circuit 64 for operating this block 63 is designed, and the block added to Pin-n is a test block. -1 (62). The test block mentioned here includes a test peripheral circuit and a test condition in consideration of circuit characteristics up to the DUT pin. Similarly, the peripheral circuit 67 tests the DSP function block 66, and the peripheral circuit 70 tests the D / A conversion function block 69.
What is added to in-n is the test block-2 (6
5) Design as test block-3 (68). In this way, the peripheral circuits are designed according to the circuit part to be tested, the test conditions, and the tester's ability. Finally, as shown in FIG. 5, the peripheral circuits of the respective test blocks are superposed for each pin. , The redundant circuits are combined into one,
If the circuits are different, the peripheral circuits may be selected as desired for each test block by inserting relay contacts. Peripheral circuits 64 and 6 shown in FIG.
From the examples of 7, 70, these peripheral circuits 64, 67,
Reference numeral 70 denotes a peripheral circuit 74 including relay contacts, that is, a test board, and a peripheral circuit required for each test is implemented by a desired combination of the relay contacts. After that, the test conditions considered in the above test board design are summarized as a test specification. Next, a test program is created in consideration of this test specification and the hardware resources of the test board and tester. In consideration of hardware resources, as shown in FIG. 6, when the application / measurement device of the LSI tester is connected to the tester channel 82 connecting the test board 81 to the tester, the D
It is to consider which device is connected to which channel according to the test condition of the UT pin. As described in FIG. 1, the test board is attached to the test head of the LSI tester, the test program is loaded into the LSI tester with the DUT mounted on the test head, and the tester body is controlled. A test is conducted to determine whether the DUT is good or bad.

The relationship between the test block and the test board described with reference to FIG. 5 will now be described with reference to a concrete example.
Each of FIG. 13 shows a test peripheral circuit of each test block. Among them, FIG. 7 shows an essential circuit for operating the DUT. As shown in FIG. 7, the internal function of the DUT is made up of nine functional blocks, and the inside is divided into nine rectangular shapes (internal function division image). The remaining FIG. 8 to FIG. 13 respectively show the peripheral circuits required in each test block, and the rectangular portion related to the internal shaded display shows which functional block is to be tested. Has become. As described above, it is a very natural way for a test designer to design a test peripheral circuit for testing all internal functions for each test block, and it is now a general design method. Also, even in the test conditions,
It is designed for each test block and is summarized as a final test specification. Also in FIG.
The test peripheral circuit shown in each of FIGS.
Finally, the circuit diagram of the case where it is put together as one test board is shown, but as can be seen from this, for each of the pins 9, 10, 13, 14, 39 in the DUT, a switching relay is provided. Peripheral circuits required for each test block are added via contacts.

Now, FIG. 15 shows the overall system configuration of an example of the test design apparatus according to the present invention. As shown,
Test board input processing for the purpose of reducing the test design man-hours including the test board design (50), test specification creation (51), test program creation (52) and debug (53) shown in FIG. Unit 1, test board diagram generation unit 2, test program generation unit 3, test specification generation unit 4, test content template storage unit 5, test condition data storage unit 6, tester hardware model data storage unit 7, test method storage unit 8 , Grammar model storage unit 9, actual machine adjustment data extraction unit 10, actual machine adjustment data registration processing unit 11
And so on. From the input processing unit 1, the operating conditions of the DUT and the test specifications indicating the expected operation contents when operating under this condition are input, but at the same time, the DUT operates under the operating conditions created by the input processing unit 1. It has a means for inputting and editing the peripheral circuit required for each test type. The test type referred to here is, in order to verify the function of the DUT, when the operating condition for operating the function is applied to the DUT, the expected response output is measured for each function and then the quality is judged. Represent
Further, in the test board diagram generation unit 2, the connection information of the peripheral circuits, which is stored in the test condition data storage unit 6 and is created by the input processing unit 1 for each test type, is integrated over all the tests. , A test board is supposed to be generated. Further, the test program generation unit 3 generates a control program for operating the LSI tester according to the test specifications stored in the test condition data storage unit 6, and further, the test specification generation unit 4
In, the sheet is output as a state in which the test specifications are compiled. The actual machine adjustment data extraction unit 10 also inputs a test program changed to adjust the test conditions on the LSI tester,
Processing for extracting expected operation content and test order is performed, and the test conditions extracted by the actual machine adjustment data extraction unit 10 are fed back to the test condition data storage unit 6 via the actual machine adjustment data registration processing unit 11. It has become a thing. Incidentally, the test content template storage unit 5 stores the test specifications based on the basic test contents of the LSI product, and the tester hardware data model storage unit 7 stores the setting / measurement range of the LSI tester. Stores data that models the hardware of the LSI tester, such as range, range, and limit. This allows the LSI
By defining the ability of the tester to generate the test conditions, the tester hardware constraint data at the time of test board generation and test program generation can be generated. The test method storage unit 8 stores test methods such as voltage, current measurement, and frequency measurement as a setting-measurement sequence, and the grammar model storage unit 9 stores the control language specification data of the LSI tester. It has been stored.

Next, each of the above processing units will be described. First, an example of the screen of the test board input processing unit 1 is shown in FIG. Since the unit of test is the test block unit,
The input processing unit 1 uses a functional block diagram / measurement peripheral circuit diagram input screen 91 and a test condition group input screen 97 for the functional block as basic input screens. The functional block diagram and the test condition are related by the pin 96 on the measurement peripheral circuit diagram and the pin name of the test condition data. By providing this input means, peripheral circuits and test conditions are defined for each functional block, and this becomes a test block.
Test designers can perform test design with natural thinking and input operations. Therefore, by providing such a user interface, the work efficiency of test design data input work is also improved.

In the test program generator (3) 114, as shown in FIG. 17, the test condition data 111 input from the test condition group input screen 97 shown in FIG.
From the tester hardware model data storage unit (7) 112, such as the number and type of voltage sources of the LSI tester actually usable in the test, the precision and the number of signal generation sources, and the type of measurement unit. The test program 115 is generated based on the wear resources and constraints and the grammar rule 113 of the test program from the grammar model storage unit (9) 113.

Now, regarding the test board diagram generator 2,
First, the flow of processing in the main generation unit 2 is shown in FIG. As shown in the figure, first, the connection data (including a netlist or schematic) of the measurement peripheral circuit input in FIG.
Is input for all test blocks (141),
If the connection data includes the netlist inside the DUT, the connection data inside the DUT is not necessary for the test board, so only the connection data of the peripheral circuit for measurement is extracted (142). Next, the measurement peripheral circuits of all the test blocks are integrated (merged) (143), and the LSI
A tester connector for connection with the tester is determined (145). In the actual test board, it is necessary to mount the interface with the tester according to the model of the tester. Therefore, by providing a means for automatically determining the tester connector, which is an interface with the tester based on the test condition and the measurement peripheral circuit, the tester independence of the input processing unit (user interface) is realized. Also,
On one test board, control data (test board control data) 148 of a component that changes the state of a relay or the like is generated in order to electrically select a peripheral circuit used for each test block. The integrated result is output as one test board netlist (which may include a schematic) (146, 14).
7).

FIG. 19 shows the procedure of the circuit merging process (143) in the process flow shown in FIG. First, in merging, the peripheral circuit parts that can be commonly used by the test blocks are integrated into one on the test board, and the commonality is eliminated. The mounting area above is saved. In order to realize this, for all pins and all test blocks of the DUT, isomorphism determination is performed in a state where the measurement peripheral circuit is divided into partial circuits, and a relay is added (151). . When the partial circuits are commonly used, parts such as relays for switching the electrical connection state are mounted so that the partial circuits on the test board are selectively used for each test block. A partial circuit is made available on all test blocks on one test board. Next, the number of mounted components on the test board is limited by the test head of the tester, and the area allowed there is small. Therefore, the number of relays for circuit switching, including component sharing and LSI tester hardware resource allocation, is minimized. (152). Furthermore, in order to optimize the number of relays, the relays of the circuit blocks that electrically do not require relays are deleted due to the characteristics of the internal circuit of the DUT (153).

As described above, with respect to all pins and all test blocks, the isomorphism determination process is performed in a state where the measurement peripheral circuit is divided into partial circuits. A method for performing this isomorphism determination process at high speed. Is shown in FIGS. 20 (A) and 20 (B). As an example, the circuit 155 shown in FIG.
According to the procedure flow shown in 0 (B), first, a unique value is determined for each component type. FIG.
In the circuit 155 shown in (A), the resistance is "1", the capacitor is "0.1", the transistor collector is "100", the base is "0.01", and so on. Each has a unique value. Next, the value of each component is passed to the node to which each component is connected (156), and the node fetches and calculates (or processes) all the values of the components having an adjacency relationship (157). , The calculation result here is passed to all the parts in the adjacent relationship (158). The result calculated by the nodes having the adjacency relationship is further calculated (or processed) to obtain a new component value (159). This process is repeated 160 times as many times as the number of parts or the number of nodes (or both). As a result, the calculated (or processed) component value and node value are used as the signature of the target circuit (161). By comparing the signatures, the circuit isomorphism determination is performed (162).

Conventionally, in order to recognize a circuit, it was general to recognize the connection relationship while sequentially tracing each node, but in this method, all the nodes are sequentially traced, and when performing isomorphism determination. Because backtrack occurs
The circuit scale that can obtain a solution in a realistic processing time becomes very small. FIG. 21 shows a memory map of the isomorphic determination method. It is assumed that the netlist data indicating the circuit connection relation is stored in the area 171 after the address A of the memory (storage unit). In this example, the name of each component and the node (signal line) from the component are stored in the order of "component name node 1 node 2 ..." From address A. FIG.
The initial value and the calculation result of each component indicated by 0 are stored in the component calculation result area 172 after the address B. Further, the calculated value of the node is stored in the node calculation result area 174 after the address C. In the netlist stored from address A,
An area for storing the address of the area for storing the calculation result starting from the addresses B and C is provided. As the data flow, the value of the component is passed to the arithmetic unit 173 to be calculated by the previously defined function formula (fv). Next, the computing unit 17
In No. 3, the node calculation result is read from the node calculation result area 174, is calculated by the previously defined function formula (fn), and is overwritten in the component calculation result area 172. This process is repeated, and finally the signature is calculated by the function expression (fs). By comparing these signatures, the circuit isomorphism is determined. The method is an event that can be represented by an undirected or directed graph and can be used for all events that require isomorphism determination. In addition, it is fast and requires less storage area during processing.

22 to 25 show the processing flow and processing relations of the entire system. First, FIGS. 22 and 23 show the processing flow of the input processing unit and the tester hard matching. In the tester hard matching process, based on the tester hardware model data in FIG. 1, the hardware constraints of the LSI tester and the test conditions, and the interface matching with the test board netlist generated under the test conditions are performed. After inputting the test specifications, the input processing unit calls the tester hard matching / check processing,
Check the tester's hardware constraints to determine if the input data is testable. Further, as shown in FIG. 24, in the test program generation, the test order is first determined (sequence generate). afterwards,
The tester hardware matching process of the LSI tester to be tested is performed, and a test program according to the grammar of the target LSI tester is generated based on the result. Furthermore, FIG.
As shown in (1), in the test board diagram generation, after reading the netlist for each test block and analyzing the connection relation, the peripheral circuit netlists of all the test blocks are merged. Next, the relationship between the generated test board and the connection portion between the application / measurement device of the LSI tester is assigned based on the tester hard matching process. As a result, a test board netlist is generated. In addition, a relay is automatically inserted in a portion where the circuit needs to be branched in the process of merging, and the corresponding data of the inserted relay and the test block is passed to the test program generation unit.

Finally, FIG. 26 shows the entire system configuration of another example of the test design apparatus according to the present invention. As illustrated, the substantial difference from that shown in FIG. 15 is that a circuit division processing unit 181 for dividing a test block from the internal circuit data 180 of the DUT is newly provided for the test board input processing unit 182. It is a point. In addition to the circuit connection information, the DUT circuit data from the circuit design CAD is provided with hierarchical information of functional blocks. A circuit division processing unit 181 that automatically divides into test blocks by using this hierarchical data is provided. Test board input processor 1
At 82, the circuit data divided by the circuit division processing unit 181 is displayed, and the test condition and peripheral circuit input means are provided. In addition, in FIG.
The system configuration provided with means for reading the UT circuit data 191 is shown. As a result, the test block input man-hours can be reduced.

[0028]

As described above, according to the first to eighth aspects, the test designer only has to decide the test condition in consideration of the operation of a part of the product, and the test condition considering the LSI tester. Not only does this eliminate the need for setting, but a test program, test board, and test specifications can also be automatically generated, reducing the number of test design steps. Further, according to claims 9 and 10, the LS as the test target is in a state where the test design man-hours can be reduced.
I can be tested for each function.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an example of a test design apparatus according to the present invention together with a tester.

FIG. 2 is a diagram showing a flow of an example of test processing by a test program.

FIG. 3 is a diagram showing a general flow in LSI design.

FIG. 4A and FIG. 4B are views for explaining the flow of a general test board design.

FIG. 5 is a diagram for explaining an outline of test board generation processing.

FIG. 6 is a diagram showing a relationship between a test condition and an LSI tester.

FIG. 7 is a diagram showing a relationship between a DUT functional block and a measurement peripheral circuit (No. 1).

FIG. 8 is a diagram showing the relationship between the functional blocks of the DUT and the measurement peripheral circuit (No. 2).

FIG. 9 is a diagram showing a relationship between a DUT functional block and a measurement peripheral circuit (No. 3).

FIG. 10 is a diagram showing the relationship between the functional blocks of the DUT and the measurement peripheral circuit (No. 4).

FIG. 11 is a diagram showing the relationship between the functional blocks of the DUT and the measurement peripheral circuit (No. 5).

FIG. 12 is a diagram showing the relationship between the functional blocks of the DUT and the measurement peripheral circuit (No. 6).

FIG. 13 is a diagram showing the relationship between the functional blocks of the DUT and the measurement peripheral circuit (No. 7).

FIG. 14 is a diagram showing a circuit diagram when the test peripheral circuits shown in FIGS. 7 to 13 are finally put together as one test board.

FIG. 15 is a diagram showing the overall system configuration of an example of a test design apparatus according to the present invention.

FIG. 16 is a diagram showing an example of a screen of a test board input processing unit according to the present invention.

FIG. 17 is a diagram for explaining processing in the test program generation unit.

FIG. 18 is a diagram showing a flow of processing in a test board diagram generation unit according to the present invention.

FIG. 19 is a diagram showing an example of a circuit merge processing procedure in the test board generation processing.

20A and 20B are diagrams for explaining a method for performing isomorphism determination processing according to the present invention at high speed.

FIG. 21 is a diagram showing a memory map in an example of a high-speed isomorphic determination method.

FIG. 22 is a diagram showing a processing flow of the entire system and processing relations (No. 1).

FIG. 23 is a diagram showing a processing flow and processing relations of the entire system (No. 2).

FIG. 24 is a diagram (No. 3) showing the processing flow and processing relation of the entire system.

FIG. 25 is a diagram showing a processing flow of the entire system and processing relations (Part 4).

FIG. 26 is a diagram showing the overall system configuration of another example of the test design apparatus according to the present invention.

FIG. 27 is a diagram showing an overall system configuration of still another example of the test design apparatus according to the present invention.

[Explanation of symbols]

1 ... Input processing unit, 2 ... Test board diagram generation unit, 3 ... Test program generation unit, 4 ... Test specification generation unit, 5 ... Test content template storage unit, 6 ... Test condition data storage unit, 7 ... Tester hardware Wear model data storage unit,
8 ... Test method storage unit, 9 ... Grammar rule storage unit, 10 ...
Actual machine adjustment data extraction unit, 11 ... Actual machine adjustment data registration processing unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaki Miyazumi 5-20-1 Josuihoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. 5-20-1 Hitachi Ltd. Semiconductor Division

Claims (10)

[Claims] 1. A test design method for inspecting whether a manufactured LSI operates reliably or not, which comprises a test condition for each function of an LSI as a test target and a test for realizing the function. Peripheral circuits for use as input results, hardware specification data of a test system for inspecting the LSI, and grammar rules of a program for controlling the test system are stored, and the input results and the hardware are stored. A test program based on the specification data and the grammar rules, a test board that interfaces the test system with the LSI based on the input results input for each function, test conditions based on the input results, and test While generating the design specifications for the peripheral circuit and test system control program respectively, adjust them by the test system. A test design method in which adjusted test conditions are reflected in previously stored test conditions. 2. A test design apparatus for inspecting whether a manufactured LSI operates reliably or not, wherein a test condition for each function of an LSI as a test target and a test for realizing the function. Means for inputting a peripheral circuit for test, an input result storing means for storing the test condition for each function and the peripheral circuit for testing input by the input means as an input result, and a hardware of a test system for inspecting the LSI. Specification data storage means for storing hardware specification data, grammar rule storage means for storing grammar rules of a program for controlling the test system, and a test program based on the input result, the hardware specification data and the grammar rule. Test program generating means for generating the test system and the LSI based on the input result input for each function. It is adjusted by the test system, the means for generating the test board that interfaces with the, the specification generation means for generating the design specifications of the test condition, the test peripheral circuit, and the test system control program based on the above input results. A test design apparatus having a configuration including means for reflecting a test condition on a test condition stored in advance. 3. A test design method for inspecting whether or not a manufactured LSI operates reliably.
Is divided based on the circuit block at the time of circuit design, and the test condition and the test peripheral circuit for realizing the function are stored as an input result for each divided circuit block, and the LSI The hardware specification data of the test system for inspecting and the grammar rules of the program for controlling the test system are stored, and the test program is prepared for each function based on the input result, the hardware specification data and the grammar rule. A test board that interfaces the test system with the LSI based on the input results input to the test system, and generates test conditions, test peripheral circuits, and design specifications of the test system control program based on the input results. On the other hand, the test conditions adjusted by the test system are stored in the Test design method to be reflected in the matter. 4. A test design apparatus for inspecting whether or not a manufactured LSI operates reliably.
Circuit dividing means for dividing the entire circuit of the circuit into circuit blocks based on circuit blocks at the time of circuit design, input means for inputting a test condition and a test peripheral circuit for realizing the function for each divided circuit block, and An input result storage means for storing, as an input result, a test condition for each function and a test peripheral circuit input by the input means, a specification data storage means for storing hardware specification data of a test system for inspecting the LSI, Grammar rule storage means for storing grammar rules of a program for controlling the test system,
A test program generating means for generating a test program based on the input result, the hardware specification data and the grammar rule, and a test for interfacing the test system with the LSI based on the input result input for each function. Means for generating a board, means for generating test conditions, test peripheral circuits, design specifications for a test system control program based on the above input results, and test conditions adjusted by the test system are stored in advance. And a test design device having a configuration including means for reflecting the test conditions. 5. A test design method for inspecting whether or not a manufactured LSI operates reliably.
After editing the whole circuit diagram of, the necessary circuit diagram extracted based on the function of the product from the edited whole circuit diagram, or the test peripheral circuit for operating the circuit block diagram and the test conditions are input. In addition to being stored as a result, the hardware specification data of the test system for inspecting the LSI and the grammar rule of the program for controlling the test system are stored, and the input result, the hardware specification data and the grammar rule are also stored. A test board based on the above, a test board that interfaces the above test system and the above LSI based on the input result input for each function, and based on the above input test conditions, test peripheral circuits, test system control Test conditions adjusted by the test system while generating each design specification of the program , Test design method to be reflected to the test conditions stored in advance. 6. A test design apparatus for inspecting whether a manufactured LSI operates reliably or not.
Editing means for editing the whole circuit diagram of, and circuit diagram extracting means for extracting a circuit diagram or a circuit block diagram necessary for the function of the product from the edited whole circuit diagram, and the extracted circuit diagram, or Peripheral circuit input means for inputting test peripheral circuits for operating the circuit block diagram, test condition input means for inputting test conditions, and input results for storing the input test conditions and test peripheral circuits as input results Storage means, specification data storage means for storing hardware specification data of a test system for inspecting the LSI, grammar rule storage means for storing grammar rules of a program for controlling the test system, the input result, the hardware Test program generation means for generating a test program based on the wear specification data and the grammatical rules, and for each function A means for generating a test board that interfaces the test system with the LSI based on the input result input, and a test condition, a test peripheral circuit, and a design specification of a test system control program based on the input result. A test design apparatus having a configuration including a specification generation unit that generates a test condition and a unit that reflects a test condition adjusted by a test system on a test condition stored in advance. 7. A test design method for inspecting whether a manufactured LSI operates reliably or not, and a test condition for each function of the LSI as a test target and a test for realizing the function. The peripheral circuit and the hardware specification data of the test system for inspecting the LSI and the grammar rules of the program for controlling the test system are stored, and the input result and the hardware specification are stored. A test program based on the data and the grammar rules, a test board that interfaces the test system with the LSI based on the input results input for each function, test conditions and test peripherals based on the input results. Generates design specifications for circuits and test system control programs, and adjusts by the test system A test design method in which the generated test conditions are reflected in pre-stored test conditions. Each test peripheral circuit is divided into partial circuits, and isomorphism determination is performed by circuit merging for all pins of the LSI. When a test board is generated by using, the circuit connection information is analyzed, and based on the analysis result, it is stored in association with the component and the signal line to which the component is connected. The type of each component and the unique value of the component are stored. A value representing the characteristic of each component is calculated based on the above, and a value representing the characteristic of the connection relation of the signal line is calculated based on the calculation result of the component connected to each signal line, and the connection information is calculated based on the connection information. A test design method in which after performing a plurality of calculations, a signature value representing the characteristics of the circuit is calculated based on the calculation result, and the isomorphism determination of the circuit is performed based on the signature value. 8. A test design apparatus for inspecting whether a manufactured LSI operates reliably or not, and a test condition for each function of an LSI to be tested and a test for realizing the function. Means for inputting a peripheral circuit for test, an input result storing means for storing the test condition for each function and the peripheral circuit for testing input by the input means as an input result, and a hardware of a test system for inspecting the LSI. Specification data storage means for storing hardware specification data, grammar rule storage means for storing grammar rules of a program for controlling the test system, and a test program based on the input result, the hardware specification data and the grammar rule. Test program generating means for generating the test system and the LSI based on the input result input for each function. It is adjusted by the test system, the means for generating the test board that interfaces with the, the specification generation means for generating the design specifications of the test condition, the test peripheral circuit, and the test system control program based on the above input results. A test designing device having a structure for reflecting test conditions to pre-stored test conditions, wherein each test peripheral circuit is divided into partial circuits, and the same shape is obtained by merging circuits for all pins of an LSI. When generating the test board by the determination means, the isomorphic determination means, means for analyzing the connection information of the circuit, and means for storing based on the analysis result in association with the component and the signal line to which the component is connected, First computing means for calculating a value representing the characteristic of each component based on the type of each component and the unique value of the component, and a unit connected to each signal line Second calculation means for calculating a value representing the characteristic of the connection relation of the signal line based on the above calculation result, and processing means for calculating the first and second calculation means a plurality of times based on the connection information. A test design apparatus comprising: a means for calculating a signature value representing the characteristics of a circuit based on the result of the arithmetic processing; and a means for determining the isomorphism of the circuit based on the signature value. 9. A test method for inspecting whether a manufactured LSI operates reliably or not, wherein a test condition for each function of the LSI to be tested and a test peripheral for realizing the function. The circuit and the LS are stored as input results, and the test system and the LS are stored based on the input results.
A test board that interfaces with I is generated, and board control data for selecting a path on the test board necessary for each test is generated. Based on the test condition input result and the board control data, This is a test method in which the LSI is tested for each function based on the generated control code of the test device. Each test peripheral circuit is divided into partial circuits, and circuit merge is performed for all pins of the LSI. When a test board is generated by the homomorphic determination, the wiring information of the circuit is analyzed, and the component and the signal line to which the component is connected are stored based on the analysis result, and the type of each component and the component A value expressing the characteristic of each component is calculated based on the unique value, and the characteristic of the connection relation of the signal line is expressed based on the calculation result of the component connected to each signal line. A value is calculated, and a plurality of times is calculated based on the above-mentioned connection information. Then, a signature value that represents the characteristics of the circuit is calculated based on the calculation result, and the isomorphism determination of the circuit is performed based on the signature value. Test method. 10. A test apparatus for inspecting whether a manufactured LSI operates reliably or not, wherein a test condition for each function of the LSI to be tested and a test peripheral for realizing the function. Input means for inputting a circuit, input result storage means for storing test conditions and test peripheral circuits for each function input by the input means as input results, a test system based on the input results, and the above L
Means for generating a test board that interfaces with the SI, and means for generating board control data for selecting a path on the test board necessary for each test,
A test device having at least a means for generating a control code of a test device based on the test condition input result and the board control data, wherein each of the test peripheral circuits is divided into partial circuits, and the entire LSI is When a test board is generated by the isomorphism determination means by circuit merging of pins, the isomorphism determination means includes means for analyzing circuit connection information, and a component and a signal line to which the component is connected based on the analysis result. Means for storing in association with each other, first computing means for computing a value representing the characteristic of each component based on the type of each component and the unique value of the component, and the above-mentioned computation result of the component connected to each signal line. Second calculation means for calculating a value representing the characteristic of the connection relation of the signal line, processing means for calculating the first and second calculation means a plurality of times based on the connection information, and the calculation processing result. Based on Means for calculating a signature value that represents the characteristics of the road, the test device is composed of a means for performing the same shape determination circuit based on signing value.