JPH09259170A - Waveform information library preparing device for integrated circuit cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically prepare a waveform information library for an integrated circuit cell. SOLUTION: Layout data (a) with respect to the new cell are prepared and a net list (c) is extracted. Based on an existent cell library (b) with respected to an equivalent cell having the logic function equal with this cell, a waveform file (d) for analysis showing an expected value waveform corresponding to a prescribed input waveform is prepared. A characteristic analyzing means 3 simulates the circuit operation at the time of applying the input waveform in the waveform file (d) for analysis to a circuit specified by the net list (c) based on the conditions in an analytic condition file (e) and generates a measured value waveform and a delay information file (f). The provided measured value waveform is compared with the expected value waveform and when both the waveforms are coincident, a library preparing means 5 prepares a waveform information library (g) by synthesizing the waveform file (d) for analysis and the delay information file (f).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit cell waveform information library creating apparatus, and more particularly, to an apparatus for creating a waveform information library containing delay information under various conditions.

[0002]

2. Description of the Related Art When designing a large scale integrated circuit,
A method is available in which various kinds of cells are prepared and a desired integrated circuit is realized by combining these cells. In this way, when the design of the large-scale integrated circuit is completed by the combination of the cells, the circuit operation is verified, and if there is a problem, the design is changed. Generally, a dynamic analysis method and a static analysis method are known as methods for verifying the circuit operation of a large-scale integrated circuit. The dynamic analysis method is a method of simulating the actual signal propagation process in real time based on the physical properties of the designed circuit (width, thickness, impurity concentration, etc. of each layer), and is performed using a logic simulator such as SPICE. Be seen. On the other hand, the static analysis method prepares information for specifying the logical operation and delay time of each cell in the form of a waveform information library, and verifies the circuit operation of the entire integrated circuit based on the data of the waveform information library. Is. The verification accuracy of the static analysis method is slightly lower than that of the dynamic analysis method, but the computational load on the computer is significantly reduced.

[0003]

When performing the above-mentioned static analysis method, it is necessary to prepare a waveform information library for each cell. This waveform information library shows information indicating the relationship between input and output waveforms, such as what kind of output waveform is obtained when a given input waveform is given to the cell, and the delay time of the output waveform with respect to the input waveform. It is composed of information and. Conventionally, such a waveform information library has been manually created. The work of creating the waveform information library is very complicated work, and there is a problem in that the work efficiency becomes poor and it becomes inaccurate if it is manually performed.

Therefore, an object of the present invention is to provide an apparatus capable of automatically creating a waveform information library of integrated circuit cells.

[0005]

SUMMARY OF THE INVENTION According to the present invention, based on layout data including information on individual figures forming an integrated circuit cell, a waveform showing input / output waveform information and delay time information on this cell. In an apparatus for creating an information library, a netlist creating means for creating a netlist showing a connection relationship between individual circuit components based on layout data and an equivalent cell having a logical function equivalent to that of a target cell are provided. An analysis waveform creating means for creating an analysis waveform file having a predetermined input waveform and an expected value waveform expected to be output from the cell for the input waveform based on the cell library describing the logical operation, and a net. An input waveform specific to the target cell based on the list, the input waveform in the analysis waveform file, and the specified analysis conditions. A characteristic analysis means for performing a characteristic analysis simulation in the case of giving a measured value waveform output from a cell and delay information of the measured value waveform with respect to a given input waveform, and a logic of the measured value waveform and the expected value waveform A library creating means for creating a waveform information library for a cell by adding delay information to the analysis waveform file when the matching result of the matching means and the matching result of the matching means indicate matching. And are provided.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on an embodiment shown in the drawings. FIG. 1 is a conceptual diagram showing a configuration of a general large scale integrated circuit 10. As shown, the large scale integrated circuit 10 is composed of a large number of cells. The individual cells are usually selected from a large number of types of cells prepared as a standard cell library, and the large-scale integrated circuit 10 as a whole can perform desired logic processing. Are wired (not shown).

For such a large scale integrated circuit 10,
When performing verification by the dynamic analysis method, a real-time simulation based on the physical properties of each cell (width of each layer, thickness, impurity concentration, etc.) will be performed. That is, a predetermined input signal is applied to the input terminal of the large-scale integrated circuit 10, and the waveform of this input signal is simulated as it propagates through each cell to simulate the final signal. Then, what kind of waveform the output signal having is obtained. On the other hand, when performing verification by the static analysis method, prepare a waveform information library for each cell and obtain the transition every time a signal passes through each cell based on the data in this library. become. In other words, what kind of input waveform is given to each cell and what kind of output waveform is obtained with what delay time, without touching each physical phenomenon occurring inside the cell? Based on the data in the waveform information library indicating that, each cell is treated as a black box, and the circuit operation of the large-scale integrated circuit 10 as a whole is analyzed.

For example, the cell 11 shown in FIG. 2 performs a logical operation of outputting one output signal D based on three input signals A, B and C. Then, the information "what kind of input waveform is given as the input signals A, B and C and what kind of expected value waveform is obtained as the output signal D" and "the input signals A and B of the output signal D are given. , C will be the delay time. ”, And a waveform information library having the information. FIG. 3 is a conceptual diagram showing the information in such a waveform information library. FIG. 3 (a) shows a waveform diagram showing the relationship between the input waveform and the expected value waveform. The waveform diagram shown in FIG. 3 (a) shows a case where the delay time of the expected value waveform D with respect to the input waveforms A, B, and C is zero.
Actually, the expected value waveform D is output with a predetermined delay time, and this delay time changes depending on various conditions. The dominant factor that determines the delay time is the load capacitance connected to the latter stage of this cell. The relationship between the load capacity and the delay time usually takes a substantially linear relationship as shown in FIG. 3 (b).

After all, in order to verify the large-scale integrated circuit 10 shown in FIG. 1 by the static analysis method, the waveform information library (input waveform and expected waveform) shown in FIG. It is necessary to prepare information indicating the relationship with the value waveform and delay information). Therefore, conventionally, every time a new cell is designed, a waveform information library for the cell is manually prepared.
As mentioned above, this work is complicated and requires a lot of labor and time. The apparatus according to the present invention has a function of automatically generating such a waveform information library.

FIG. 4 is a block diagram showing the basic configuration of the device according to the present invention. In this figure, rectangular blocks 1 to 5 indicate individual constituent elements of the apparatus, and cylindrical blocks a to g indicate data handled by each constituent element. The basic components of this apparatus are a netlist creating means 1 for creating a netlist c based on predetermined layout data a, and an existing cell library b.
Analysis waveform creating means 2 for creating an analysis waveform file d based on the above, a netlist c and an analysis waveform file d
Characteristic analysis means 3 for performing a characteristic analysis simulation based on an input waveform in the above and an analysis condition file e, an actually measured value waveform obtained as an analysis result of the characteristic analysis means 3 and an expected value waveform in an analysis waveform file d. Of the logical collating means 4 for performing the logical collation of the above, and the delay information file f obtained as the analysis result of the characteristic analyzing means 3 is added to the analyzing waveform file d when the collating results coincide with each other to create the waveform information library g. The library creating means 5.

Here, the procedure for creating a waveform information library for a newly designed integrated circuit cell with this device will be described below. First, layout data a for a newly designed cell is prepared. The layout data a is composed of graphic data showing the shapes, positions, and connection relationships of individual graphics (wiring layers, semiconductor channel layers, individual electrode layers, etc.) that make up a cell. The operator is the netlist creation means 1
Thus, a netlist c indicating the connection relationship between individual circuit components is created from this layout data a. As the netlist creating means 1, a netlist extraction tool known as a so-called LPE tool (Layout Parameter Extraction Tool) may be used.

Then, a cell library b is prepared which describes the logical operation of an equivalent cell having a logical function equivalent to that of the newly designed cell. At present, even when a new cell is designed, it is extremely rare that the cell has a completely new logic function, and normally, many equivalent cells having the same logic function have already been designed in the past. Is common. In other words, in the present situation,
The task of designing a new cell is not the task of newly developing a cell having a completely new logic function, but the task of improving an existing cell to further save space and power. Is common. When a cell with such an improvement is newly designed, a cell library b for existing equivalent cells can be prepared.
Specifically, EDA tools (Electric Design Automati
Since a large number of cell libraries for on Tool) are prepared as past design assets, this library can be used as it is.

Next, based on this cell library b,
The analysis waveform creating means 2 creates the analysis waveform file d. The analysis waveform file d is a file having information indicating a relationship between a predetermined input waveform and an expected value waveform expected to be output from the cell with respect to the input waveform. For example, FIG. It is a file showing the relationship between the input waveform and the expected value waveform as shown in. Cell library b
Contains a truth table and a logic description for the cell, and the analysis waveform creating means 2 can create the analysis waveform file d based on the truth table and the logic description.

When the netlist c and the analysis waveform file d are prepared in this way, the characteristic analysis means 3 performs characteristic analysis. The characteristic analysis means 3 is a device for performing circuit simulation based on a dynamic analysis method,
For example, it is configured by a circuit simulator such as SPICE. An analysis condition file e is prepared in order to set various conditions of this simulation (for example, load capacity and temperature conditions connected in the subsequent stage). After all,
The characteristic analysis unit 3 executes the simulation of the circuit operation when the input waveform in the analysis waveform file d is given to the circuit specified by the netlist c under the condition set in the analysis condition file e. Will be done. As a result, the measured value waveform output from this cell and the delay information regarding this measured value waveform are obtained. For example, when the simulation is performed on the cell 11 shown in FIG. 2, a measured value waveform as shown by the waveform D in FIG. 3 (a) and delay information as shown in FIG. 3 (b) are obtained. It will be.

The measured value waveform thus obtained is compared and compared with the expected value waveform in the analysis waveform file d by the logic collating means 4. If the cell represented by the netlist c (that is, the cell specified by the layout data a) performs the intended logical operation, the two waveforms should match, but it is not possible to design the cell. If so, the two waveforms may not match with each other without performing the expected logical operation. The logic collating means 4 determines if the two waveforms do not match,
The operator is notified to that effect. When the operator is notified of this inconsistency, the operator will perform the correction process for the layout data a based on the content of the inconsistency. In this case, the cell itself is incomplete in design, and naturally, it is not necessary to create the waveform information library.

As a result of the collation by the logical collating means 4, if the two waveforms match, the library creating means 5 adds the delay information file f to the analysis waveform file d,
A waveform information library g is created. For example, in the case of the cell 11 shown in FIG. 2, the information indicating the relationship between the input waveform and the expected value waveform as shown in FIG. 3A and the delay information as shown in FIG. It will be obtained as a library g.

As described above, by using the apparatus according to the present invention, a waveform information library for a newly designed cell can be automatically created, and the logical operation of the cell is incomplete. In that case, since the notification to that effect is given, it becomes possible to immediately perform the process of correcting the design. The waveform information library g created in this way can be used when performing highly accurate static analysis of the large scale integrated circuit 10 designed using this cell, and based on this waveform information library g. , It becomes possible to create a new cell library for the EDA tool, and it can be used as a future design asset.

[0018]

As described above, according to the present invention, it becomes possible to automatically create a waveform information library of integrated circuit cells.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a configuration of a general large scale integrated circuit 10.

FIG. 2 is a diagram showing an example of cells constituting the large scale integrated circuit 10 shown in FIG.

FIG. 3 is a conceptual diagram showing information in a waveform information library for the cell shown in FIG.

FIG. 4 is a block diagram showing a basic configuration of an apparatus according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Netlist creation means 2 ... Analysis waveform creation means 3 ... Characteristic analysis means 4 ... Logical matching means 5 ... Library creation means 10 ... Large scale integrated circuit 11 ... Cell a ... Layout data b ... Cell library c ... Netlist d Waveform file for analysis e ... Analysis condition file f ... Delay information file g ... Waveform information library A to C ... Input signal D ... Output signal

Claims (1)

[Claims] 1. An apparatus for creating a waveform information library showing input / output waveform information and delay time information on a cell based on layout data including information on individual figures constituting an integrated circuit cell. And a netlist creating means for creating a netlist showing the connection relationship of individual circuit components based on the layout data, and a cell library describing the logical operation of an equivalent cell having the same logical function as the cell. An analysis waveform creating means for creating an analysis waveform file having a predetermined input waveform and an expected value waveform expected to be output from the cell for the input waveform, the netlist, and the analysis Analysis when the input waveform is given to the cell based on the input waveform in the waveform file for use and predetermined analysis conditions A simulation is performed, and characteristic analysis means for obtaining an actually measured value waveform output from the cell and delay information of the actually measured value waveform with respect to the input waveform, and a logical comparison between the actually measured value waveform and the expected value waveform are performed. When the logical collating unit and the collating result of the logical collating unit show a coincidence, the delay information is added to the analysis waveform file to create a waveform information library for the cell. An integrated circuit cell waveform information library creating apparatus comprising: