JP3144617B2 - Logic circuit verification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for verifying a logic circuit, and more particularly to a technique effective when applied to a method for verifying a logic circuit by verifying the logic circuit by logic circuit simulation and architecture simulation.

[0002]

2. Description of the Related Art The functions of a microprocessor and the like used in a conventional computer are realized by hardware comprising a logic circuit and software executed on the logic circuit.

When designing the logic circuit, CAD
(Computer Aided Design) system is used, and the logic circuit data describing the operation of the logic circuit based on the design specification of the logic circuit is converted to the CAD data.
After input to a system and verifying the logic circuit using the logic circuit data, the logic circuit is manufactured based on the logic circuit data.

In the verification of the logic circuit, a logic circuit simulation is performed on the logic circuit data.
The logic circuit simulation simulates the operation of the logic elements constituting the logic circuit data in the input CAD system, and when a digital signal of “0” or “1” is input to an input terminal of a certain logic circuit. , Calculating the signal value output to the output terminal of the logic circuit, and verifying whether the calculated output signal value satisfies the design specification.

[0005] The functions of the microprocessor are realized not only with the hardware that is the logic circuit, but also with software executed on the logic circuit. Logic circuit data corresponding to the function realized by the software includes: Since it does not exist, the function of the entire logic circuit cannot be verified only by logic circuit simulation.

Further, even when a certain function of the microprocessor is realized by hardware which is a logic circuit, if the design of the logic circuit is not completed, logic circuit data of the logic circuit is input. Therefore, a logic circuit simulation of the logic circuit cannot be performed.

Therefore, an architecture simulation is performed for the functions realized by the software and a function of a logic circuit whose design has not been completed, and a logic circuit simulation is performed for the logic circuit whose design has been completed. Has been verified.

[0008] The architecture simulation includes:
A function realized by the software or a function of a logic circuit whose design has not been completed is described in a program language such as C language, and the function is simulated by executing the program. It is executed as needed during execution of the logic circuit simulation.

A logic simulation apparatus using both the logic circuit simulation and the architecture simulation is described in Japanese Patent Application Laid-Open No. 2-268341.

The outline is that a logic circuit simulation is performed on the function of the logic circuit input to the CAD system, and at the same time, an architecture simulation in which the function realized by software is described in a program language is executed, and the function of the entire logic circuit is performed. Is performed.

For example, among certain functions including an initial setting section, a test section, and a result determining section, when the initial setting section and the result determining section are realized by software and the testing section is realized by a logic circuit, The function of the result determination unit is described in a programming language, an architecture simulation is performed in the initial setting unit, the result of the architecture simulation is performed as an input of a logic circuit simulation in the test unit, and the logic circuit simulation is performed. The entire function is verified by performing the architecture simulation as an input of the architecture simulation of the result determination unit.

In the logic simulation apparatus, a logic circuit simulation result is extracted from the logic circuit, and a verification circuit, which is a circuit to be passed to an architecture simulator as input data, is added to the logic circuit data.

The logic circuit data to which the verification circuit is added is different from the logic circuit data in which the design specification is described. Therefore, when performing the architecture simulation, the logic circuit data for the logic circuit simulation is required. Separately, logic circuit data for architecture simulation is created.

After verifying the logic circuit as described above using the logic circuit data input to the CAD system, a logic circuit is created based on the logic circuit data. It is verified whether the logic circuit satisfies the design specification.

In the verification of the created logic circuit, an electric signal of each part of the logic circuit created based on the logic circuit data is measured, and an electric signal of each part of the logic circuit determined from the design specification of the logic circuit is measured. The diagnostic data, which is the design value of the signal, is compared with the measured value of the electric signal of each part of the logic circuit to verify whether the created logic circuit satisfies the design specifications.

[0016]

SUMMARY OF THE INVENTION The present inventor has found the following problems as a result of studying the above prior art.

That is, in the conventional logic circuit verification method using both the logic circuit simulation and the architecture simulation, since the logic circuit data is created twice, the management of the design file composed of the above-mentioned double logic circuit data is performed. In addition, there is a problem that the load required for the work of correcting the above-described double logic circuit data accompanying the failure analysis and the failure countermeasure becomes large.

Further, in a complicated logic circuit, the number of combinations of logics becomes enormous, so that there is a problem that it takes much time to create diagnostic data.

An object of the present invention is to provide a technique capable of efficiently verifying a logic circuit.

It is another object of the present invention to provide a technique capable of verifying a logic circuit without duplicating logic circuit data describing the logic circuit.

Another object of the present invention is to provide a technique capable of generating diagnostic data of a logic circuit at high speed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0023]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a logic circuit simulation for simulating the operation of the logic circuit and an architecture simulation for simulating the processing of software executed on the logic circuit are performed to determine whether the logic circuit satisfies the design specifications. A method of verifying a logic circuit to be verified, wherein a control definition defining execution conditions of the architecture simulation is created, and for a certain logic circuit portion of the logic circuit, an operation of a logic element constituting the logic circuit portion is simulated. Executing the logic circuit simulation, and executing the architecture simulation when the result of the logic circuit simulation satisfies the execution condition in the control definition, and executing the logic circuit simulation and the result of the architecture simulation. The one in which by comparing the design specification of the logic circuit verifies the entire logic circuit.

Further, a logic circuit simulation for simulating the operation of the logic circuit and an architecture simulation for simulating the processing of software executed on the logic circuit are performed to determine whether the logic circuit satisfies the design specifications. A method of verifying a logic circuit to be verified, wherein a control definition defining execution conditions of the architecture simulation is created without changing a description of the logic circuit, and the logic circuit portion is included in a logic circuit portion of the logic circuit. Simulating the operation of the constituent logic elements to execute the logic circuit simulation; executing the architecture simulation when the result of the logic circuit simulation satisfies the execution condition in the control definition; The ar Compared results of Te Kucha simulation and design specifications of the logic circuit performs a validation of the entire logic circuit.

Also, in a logic circuit verification method for measuring whether or not the logic circuit satisfies the design specification by measuring an electric signal on the logic circuit, a logic circuit simulation for simulating the operation of the logic circuit is provided. Executing an architecture simulation for simulating software processing executed on the logic circuit, creating diagnostic data of the logic circuit from the result of the logic circuit simulation and the architecture simulation; To verify the logic circuit by comparing the measured values of the electric signals.

[0027]

According to the above-described means, in the logic circuit verification method of the present invention, first, a control definition defining execution conditions of the architecture simulation is created.

The control definition defines executing the architecture simulation in accordance with a signal value of the logic circuit data determined by a logic circuit simulation using logic circuit data describing the logic circuit. It is.

Next, an input signal value is set to a logic element constituting an input portion of the logic circuit data, and an output signal value of the logic circuit data is calculated by simulating the operation of the logic element. The logic circuit simulation is performed.

After performing the logic circuit simulation, referring to the control definition, when the output signal value of the logic circuit data determined by the logic circuit simulation satisfies the execution condition of the architecture simulation, the output signal The value is input as an input signal value of the architecture simulation, and the architecture simulation is executed.

The logic circuit simulation and the architecture simulation are performed on all the logic circuit data to verify whether the result satisfies the design specifications of the logic circuit.

As described above, in the logic circuit verification method of the present invention, the architecture simulation is executed during the logic circuit simulation by referring to the control definition , so that the logic circuit can be efficiently verified. Is possible.

In the method for verifying a logic circuit according to the present invention,
The control definition defining the execution condition of the architecture simulation is not created in the logic circuit data describing the logic circuit, but is created separately from the logic circuit data.

The control definition defines executing the architecture simulation in accordance with a signal value of the logic circuit data determined by a logic circuit simulation using logic circuit data describing the logic circuit. In addition, a place where a signal value of the logic circuit data necessary for determining the execution condition is stored.

Next, an input signal value is set to a logic element constituting an input portion of the logic circuit data, and an operation of the logic element is simulated to calculate an output signal value of the logic circuit. Perform a logic circuit simulation.

After performing the logic circuit simulation, the control definition is referred to, the signal value of the logic circuit data necessary for determining the execution condition is checked, and the logic circuit data determined by the logic circuit simulation is determined. When the output signal value satisfies the execution condition of the architecture simulation, the output signal value is input as an input signal value of the architecture simulation, and the architecture simulation is executed.

The logic circuit simulation and the architecture simulation are performed on all the logic circuit data to verify whether the result satisfies the design specifications of the logic circuit.

As described above, in the logic circuit verification method of the present invention, since the architecture simulation is performed without adding a verification circuit for executing the architecture simulation to the logic circuit data, the logic circuit data is duplicated. It is possible to verify the logic circuit without performing.

In the method for verifying a logic circuit according to the present invention,
Diagnostic data of a logic circuit created based on the logic circuit data is created from the signal values of each part of the logic circuit obtained as a result of the logic circuit simulation and the architecture simulation.

The results of the logic circuit simulation and the architecture simulation are physically divided into layers, and the result of the simulation of the signal line to be measured when measuring the electric signal on the created logic circuit is calculated. Extract and create diagnostic data for the measurement location.

The logic circuit created based on the logic circuit data is actually operated, an electric signal on the logic circuit is measured, and the measured value of the electric signal is compared with the diagnostic data to compare the logic data. Perform verification.

As described above, in the logic circuit verification method of the present invention, since the diagnostic data of the logic circuit is created based on the result of the logic circuit simulation and the architecture simulation, the diagnostic data of the logic circuit can be created at high speed. It is possible.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail together with an embodiment with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a logic circuit simulator and an architecture simulator for implementing the logic circuit verification method of the present invention. In FIG.
Is a logic circuit simulator, 102 is a logic circuit, 103 and 104 are signal lines, 105 and 106 are data flow arrows, 107 is a control definition, 108 is a definition unit, 109 is a trigger definition unit, and 110 is an architecture simulator call. , An arrow indicating that a signal value is passed to the architecture simulator, an arrow indicating that a signal value is returned to the architecture simulator, an arrow indicating that a signal value is returned from the architecture simulator, an architecture simulator, 1
15 is an input function for inputting a signal value, and 116 is an output function for outputting a signal value.

As shown in FIG. 1, in the method of verifying a logic circuit according to the present embodiment, the logic circuit simulator 101 activates the architecture simulator 114 based on the signal value of the logic circuit 102 and the activation condition defined in the control definition 107. I do.

For example, the logic circuit 102 has a control definition 1
07, a signal line 103 having a signal name of SIGA and a signal line 104 having a signal name of SIGB described in a declaration section 108,
By executing the logic circuit simulator 101, the signal values of the signal lines 103 and 104 change.

The change in the signal values of the signal lines 103 and 104 is immediately transmitted to the trigger definition unit 109 via the declaration unit 108 of the control definition 107 according to the data flows 105 and 106.

The trigger definition unit 109 checks the value of the variable SIG to which the value of the signal line 103 or 104 is substituted, and activates the architecture simulator 114 when the value of SIG is larger than “0”.

The activated architecture simulator 1
At 14, the input function 115 captures the signal values of each signal line defined in the declaration unit 108, performs internal processing according to the design specifications, and then outputs the signal value to the declaration unit 10 by the output function 116.
An output signal value is set for each signal line defined in 8.

When the execution of the architecture simulator 114 is completed, the process returns to the control definition 107, and the control definition 107 is executed.
After all of the above processes are completed, the logic circuit simulation of the logic circuit 102 is continued.

By repeating the above-described processing, the entire logic circuit is verified by interlocking the logic circuit simulator 101 and the architecture simulator 114.

FIG. 2 is a diagram showing an example of a logic circuit to be verified by the method of verifying a logic circuit according to the present embodiment. In FIG. 2, 201 is a logic circuit, and 202 is AND
Logic element 203, flip-flop logic element, 211
Is an input terminal.

As shown in FIG. 2, in the logic circuit to be verified by the logic circuit verification method of the present embodiment, component connection information for creating hardware is represented by a circuit description.
Each logic element has a unique name for a signal line connecting the logic element, and the circuit description is made in a configuration that does not cause inconsistency in the connection between the logic elements.

For example, the input terminal 21 of the logic circuit 201
1, the signal name DA is input to the input terminal of the AND logic element 202.
The output terminal of the AND logic element 202 is connected to the D input terminal of the flip-flop logic element 203 by the signal name DATA1.

When the logic circuit 201 operates, the signal value of each signal line changes, whereby the signal value is propagated to each logic element, and the logic element connected according to the propagated signal value is designed in hardware. After performing the operation of the logical function defined in the above, the signal value as the operation result is output to the output terminal of the element.

FIG. 3 is a diagram showing an example of the control definition of the verification method of the logic circuit according to the present embodiment. In FIG.
Is a control definition, 302 is a declaration part, 303 is a parameter, 30
4 is a signal line, 310 is a trigger definition unit, and 401 is an architecture simulator.

As shown in FIG. 3, in the logic circuit verification method of this embodiment, the declaration section 302 of the control definition 301
A signal name of the logic circuit 201 is defined as a signal line 304 together with a parameter 303 used as an argument for starting the architecture simulator 401 and passing a signal value,
The logic circuit 201 and the architecture simulator 401 are associated with each other.

Logic circuit 2 defined as signal line 304
When the signal line No. 01 changes, the trigger definition unit 31 using the parameter 303 in which the signal line 304 is defined
0, and after the defined condition is determined, if the condition is satisfied, the architecture simulator 401 defined in the description is started.

When a change occurs in the signal value of the signal line 304 (1) of the signal name DATA1 and the signal line 304 (2) of the signal name CTRL defined in the parameter 303, TRG, the condition definition of the trigger definition section 310 is performed. Is performed, and when the signal value of the signal line 304 (1) of the signal name DATA1 is high and the signal value of the signal line 304 (2) of the signal name CTRL is low, that is, the TRG of the parameter 303 is 2 (10 in binary). , The condition of the trigger definition unit 310 is satisfied, and ARG1 (signal names ADR1, ADR2) and ARG2 (signal name OUT) defined in the declaration unit 302 as arguments
The architecture simulator 401 is started using 1). The activated architecture simulator 401
Performs various internal processes using the arguments ARG1 and ARG2.

FIG. 4 is a diagram showing an example of an architecture simulator of the method of verifying a logic circuit according to the present embodiment. In FIG. 4, reference numeral 401 denotes an architecture simulator.

As shown in FIG. 4, in the logic circuit verification method of this embodiment, the contents existing at the address indicated by ARG1 of MEM, which is the internal memory of the architecture simulator 401, are output to ARG2. That is, the signal name A is read from the internal memory MEM of the architecture simulator 401.
The value existing at the address indicated by DR1 and ADR2 is output to the signal name OUT1.

When the operation of the architecture simulator 401 is completed, the control is returned to the control definition 301 which is the calling source. When the operation of the control definition 301 is completed, the control is returned to the simulation of the logic circuit.

FIG. 5 is a diagram showing a logic expression table of the method of verifying a logic circuit according to the present embodiment. In FIG. 5, 50
1 is a logical expression table, 502 is an element function, 503 is the number of inputs, 504 is the number of outputs, 505 is an element delay, 506
Is an input signal value 1, 507 is an input signal value 2, 508 is an output signal value, 509 is an input 1 connection destination, 510 is an input 2 connection destination, 511 is an output 1 connection destination, 512 is a signal name table pointer, and 513 is a control. This is a definition table pointer.

As shown in FIG. 5, in the method of verifying a logic circuit according to the present embodiment, the logic expression table 501 is a table in which logic elements on the logic circuit are converted into a form in which simulation can be executed. One logic expression table 501 is created for each logic element.

Element function 502 of logical expression table 501
Sets logical elements such as AND and OR, and expresses the operation of each logical expression table 501. The number of inputs 503 and the number of outputs 504 indicate the number of signal lines connected to the input terminal and the output terminal of the logic element, and are required when calculating the output signal value in the element function 502. An output connection destination 51 indicating the number of input signal values 506 of the signal line and a logical expression table to which the signal value is to be propagated
Indicates the number of 1.

The element delay 505 sets the delay time required for outputting the signal value of the logic element, and sets the input signal value 50
When a signal change occurs in the logical expression table 6 and 507, the output signal value 508 of the logical operation result is used as a delay time when the signal is propagated to the logical expression table 501 indicated by the output connection destination 511. That is, if the element delay of the logic element is 2 ns, when the output signal value 508 of the logic element changes, the changed output signal value 508 is propagated to the logic element indicated by the output connection destination 511 after 2 ns.

The signal name table pointer 512 has an address where a signal name table having the signal name of the output terminal of the logic element is stored, and can refer to the name of the output signal of the logic element.

The control definition table pointer 513 indicates that the name of the output signal of the logical expression table 501 is
When it is defined in the declaration section 302, it indicates the name of the output signal and the storage address of the control definition table created from the used trigger definition section 310.

FIG. 6 is a diagram showing a signal name table storing the signal names of the logic circuits to be verified by the logic circuit verification method of this embodiment. In FIG. 6, 520 is a signal name table, 521 is a signal name, 522 is a logical expression table pointer, and 523 is hierarchy information of the signal name table 520.

As shown in FIG. 6, in the method of verifying a logic circuit according to the present embodiment, the signal name table 520 stores all the signal names on the logic circuit to be simulated as signal names 52.
1 and a logical expression table 501 having the signal name
Is stored in the logical expression table pointer 52.
I have 2 This signal name table 520 makes it possible to associate the signal name defined in the declaration section 302 of the control definition 301 with the logical expression table 501.

FIG. 7 is a diagram showing a control definition table storing the contents of the control definition of the logic circuit verification method of the present embodiment. 7, 530 is a control definition table, 53
1 is the number of used parameters, 532 is a condition determination expression, 533 is the number of defined signals of parameter 1, 534 is the signal name table pointer of the defined signal, 535 is the number of defined signals of parameter 2, 53
6 is the signal name table pointer of the definition signal, 537 is the architecture simulator address, 538 is the number of definition arguments, 539 is the number of signal names of argument 1, 540 is the signal name table pointer of argument 1, 541 is the number of signal names of argument 2 , 5
Reference numeral 42 denotes an argument 2 signal name table pointer.

As shown in FIG. 7, the control definition table 530 of the logic circuit verification method of the present embodiment is obtained by converting the contents defined by the control definition 301 into a structure that can be easily handled by simulation. A control definition table 530 is created for each definition unit 310.

A plurality of parameters 303 used as judgment conditions in the trigger definition unit 310 can be used. The number of used parameters 303 is set in the number of used parameters 531, and the number of defined signals for each parameter is set as a parameter. Of the signal name table 520 of the signal line 304 and the signal name table pointer 5
34, 536.

The condition determination statement of the trigger definition unit 310 is set in the condition determination expression 532, and the logic circuit simulator 101 performs the above-described condition determination by using the signal name table pointer of the signal line 304 defined by each parameter. The logical expression table pointer 522 is extracted from the signal name table 520 indicated by, and the output signal value 508 of the logical expression table 501 is extracted and used as the value of the parameter.

When the above condition is satisfied, the control is transferred to the address indicated by the architecture simulator address 537 registered in the control definition table 530, and the architecture simulator is executed. At this time, the address at which the number of definition arguments 538 of the control definition table 530 is stored is passed as an argument to the architecture simulator.

The architecture simulator uses a signal value input function and a signal value output function according to the address 538 of the number of defined arguments given as an argument.
The number of signals 539 and 541 of the argument registered in the control definition table 530 and the signal name table pointers 540 and 542 of the defined signals for the number are referred to.

Next, the architecture simulator refers to the signal name table 520 from the signal name table pointers 540 and 542, and from the logical expression table pointer 522 of the signal name table 520 to the logical expression table 50.
1, the signal value of each signal line is represented by a logical expression table 5
01 from the output signal value 508.

Also, when setting the signal value of each signal line, the signal name table 520 is referred from the signal name table pointer 540 and the signal name table 52
The logical expression table 501 is accessed from the logical expression table pointer 522 of 0, and the signal value is set to the output signal value 508 of the logical expression table 501 of each signal line.

In the following, a description will be given of a procedure for verifying a logic circuit by an event driven method which executes a process when a certain event occurs in the method of verifying a logic circuit according to the present embodiment.

FIG. 8 is a flowchart showing a processing procedure of the method of verifying a logic circuit according to the present embodiment.

FIG. 9 is a diagram showing a time wheel and an event table showing the lapse of time when the method of verifying a logic circuit according to the present embodiment is executed. 9, 700 is a time wheel, 710 is an event table, 711 is an event, and 712 is a flag.

As shown in FIG. 9, in the method of verifying a logic circuit according to the present embodiment, when verifying a logic circuit by event driven, first, an event 7 to be processed in the event table 710 is stored in the time wheel 700.
11 is set, the arrow of the time wheel 700 indicating the simulation time is moved, and the event indicated by the arrow is executed. The event 711 shown in the event table 710 has a flag 712 indicating the type of the event.

In the method of verifying a logic circuit according to the present embodiment, FIG.
As shown in (1), first, in step 601, the logic circuit information is expanded to convert the logic circuit information into a form in which simulation can be executed, and the connection state of each logic element is converted into a logic expression table.

At this time, the number of input terminals and the number of output terminals of each logic element are set to the number of inputs 503 and the number of outputs 504 of the logic expression table 501, respectively, and the input signal values 506 and 507 and the output signal A storage area for storing the value 508 is secured.

The connection destinations of the signal lines connected to these terminals are extracted from a netlist or the like, and the connection destinations 509 and 510 and the output connection destination 511 are assigned the head address of the logical expression table of the connection destination. Set.

The signal line connected to each input / output terminal has its signal name stored in the signal name table 520.
1 and when the signal line is connected to the output terminal, the head address of the logical expression table 501 is registered in the logical expression table pointer 522 of the signal name table 520 and the signal name table pointer 512 of the logical expression table 501 is also registered. , An address of a signal name table in which the signal names are registered. The hierarchical information such as the instance name existing in the netlist is stored in the signal name table 52.
It is registered as the layer information 523 of 0.

After the logical expression table 501 and the signal name table 520 of all the logic circuits to be verified are created, in step 602, the control definition 301 previously created in the storage medium such as a card as input information and the program language are used. The architecture simulator 401 that has been created and converted into an executable format is read, and a control definition table 530 is created.

The number of used parameters 531 of the control definition table 530 sets the number of parameters 303 used for the determination condition of the trigger definition section 310 of the control definition 301, and the condition determination expression 532 for each parameter is AND, O
It is registered with a logical expression such as R and a comparison operator.

The definition contents of the parameter 303 used for the judgment condition are as follows.
3, 535 are set, and the signal name table pointers 534, 536 of the defined signals are set according to the set number of defined signals.

After setting the contents of the parameters used for the judgment conditions and setting the simulation time to “0”, the number of parameters is registered in the number of defined arguments 538,
The number of signal names is set to the signal name number 539 of the argument, and the signal name table pointer is set to the signal name table pointer 540 of the argument.
Set to.

After setting the signal name table pointers 540 for the number indicated by the signal name number 539 of the argument, the signal name number 541 for the next argument and the signal name table pointer 542 of the signal name as a component thereof are sequentially set. Set.

At step 603, the called architecture simulator is dynamically arranged on the memory, and its logical address is set to the architecture simulator address 537.

[0093] If there is a control definition to perform a plurality of architecture simulator under the same judgment condition of the
Repeat setting to complete the control definition table 530.

In step 604, if a different judgment condition exists, steps 602 to 603 are repeated for that judgment condition, and a control definition table 530 is created for all the judgment conditions.

In the next step 605, an input test pattern created and prepared in advance in a storage medium is read, and an input signal value of a signal line corresponding to the input test pattern is stored in a logical expression table 501 as a connection destination of the signal line. And registers the address of the logical expression table 501 in the event 711 of the event table 710 connected to the time “0” of the time wheel 700 as an event for starting the logic circuit simulation.

After setting all of the input initial values in the logical expression table 501 and completing the registration of the event 711 based on the signal value, the logic circuit simulation is executed from step 606 according to the simulation time.

That is, in step 606, the events 711 existing in the event table 710 connected to the corresponding time of the time wheel 700 indicating the simulation time are sequentially fetched, and when the flag 712 is "0", the processes of steps 608 and 1 are performed. Time step 609
Is executed (step 607).

At step 608, the input signal values 506 and 507 of the logical expression table 501 indicated by the event 711
, An output signal value based on the element function 502 is calculated, and the output signal value 508 is set to the output signal value.

The logical expression table 5 of the relevant logic element
The value (address) of the output connection destination 511 which is the connection destination of the output signal line of the logic element is registered as the event 711 on the event table 710 connected to the time wheel 700 at the time when the element delay 505 of the logical element 01 is added. I do.

At this time, when the control definition table pointer 513 on the logical expression table 501 is other than zero (that is, when the control definition table is connected to the logical expression table 501), the control definition table pointer 513 of the connection destination is also changed. Event 71 on the event table 710
Registered as 1 and set the flag 712 to “1”. When the flag 712 of the event 711 is "1", it indicates that the event is for the control definition table 530.

At step 609, the processing of the control definition table 530 indicated by the event 711 is executed. First, the signal name table 520 is extracted from the signal name table pointer 534 of the parameter number indicated by the used parameter number 531 of the control definition table 530, and the logical expression table 5 indicated by the logical expression table pointer 522 defined therein is extracted.
After calculating the input signal value of each parameter from the output signal value 508 in 01 and executing the condition determination formula 532, if the above condition is satisfied, the address of the signal names 53 9 and 541 of each argument of the control definition table 530 is obtained. Is transferred to the address indicated by the architecture simulator address 533 using the argument as an argument.

That is, at this point, the architecture simulator is called. In the called architecture simulator, the input function that reads the signal value according to the passed argument transmits the signal name table 5 from the signal name table pointers 540 and 542 of the corresponding argument in the control definition table 530.
An input signal value can be obtained by reading the output signal value 508 set in the logical expression table 501 via the interface 20.

In a signal value output function for setting an output signal value, a target value is set in the output signal value 508 of the logical expression table 501 in the same manner, and the output connection destination 511 is set.
Table after the element delay 505
0 is registered as an event 711.

Step 605 is repeated until there is no event 711 on the event table 710 at the same time as the simulation time being executed (step 61).
0), advance to the next simulation time (step 61)
1), These processes are repeated until the simulation end time (step 612).

As described above, according to the logic circuit verification method of the present embodiment, the architecture simulation is executed during the logic circuit simulation by referring to the control definition that defines the execution conditions of the architecture simulation. The circuit can be efficiently verified.

Further, according to the logic circuit verification method of the present embodiment, the architecture simulation is executed without adding a verification circuit for executing the architecture simulation to the logic circuit data. It is possible to verify a logic circuit without duplication.

A procedure for creating diagnostic data of a logic circuit in the method of verifying a logic circuit according to the present invention will be described below.

In the method of verifying a logic circuit according to the present embodiment, a logic circuit simulation and an architecture simulation are executed using logic circuit data describing the logic circuit, and the operation of each part of the logic circuit and the execution on the logic circuit are performed. A simulation of software to be performed is performed to calculate a signal value of each unit of the logic circuit, and the signal value is stored in a storage device.

Next, when measuring an electric signal on a logic circuit created based on the logic circuit data, the simulation result of a signal line to be measured is extracted,
Diagnostic data of the measurement location is created.

That is, the instance name indicating the physical hierarchical description described in the hierarchical information 523 of the signal name table 520 is extracted, and the signal name 52 having the same instance name is extracted.
1, that is, the signal value of the signal line of the hierarchy is extracted from the signal value stored in the storage device to create diagnostic data of the logic circuit.

Next, the logic circuit created based on the logic circuit data is actually operated to measure the electric signal of each part on the logic circuit, and the measured value is compared with the diagnostic data. Is used to verify the logic circuit.

As described above, in the logic circuit verification method of the present embodiment, since the diagnostic data of the logic circuit is created based on the result of the logic circuit simulation and the architecture simulation, the diagnostic data of the logic circuit can be created at high speed. Is possible.

Although the present invention has been described in detail with reference to the above embodiment, the present invention is not limited to the above embodiment, but may be variously modified without departing from the scope of the invention. Of course.

[0114]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by referring to the control definition defining the execution conditions of the architecture simulation, the architecture simulation is executed during the logic circuit simulation, so that the logic circuit can be efficiently verified.

Further, since the architecture simulation is executed without adding a verification circuit for executing the architecture simulation to the logic circuit data describing the logic circuit, the verification of the logic circuit can be performed without duplicating the logic circuit data. It is possible to do.

In the method of verifying a logic circuit according to the present invention,
Since the diagnostic data of the logic circuit is created based on the result of the logic circuit simulation and the architecture simulation, the diagnostic data of the logic circuit can be created at high speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a logic circuit simulator and an architecture simulator for implementing a logic circuit verification method of the present invention.

FIG. 2 is a diagram illustrating an example of a logic circuit to be verified by the logic circuit verification method according to the embodiment;

FIG. 3 is a diagram illustrating an example of a control definition of a method of verifying a logic circuit according to the embodiment;

FIG. 4 is a diagram illustrating an example of an architecture simulator of the logic circuit verification method according to the embodiment;

FIG. 5 is a diagram illustrating a logic expression table of a method of verifying a logic circuit according to the embodiment;

FIG. 6 is a diagram illustrating a signal name table in a method of verifying a logic circuit according to the embodiment;

FIG. 7 is a diagram illustrating a control definition table of a logic circuit verification method according to the present embodiment.

FIG. 8 is a flowchart illustrating a processing procedure of a logic circuit verification method according to the present embodiment.

FIG. 9 is a diagram showing a time wheel indicating an elapse of time and an event table when the processing of the method of verifying a logic circuit according to the embodiment is executed.

[Explanation of symbols]

101: logic circuit simulator, 102: logic circuit, 1
03: signal line, 104: signal line, 108: declaration section, 10
9: trigger definition unit, 110: architecture simulator call, 111: return from architecture simulator, 114: architecture simulator, 201
... Logic circuit, 301 ... Control definition, 302 ... Declaration part, 30
3 ... parameters, 304 (1), 304 (2) ... signal lines,
Reference numeral 310 denotes a trigger definition unit, 401 denotes an architecture simulator, 501 denotes a logical expression table, 520 denotes a signal name table, 530 denotes a control definition table, 700 denotes a time wheel, 710 denotes an event table, 711 denotes an event, and 712 denotes a flag.

Continuation of the front page (56) References JP-A-2-268341 (JP, A) JP-A-63-292337 (JP, A) JP-A-2-81236 (JP, A) JP-A-5-128196 (JP) JP-A-6-35988 (JP, A) JP-A-6-162130 (JP, A) JP-A-62-219137 (JP, A) JP-A-2-210552 (JP, A) 2-73469 (JP, A) Masahiro Kurashita, 3 others, "Efficient Logic Verification by Ultra-High Speed Simulator (HAL)", Proc. Of the IPSJ National Convention, IPSJ, 1988, Vol. 3, p. 1761-1762 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50 664

Claims (3)

(57) [Claims] 1. Design of a logic circuit using a CAD system
A logic circuit describing the operation of the logic circuit based on specifications
Data is input to the CAD system and the logic circuit data is input.
Verification of the logic circuit using the data
A method, whether the logic circuit logic circuit simulation and wherein performing architecture simulation to simulate the process of software running on the logic circuit logic circuit for simulating the operation of the meets its design specifications A method of verifying a logic circuit, wherein a control definition table defining execution conditions of the architecture simulation is stored in a memory in the CAD system.
Placed above, to simulate the operation of the logic elements constituting the logic circuit portion for the logic circuit portion of the the logic circuit performs the logic circuit simulation, obtained by the results of the logic circuit simulation signal
The value is stored in a predetermined memory area, and the predetermined memory
The running architecture simulation when the signal value stored in the rear is the execution condition is satisfied in the control definition table, obtained by the logic circuit simulation and results of the architecture simulation
A method for verifying a logic circuit, comprising: comparing the obtained signal value with a design specification of the logic circuit to verify the entire logic circuit. 2. Designing a logic circuit using a CAD system.
A logic circuit describing the operation of the logic circuit based on specifications
Data is input to the CAD system and the logic circuit data is input.
Verification of the logic circuit using the data
A method, whether the logic circuit logic circuit simulation and wherein performing architecture simulation to simulate the process of software running on the logic circuit logic circuit for simulating the operation of the meets its design specifications in the verification method of the logic circuit for verifying a distribution on memory in the CAD system control definition table which defines the condition for executing the architecture simulation is made without changing the description of the logic circuit
And simulates the operation of the logic elements constituting the logic circuit portion for a certain logic circuit portion of the logic circuit, executes the logic circuit simulation, and obtains a signal value obtained as a result of the logic circuit simulation.
Stored in a predetermined memory area, and stored in the predetermined memory area.
When the stored signal value satisfies the execution condition in the control definition table , the architecture simulation is executed, and the simulation is performed based on a result of the logic circuit simulation and the architecture simulation .
A method for verifying a logic circuit, comprising comparing a signal value with a design specification of the logic circuit to verify the entire logic circuit. 3. A method of creating the diagnostic data to which the logic circuit electrical signals measured by the logical circuit to verify whether it meets the design specifications, claims 1 or
According to the logic circuit verification method described in either
The diagnostic data of the logic circuit is created from the obtained signal values.
Diagnostic data creation method, characterized in that: