JPH0887532A - Logic circuit verification method and bi-directional buffer circuit - Google Patents

Abstract

PURPOSE: To save the labor and time of a user and also to improve the accuracy of verification when the function and the operation of a logic circuit are verified by a logical simulator. CONSTITUTION: A logic circuit includes a bi-directional buffer circuit 10 consisting of a tri-state output buffer gate B1 and an input buffer gate B2. In such a constitution of the logic circuit, it is difficult to verify its operation against the collision between a signal I1 produced from the output U of the gate B1 and an external signal IO1. In this respect, an input/output state detection circuit 12 is especially added so that the collision can be easily detected between both signals I1 and IO1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, while operating a simulated logic circuit on the basis of circuit information data indicating the configuration of the verified logic circuit, inputs and outputs signals to and from the outside of the verified logic circuit. Of the internal net signal and the logic state of the internal net signal, and based on these observation results, the logic circuit verification method for verifying the function and operation of the logic circuit to be verified. Bi-directional buffer circuit consisting of a tri-state logic gate for input and a logic gate for input, and especially, at the same time while verifying the function and operation of the logic circuit to be verified while reducing the user's time and effort. The present invention relates to a logic circuit verification method and a bidirectional buffer circuit that can further improve the accuracy of.

[0002]

2. Description of the Related Art Due to widespread use of computer devices and advances in software technology, for example, EWS
A CAD (computer aided design) device using a computer device such as an (engineering workstation) has been widely used.

For example, such a CAD device is also used for designing a logic circuit incorporated in an integrated circuit or the like. The CAD device used to design an integrated circuit is
For example, based on the concept of hierarchical design, logical circuits are sequentially designed and input while defining a hierarchical block by a set of adjacent logical circuit elements and using block symbols corresponding to the hierarchical block. That is.

CAD used for designing such an integrated circuit
In the device, there is a device called a logic simulator, which has a function of a logic simulation in which a designed logic circuit is simulatedly operated on a computer device. Alternatively, a CA for designing such an integrated circuit
There is also a logic simulator which performs a logic simulation in another computer device based on the circuit information data of the designed circuit obtained by the D device.

Whether configured as one computer together with a CAD device for designing the integrated circuit or separately configured, the logic simulator as described above has circuit information indicating the configuration of the logic circuit to be verified. Based on the data, for example, circuit information data indicating the elements to be configured and their connections, the function and operation of the logic circuit to be verified are verified while the logic circuit to be verified is simulated.
That is, while simulating the operation as described above, the logic state of the signal input / output to / from the outside of the logic circuit to be verified is observed, and the logic state of the signal of the internal net (wiring) is observed, Based on these observation results, the function and operation of the verified logic circuit are verified.

For example, in a semiconductor integrated circuit or the like, many steps are required to obtain a prototype for verifying its function and operation, and a great deal of cost and time are required. Therefore, according to the logic simulator as described above, the function and the operation can be verified by the computer device or the like, centering on the circuit information data of the designed logic circuit, even without the prototype. It has many advantages. For example, it is possible to find many existing defects in the function and operation of the logic circuit to be verified in a relatively short period of time. Therefore, the cost required for designing the semiconductor integrated circuit and the design period can be further reduced.

However, in such a logic simulator, in particular, a bidirectional buffer circuit composed of an output tristate logic gate such as a tristate output buffer gate and an input logic gate such as a general input buffer gate. With respect to the logic circuit to be verified having the above, various ingenuities were required when verifying its function and operation by the logic simulator.

This is because the output side of such a bidirectional input / output buffer transmits signals bidirectionally. That is, since the output of such a bidirectional buffer circuit is tri-stated and the logical state changes, the logical state of the output of the bidirectional buffer circuit and the logical state input to the bidirectional buffer circuit from the outside This is because it is necessary to make a special distinction. In such a bidirectional buffer circuit, for example, it becomes difficult or impossible to verify the function and operation of the signal direction switching signal for switching the signal direction in the bidirectional buffer circuit. There were cases where it would end up.

Conventionally, when verifying the function and operation of such a bidirectional buffer circuit, the device shown in FIG. 9 is used. In FIG. 9, when verifying the function and operation of the bidirectional buffer circuit 10B in the logic circuit to be verified, it is called a dummy gate and the buffer gate B3 is connected. Thereby, with respect to the bidirectional signal input / output to / from the bidirectional input / output IO of the bidirectional buffer circuit 10B from the outside of the bidirectional buffer circuit 10B, a signal is particularly output from the bidirectional input / output IO to the outside. It is possible to clearly distinguish the input (output O) from the input and the input (input I2) to the bidirectional input / output, in particular, which inputs a signal from the outside.

As shown in FIG. 9, the buffer gate B3
With the above, the verification of the logic circuit to be verified centering on the signal direction switching signal C can be performed as follows.

(1) When the logic state of the signal Y in FIG. 9 becomes indefinite during the logic simulation:
In this case, the logic state of "1" or "0" output from the bidirectional buffer circuit 10B and the buffer gate B
It is determined that the logical state of "0" or "1" output from the output terminal 3 collides with each other and the mutual logical states do not match. In such a case, there is a problem in the signal direction switching signal C, and therefore the bidirectional buffer circuit 1
Where the output of the tristate buffer gate B1 of 0B must be in a high impedance state,
It is considered that the logical state of "1" or "0" has been reached.

(2) When the signal Y is in a high impedance state: When the signal Y, which originally has a logic state of "1" or "0", is in a high impedance state, the signal direction switching signal C When the output of the tri-state buffer gate B1 of the bidirectional buffer circuit 10B becomes the logic state of "1" or "0", it becomes a high impedance state. Determine that

As described above, by providing the buffer gate B3 as a dummy gate as shown in FIG. 9, various problems concerning the bidirectional buffer circuit 10B are found by the logic circuit verification performed while performing the logic simulation. It is possible.

On the other hand, with respect to the circuit to be verified having the bidirectional buffer circuit, the function and the operation are verified while performing the logic simulation, especially the signal direction switching signal C.
It is also said that the verification of the operation and function of is performed based on the log of the simulation result and the input pattern.

That is, the log of the logic state of the signal direction switching signal C, the log of the logic state of the tristate buffer gate B1 of the bidirectional buffer circuit 10B (also serving as the tristate), and the bidirectional buffer. Circuit 1
Logs of logic state (also known as tri-state) input from 0B to the outside and other input patterns are compared with each other, and while examining whether there is any contradiction between them, This is to verify the function and operation of the logic circuit to be verified.

[0016]

However, when verifying the operation and function of the logic circuit to be verified having the bidirectional buffer circuit by the logic simulation as described above, the buffer gate B3 is dummy as shown in FIG. When provided as a gate, there are the following problems.

(1) The output of the tri-state buffer gate B1 of the bidirectional buffer circuit 10B of FIG. 9 is "1" or "0", and the output of the buffer gate B3 is "1" or "0". ", And even if the signals collide,
The logic state of the signal Y may not be indefinite.
That is, when the two outputs collide with each other and the logic state of the tri-state buffer gate B1 and the logic state of the buffer gate B3 coincide with each other, the logic state of the signal Y is not indefinite. Therefore, even if the two outputs collide with each other due to a defect in the signal direction switching signal C or the like, if the two colliding logic states match, the signal Y does not become indefinite. The defect cannot be detected.

(2) The buffer gate B3 shown in FIG.
By providing, the operating condition of the logic circuit to be verified is different from the actual condition. The buffer gate B3 is a dummy gate and does not exist in the original logic circuit to be verified. Therefore, by providing the buffer gate B3 as described above, the value of the wiring capacitance (temporary wiring capacitance in the logic simulation) of the wiring to which the buffer gate B3 is connected, the layout, etc., are the same as those of the original logic circuit to be verified. It will be different. For this reason, the accuracy of the logic simulation, such as the operation timing, at the time of verifying the logic circuit decreases. In order to reduce such a problem, the process of ignoring the influence of the provision of the buffer gate B3 may be performed, and the back annotation of the change in the tentative wiring capacitance and the layout due to the provision of the buffer gate B3 may be performed. Conceivable. However, the number of man-hours and the time required for such processing increase. In particular, in a large-scale circuit, such an increase in man-hours and time cannot be ignored.

On the other hand, when verifying the function and operation of the logic circuit to be verified having the bidirectional buffer circuit while performing logic simulation, in particular, as described above, it should be performed based on the log of the logic simulation result. If set to, there are the following problems.

(1) For example, in the bidirectional buffer circuit 10B shown in FIG. 9 and FIG. 1 described later, after the logic state of the signal direction switching signal C changes, the logic of the output of the tristate buffer gate B1. There is a delay before the state changes. However, the log of the logic state of the signal direction switching signal C, the log of the logic state of the output of the tri-state buffer gate B1, and the bidirectional input / output IO of the bidirectional buffer circuit 10B are externally input. Such delay times can hardly be taken into consideration when comparing and examining these logs such as the log of the logic state of a signal. For this reason, there is a problem that the accuracy of verification of the function or operation is reduced.

(2) There is a problem that the log of the target logic simulation result generally becomes huge, and the time for analyzing such a huge log increases. In particular, the larger the circuit scale of the logic circuit to be verified and the longer the time of the logic simulation at the time of verification, the larger the log of the result, and the processing required for the analysis based on the log accordingly. The time etc. will increase.

The present invention has been made to solve the above-mentioned conventional problems, and at the same time, saves the user's trouble when verifying the function and operation of the logic circuit to be verified, and at the same time, the accuracy of the verification. It is an object of the present invention to provide a logic circuit verification method capable of further improving the above and a bidirectional buffer circuit used in such a logic circuit verification method.

[0023]

First, in the logic circuit verification method of the first invention of the present application, the simulated logic circuit is operated based on the circuit information data indicating the configuration of the verified logic circuit, The logic state of the input / output signal to / from the outside of the verified logic circuit is observed, and the logical state of the signal of the internal net is observed, and the function and operation of the verified logic circuit are checked based on these observation results. In the method for verifying a logic circuit to be verified, the output of the output tri-state logic gate is set to U with respect to the verified logic circuit having a bidirectional buffer circuit composed of an output tri-state logic gate and an input logic gate. A bidirectional input / output of the bidirectional buffer circuit in which the input of the input logic gate is V, and the output U and the input V are connected at a normal time other than the logic circuit verification. The when the IO, there these output U, the input V and bidirectional input-output IO, the input I
1 is connected to the output U and its output Y1 is the input V
An input / output state verification circuit having an input I1, an output Y1, and a bidirectional input / output IO1 connected to the bidirectional input / output IO1 at least during the logic circuit verification, The input / output state verification circuit determines the logical state output from the output Y1 based on the logical state input to the input I1 and the logical state input to the bidirectional input / output IO1. , The input I1 and the bidirectional input / output IO1 while operating the logic circuit to be verified while determining the logic state output from the bidirectional input / output IO1.
The object is achieved by observing the logic state of the signal and verifying the function and operation of the logic circuit to be verified.

In the logic circuit verification method of the first aspect of the invention, the logic state of the input I1 and the bidirectional input / output I
When the logic state of O1 is the same fixed value, the first error information used for the logic circuit verification is generated, and these input I
When the logic state of 1 and the logic state of the bidirectional input / output IO1 are both high impedance, the above problem can be achieved by generating the second error information utilized for the logic circuit verification, and the minimum error can be achieved. By generating only the information, the work efficiency of the entire logic circuit verification including the parts other than the bidirectional buffer circuit is further improved.

In the logic circuit verifying method of the second invention of the present application, the logic circuit to be verified is simulated while operating the logic circuit to be verified on the basis of circuit information data indicating the configuration of the logic circuit to be verified. A logic circuit verification method for observing the logic state of an input / output signal with respect to the outside, observing the logic state of a signal for an internal net, and verifying the function and operation of the logic circuit to be verified based on these observation results. In the above-mentioned, in the logic circuit to be verified having a bidirectional buffer circuit composed of an output tristate logic gate and an input logic gate, first, based on the input logic state of the output tristate logic gate, In consideration of the signal delay time, the buffer side logic state I1 to be output is obtained, and the output of the output tri-state logic gate and the output Output to the bidirectional input / output IO of the bidirectional buffer circuit to which the inputs of the output logic gates are connected together, and the paired buffer logical state IO1 input from the outside of the bidirectional buffer circuit is obtained. I
The object is achieved by generating error information utilized for logic circuit verification based on 1 and the paired buffer logic state IO1.

On the other hand, in the bidirectional buffer circuit of the third invention of the present application, in the bidirectional buffer circuit composed of the output tristate logic gate and the input logic gate, the output of the output tristate logic gate is set to U. , When the input of the input logic gate is V and the bidirectional input / output of the bidirectional buffer circuit is IO, the output U, the input V, and the bidirectional input / output IO have their input I1. Are connected to the output U, the output Y1 is connected to the input V, and the bidirectional input / output IO1 is connected to the bidirectional input / output IO. These input I1, output Y1 and bidirectional input / output IO1 An input / output state detection circuit having the input / output state detection circuit, and the input / output state detection circuit is input to the input I1 and the bidirectional input / output IO1. The above object can be achieved by determining the logic state output from the output Y1 based on the logic state and determining the logic state output from the bidirectional input / output IO1. And a bidirectional buffer circuit that can be used in the logic circuit verification method of the first invention, the logic circuit verification method of the second invention, and the like.

[0027]

FIG. 1 is a circuit diagram of a general bidirectional buffer.

As shown in FIG. 1, the bidirectional buffer 10B includes a tri-state output buffer gate B1 and
It is composed of an input buffer gate B2.

When the output of the tristate output buffer gate B1 is U and the input of the input buffer gate B2 is V, the output U and the input V are bidirectional input / output of the bidirectional buffer 10B. It is connected to IO. Also, the tri-state output buffer gate B
The input of 1 is the input I of the bidirectional buffer 10B. The output of the input buffer gate B2 is the output Y of the bidirectional buffer 10B.

When verifying the function and operation of the circuit under test having such a bidirectional buffer circuit 10B, in the first to third inventions, the logical state output from the tristate output buffer gate B1 and While observing a logical state input from the outside of the bidirectional buffer 10B to the bidirectional input / output IO of the bidirectional buffer 10B,
I try to verify its function and operation.

The output U of the tristate output buffer gate B1 is not limited to this.
Of the tristate output buffer gate B
It can be calculated based on the logic state input by 1.

Therefore, first, in the first aspect of the invention, as shown in FIG.
To the bidirectional buffer circuit 10 in the logic circuit to be verified,
In particular, the input / output state detection circuit 12 is provided.

The input / output state detection circuit 12 has inputs I1,
It has an output Y1 and a bidirectional input / output IO1. The input / output state detection circuit 12 has its input I1 connected to the output U of the tri-state output buffer gate B1 and its output Y1 connected to the input V of the input buffer gate B2. Has been done. Further, the bidirectional input / output IO of the input / output state detection circuit 12 is connected to the bidirectional input / output IO.

The operation of the input / output state detection circuit 12 thus connected is as follows. First, the bidirectional buffer circuit 10 provided with the input / output state detection circuit 12 is the same as the bidirectional buffer circuit 10B. Is made to operate. Therefore, in the input / output state detection circuit 12,
Based on the logic state input to the input I1 and the logic state input to the bidirectional input / output IO1
The logic state output from the output Y1 is determined. Also, based on the logical state input to the input I1 and the logical state input to the bidirectional input / output IO1,
The logical state output from the bidirectional input / output IO1 is determined.

At the same time, in the input / output state detecting circuit 12 as described above, in the first invention, the logical state of the signal of the input I1 and the logical state of the signal of the bidirectional input / output IO1 are observed, The function and operation of the logic circuit to be verified are verified.

For example, even in the conventional logic simulator, the logic state of the output U of the tristate output buffer gate B1 is "1",
It can be determined whether it is "0" or in a high impedance state. Furthermore, it is possible to determine whether the logic state of the output U is indefinite.

On the other hand, the logic state input from the outside of the bidirectional buffer circuit 10 and input to the bidirectional input / output IO1 is set to "1", "0" or high according to a conventionally used logic simulator. It can be determined whether it is in the impedance state. Furthermore, even with a conventional logic simulator, it is possible to determine whether the logic state input to the bidirectional input / output IO1 is indefinite.

Here, in the first aspect of the invention, the logic state of the input I1 and the logic state of the bidirectional input / output IO1 are observed while observing the logic to be verified in which the bidirectional buffer circuit 10 is used. The function and operation of the circuit can be verified.

The second invention is similar in concept to the first invention, and basically the same. That is, first, the first aspect of the invention has the input / output state detection circuit 12 as shown in FIG.
It is a logic circuit verification method using the bidirectional buffer circuit 10. On the other hand, in the second invention, based on the same principle as the first invention, the input / output state detection circuit 12 is virtually considered and the function and operation of the similar logic circuit are verified. .

That is, according to the second aspect of the invention, the tri-state output buffer gate B1 has a logic state of the output U (on the buffer side) based on the input logic state while considering the signal delay time. Seeking the logic state I1). Further, in the second aspect of the invention, a logical state (to the buffer logical state IO1) that is input from the outside of the bidirectional buffer circuit 10 and is input to the bidirectional input / output IO1 is obtained. Further, error information utilized for logic circuit verification is generated based on the logic states I1 and IO1 thus obtained.

The bidirectional buffer circuit of the third aspect of the invention is the bidirectional buffer circuit 10 used in the first aspect of the invention. That is, in addition to the tri-state output buffer gate B1 and the input buffer gate B2,
The input / output state detection circuit 12 as described above is provided.

In the first to third inventions, for example, the tri-state output buffer gate B1 and the input buffer gate B2 shown in FIG. 2 are not limited to literal buffer gates. . That is, the tristate output buffer gate B1 may be a tristate output, and may be, for example, a tristate output AND logic gate or the like, or a tristate output OR logic gate. Similarly, the input buffer gate B2 is not limited to a simple buffer gate,
It may have more functions and may be, for example, an AND logic gate or an OR logic gate.

According to the first to third inventions described above, as compared with the case where the function or operation of the logic circuit is detected by using the buffer gate B3 serving as the dummy gate as shown in FIG. , Has the following advantages.

That is, when verifying the function and operation of the logic circuit based on the observation of the logic state of the signal of the input I1 and the logic state of the signal of the bidirectional input / output IO1, the tristate output buffer gate B1 Even when the output and the input from the outside to the bidirectional input / output IO of the bidirectional buffer circuit collide in the same logic state,
It is possible to detect the defect. Also, in FIG.
Since a dummy gate such as the buffer gate B3 is not used, the dummy gate does not change the operating conditions such as the wiring capacitance (temporary wiring capacitance in the logic simulation).

Further, according to the first invention to the third invention, the following is compared with the above-mentioned verification of the function and operation of the conventional logic circuit centering on the log of the logic simulation result. Have advantages.

That is, the logic state output from the output U of the tri-state buffer B1 is obtained by a logic simulator and is input to the tri-state output buffer gate B1 in consideration of the delay time of signals and operations. It is calculated based on the logical state. Therefore, the first
According to the invention to the third invention, it is possible to verify the function and operation of the logic circuit to be verified according to the actual operation timing of each logic gate. Further, since the log of the logic simulation result is not analyzed, the processing time required for log analysis can be reduced.

[0047]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 shows the third circuit in which the logic circuit is verified while applying the first invention or the second invention.
1 is a circuit diagram of an embodiment of a logic circuit to be verified having a bidirectional buffer circuit to which the invention is applied.

As shown in FIG. 3, the logic circuit under test 14 of the present embodiment has a signal input terminal CIN, a signal direction switching signal input terminal CTL, and a signal output terminal COUT.
It has a bidirectional input / output terminal IO. The verified logic circuit 14 has inverter gates IV1 and IV2 in addition to the bidirectional buffer circuit 10 to which the third invention is applied. The inverter gates IV1 and IV2 and the bidirectional buffer circuit 10 are provided with "I1",
Instance names of "I2" and "I3" for identifying each logic gate in the logic circuit under verification 14 are given.

These terminals CIN, CTL, COU
The same symbols are used for the respective signals in T and IO. The bidirectional buffer circuit 10 is the same as that shown in FIG.
Have.

FIG. 4 is a time chart showing an operation example of the logic circuit to be verified of the present embodiment.

In the time chart of FIG. 4, first, in the period from time 0 to time 20, the bidirectional switching signal CTL is in the L state. Therefore, the output of the tristate output buffer gate B1 of the bidirectional buffer circuit 10 is the same as the logical state input to the input I of the bidirectional buffer circuit 10, and the output of the tristate output buffer gate B1 is input to the tristate output buffer gate B1. It is the same as the input logic state.

Therefore, during the period from time 0 to time 10, the input signal CIN in the H state is input to the inverter IV1 and inverted by the inverter gate IV1. The L state is output. During the period from time 0 to time 10, the bidirectional input / output signal IO input from the outside is in the H state, so the bidirectional input / output signal IO collides with the output of the tristate buffer B1. At this time, the logic state of the output U of the tri-state buffer B1 is "L state", while the logic state of the bidirectional input / output signal IO is H state. Therefore, the final bidirectional input / output signal IO becomes indefinite.

Next, during the period from time 10 to time 20,
The input signal CIN in the L state is inverted by the inverter IV1. Therefore, the output U of the tri-state output buffer gate B1 outputs the H-state logic state. The logic state of the output U collides with the bidirectional input / output signal IO which is not in the high impedance state. Here, since the logic state of the output U is the H state and the logic state of the bidirectional input / output signal IO is also the H state,
The final bidirectional input / output signal IO also becomes H state.

Then, during the period from time 20 to time 40, the signal direction switching signal CTL is in the H state. Therefore, the output U of the tristate output buffer gate B1 in the bidirectional buffer circuit 10 is in a high impedance state.

Here, during the period from time 20 to time 30, the bidirectional input / output signal IO from the outside is in a high impedance state. Therefore, the bidirectional input / output signal IO from the outside as well as the output U of the tristate output buffer gate B1 are both in a high impedance state.

Subsequently, in the period from time 30 to time 40, the bidirectional input / output signal IO input from the outside is at L level.
It is in a state. At this time, since the output of the tri-state output buffer gate B1 is in a high impedance state, the final bidirectional input / output signal IO is also in the logical state input from the outside, that is, the L state.

As described above, in the operation example shown in the time chart of FIG. 4, a total of three signal states considered to be defective are observed.

That is, first, from time 0 to time 10, the output U of the tristate output buffer gate B1 collides with the bidirectional input / output signal IO from the outside. Secondly, from time 10 to time 20 as well, the output U collides with the bidirectional input / output signal IO from the outside. Thirdly, in the period from time 20 to time 30, both the output U of the tri-state output buffer gate B1 and the bidirectional input / output signal from the outside are both in a high impedance state.

FIG. 5 is a flow chart showing the processing of the main part of the logic circuit verification method of this embodiment.

In FIG. 5, in this embodiment,
In particular, the processing centering on the part to which the logic circuit verification method of the first invention and the second invention is applied is shown. That is, the processing is mainly shown for verifying the presence / absence of a defect in the logic circuit to be verified, especially in the bidirectional buffer circuit.

In the flowchart of FIG. 5, first, in step S110, it is determined whether a processing request event has occurred. This event occurs when the logical state of a signal changes, especially when it changes. For example, such an event changes the logical state of the signal I1 output from the tri-state buffer B1 shown in FIG. 2 or the signal input from the outside of the bidirectional buffer circuit 10. This occurs when the logical state of IO1 changes. In step S110, when an event occurs, the process proceeds to step S112, and when it is determined that the event has not occurred, the step S11
Branch to the front of 0.

Next, in step S112, the logical state of the required signal is extracted, including the logical state of the signal whose logical state has changed, in accordance with the determination of the event occurrence. For example, when the occurrence of an event is determined for the signals I1 and IO1, the logical states of the signals I1 and IO1 at that time are extracted. The logic states of these signals I1 and IO1 are
All of them are tri-states, and in addition to any one of these "1", "0", and high impedance states, this embodiment also has a "undefined" logic state. This indeterminate logical state is one in which the logical state is not determined due to signal collision or the like.

After this, the following steps S114 and S12
For 0, a specific process to which the first to third inventions are applied is performed. That is, it is input to the bidirectional buffer circuit 10, particularly to the input / output state detection circuit 12,
The processing concerning the signals I1 and IO1 is performed.

First, in step S114, the signal I
It is determined whether the logical states of 1 and IO1 are both definite values. That is, even if the logic states of these signals I1 and IO1 are not the same logic state, it is determined whether or not they are in the logic state of "1" or "0", respectively. If the signals I1 and IO1 are both definite values as a result of such a determination, then step S11 is performed.
6, the process proceeds to step S120 if either one is not the definite value.

In step S120, it is determined whether the logic states of the signals I1 and IO1 are both high impedance states. If the logic states of these signals I1 and IO1 are both in the high impedance state, the process proceeds to step S116. On the other hand, if at least one of them is not in the high impedance state, the process branches to the front of step S110.

Here, in step S116, the signal I
1 outputs an error message according to the logic state of the signal IO1. This error message is used to verify the function and operation of the logic circuit. Regarding the error message, for example, the contents thereof, see FIG. 6 and FIG.
Will be described later in detail.

FIG. 6 is a diagram showing an operation of the input / output state detection circuit used in this embodiment, showing a correspondence table of the input / output signals and output message table pointer MTP.

In FIG. 6, first, the input / output state detection circuit 12 for the combination of the logical states of the signals I1 and IO1 input to the input / output state detection circuit 12 is described.
The logic state of the signal IO1 and the logic state of the signal Y1 output from the are shown. Further, in FIG. 6, the value of the output message table pointer MTP with respect to the combination of the logical states of the signals I1 and IO1 input to the input / output state detection circuit 12 is shown.

Output message table pointer MTP
Is used to search the output message table of FIG. 7 described later. That is, the output message table pointer M
TP is the address of the output message table. When the value of the output message table pointer MTP is "1" or "2", the message content corresponding to this is obtained in the output message table. On the other hand, the output message table pointer MTP is "-".
If so, the value of the pointer MTP is specifically “0”, and no error message is particularly output.

In FIG. 6, first, the signal I1 input to the input / output state detection circuit 12 is "1",
The signal I which is in a logical state of "0", "X (undefined)" or "Z (high impedance state)" and which is also input to the input / output state detection circuit 12 from the outside.
O1 is the same "1" as the signal I1 at this time,
When the logical state is "0", "X", or "Z", the logical state of the signal IO1 and the logical state of the signal Y1 output from the input / output state detection circuit 12 are both "X".
Becomes

Further, only one of the logical states of the signal I1 or IO1 input to the input / output state detection circuit 12 is "Z", and the other is "1" or "0".
Is the definite value of the signal, the definite value is the signals IO1 and Y.
It is output as a logic state of 1.

When the logic states of the signals I1 and IO1 input to the input / output state detection circuit 12 are "Z", the logic states of the signals IO1 and Y1 output at this time are both "Z". Z ".

Further, in FIG. 6, when the logical states of the input signals I1 and IO1 are both "0", or both are "1", the value of the output message table pointer MTP is It becomes "1".

When the logical states of the input signals I1 and IO1 are both "Z", the value of the output message table pointer MTP is "2".

As described above, according to the logic state of the signals I1 and IO1 input to the input / output state detection circuit 12, the logic of the signals IO1 and Y1 output from the input / output state detection circuit 12 is determined. States can be set. As a result, the operation of the bidirectional buffer circuit 10 provided with the input / output state detection circuit 12 is performed, for example, by the conventional bidirectional buffer circuit 10 shown in FIG.
It can be equivalent to B. Further, it is possible to more accurately select and output an effective error message by verifying the logic circuit as to an error message as described later in more detail.

FIG. 7 is a diagram showing an output message table used in this embodiment.

FIG. 7 shows a table in which the contents of the error message output in this embodiment, which is referred to by using the value of the output message table pointer MTP described above with reference to FIG. 6, as an address, are stored. ing.

In FIG. 7, when the value of the output message table pointer MTP is "1", the signal I output from the tristate output buffer gate B1 in the bidirectional buffer circuit 10 shown in FIG.
1 and the signal IO1 input from the outside indicate a collision message, that is, "CONFLICT ER".
The message "ROR: ..." Is referred to and fetched. Further, when the value of the output message table pointer MTP is "2", the logic state of the signal I1 output from the tristate output buffer gate B1 is high impedance. In addition to the state, the logic state of the signal IO1 input from the outside of the bidirectional buffer circuit 10 is a high impedance state, so that the signals IO and Y output from the bidirectional buffer circuit 10 have a problem. There is an error message indicating that there is "DISAB
The error message "LE ERROR: ..." Is referenced and fetched.

In these error messages, the variable "$ inst" is displayed together with the message "Instance".
The message of the instance name (instance number (number attached to the logic gate of the logic circuit)) referred to by "ance" is obtained. Furthermore, it is referred to by the variable "$ io" together with the message of "pin". Pin number (or IO
Number) is obtained. Also, the message of the event occurrence time referred to by the variable "$ time" can be obtained together with the message of "at time".

FIG. 8 is a diagram showing an example of an error message printed out in this embodiment.

FIG. 8 shows a print example of the error message obtained in the operation example shown in the time chart of FIG. The print example has three lines.

Of these three lines of error messages, the first line is the time 0 in the time chart of FIG.
Then, the logic state of the input signal CIN changes to change the logic state of the signal I1, or the bidirectional input / output signal IO input from the outside changes to change the signal IO1. This is the error message obtained when the event occurred. This error message indicates that "CONFLICT ERROR" has occurred on pin IO of instance I3. This instance I3 is the bidirectional buffer circuit 10, and the "pin IO" of the error message is that of the bidirectional buffer circuit 10. As described above, this error message is an error that particularly indicates the occurrence of the collision between the signal I1 and the signal IO1 in the period from time 0 to time 10 in the time chart of FIG.

Subsequently, in the second row of FIG. 8, at time 10 of the time chart of FIG. 4, the logic state of the input signal CIN changes and the logic state of the signal I1 changes, so that an event occurs. This is an error message indicating the error that was obtained when you did. The third row also relates to "instant I3" and its "pin IO".
Further, this error message is generated by the signal I as described above, which occurs during the period from time 10 to time 20 in FIG.
1 shows the occurrence of a collision between the signal 1 and the signal IO1, in particular, the occurrence thereof.

Then, in the third line of FIG.
It is an error message showing an error obtained at the time of occurrence of an event generated by changing the logical state of the bidirectional input / output signal IO at the time 20. The error message also relates to the pin IO of the instance I3. Also, this error message is
Of the signal I1 occurring in the period from time 20 to time 30 of
And the logic state of the signal IO1 are both in a high impedance state.

As described above, according to this embodiment,
The logic circuit verification to which the first invention or the second invention is applied can be performed while using the bidirectional buffer circuit to which the third invention is applied. In particular, in this embodiment,
Since the error message as shown in FIG. 8 can be printed out, there is a problem in the operation of the verified logic circuit 14 or the signal input to the verified logic circuit 14. Especially, when there is a problem with the bidirectional buffer circuit 10, it is possible to print out the information about the problem as an error message together with the time of occurrence. Therefore, the function and operation of the verified logic circuit 14 and the verified logic circuit 1
It is possible to efficiently verify the abnormality of the signal input to the signal processing unit 4.

When verifying the functions and operations as described above, for example, the bidirectional buffer circuit 10 having the input / output state detection circuit 12 is used as described above. However, after such verification, when the logic circuit 14 to be verified is actually used, the bidirectional buffer circuit 10 does not include the I / O state detection circuit 12 shown in FIG. It can be replaced with the buffer circuit 10B. As a result, since the input / output state detection circuit 12 is not included, the degree of integration and the operation speed can be improved.

Further, such a bidirectional buffer circuit 1
The replacement of 0 with the bidirectional buffer circuit 10B, and further with the replacement of the bidirectional buffer circuit 10B with the bidirectional buffer circuit 10 performed prior to the verification of the function and the operation are automatically performed in a CAD device, for example. It is also possible to do so. By automating in this way, it is possible to further reduce the labor of the user.

In the present embodiment, as described above with reference to FIG. 6, even if the logic state of the definite value of the signal I1 and the logic state of the definite value of the signal IO1 collide with each other, If the conflicting logic states are not the same, the error message output is omitted. this is,
Even if the error message is omitted in this way, the logic states of the signals IO1 and Y1 output from the bidirectional buffer circuit 10 are "undefined (X)" in the collision of different logic states as described above. This is because such a defect can be caught by propagating such an indefinite logic state in the series of logic circuits. By outputting only the minimum necessary error messages in this way, only more important error messages can be shown to the user. Especially for problems that could not be detected in the past,
The user can easily recognize the presence or absence of such an error message.

[0090]

As described above, according to the present invention, it is possible to further reduce the time and effort of the user when verifying the function and operation of the logic circuit to be verified, and at the same time, to improve the accuracy of the verification. It is possible to obtain an excellent effect that

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a bidirectional buffer circuit which is a target of a logic circuit verification method of the first invention and the second invention of the present application and a bidirectional buffer circuit of the third invention.

FIG. 2 is a circuit diagram of a bidirectional buffer circuit showing the gist of the first invention to the third invention.

FIG. 3 is a circuit diagram of a logic circuit to be verified according to an embodiment to which the first invention to the third invention are applied.

FIG. 4 is a time chart showing an operation example of the verified logic circuit of the embodiment.

FIG. 5 is a flow chart showing a logic circuit verification method in the above embodiment.

FIG. 6 is a diagram showing the correspondence between the input and output logical states and the correspondence between the output message table pointers showing the operation of the input / output state detection circuit used in the embodiment.

FIG. 7 is a diagram showing an example of an output message table used in the embodiment.

FIG. 8 is a diagram showing an example of an error message printed out in the above embodiment.

FIG. 9 is a circuit diagram showing verification of a circuit having a conventional bidirectional buffer circuit.

[Explanation of symbols]

 10, 10B ... Bidirectional buffer circuit 12 ... Input / output state detection circuit 14 ... Verified logic circuit B1 ... Tristate output buffer gate B2, B3 ... Buffer gate IV1, IV2 ... Inverter gate

Claims (4)

[Claims] 1. A logic state of an input / output signal to the outside of the verified logic circuit is observed while simulating the verified logic circuit based on circuit information data indicating the configuration of the verified logic circuit. Also, in a logic circuit verification method for observing the logic state of an internal net signal and verifying the function and operation of the logic circuit to be verified based on these observation results, a tristate logic gate for output and a logic for input are provided. With respect to the logic circuit to be verified having a bidirectional buffer circuit composed of gates, the output of the output tri-state logic gate is U, the input of the input logic gate is V, and other than at the time of logic circuit verification. When the bidirectional input / output of the bidirectional buffer circuit is IO, the output U, the input V, and the bidirectional input / output are normally connected to the output U and the input V. In the IO,
The input I1 is connected to the output U, the output Y1 is connected to the input V, and the bidirectional input / output IO1 is connected to the bidirectional input / output IO. An input / output state verification circuit having an output IO1 is provided at least during the logic circuit verification, and the input / output state verification circuit inputs a logical state to the input I1 and a logical state to the bidirectional input / output IO1. The logic state output from the output Y1 and the logic state output from the bidirectional input / output IO1 while operating the logic circuit to be verified. Logic circuit verification characterized by observing a logic state of a signal of the bidirectional input / output IO1 and verifying a function and an operation of the verification target logic circuit. Law. 2. The first error information according to claim 1, wherein when the logical state of the input I1 and the logical state of the bidirectional input / output IO1 are the same definite value, the first error information used for the logic circuit verification is generated, , The logical state of these inputs I1 and bidirectional input / output IO1
A logic circuit verification method, wherein the second error information used for logic circuit verification is generated when all of the logic states are high impedance. 3. A logic state of an input / output signal to / from the outside of the verified logic circuit is observed while simulating the verified logic circuit based on circuit information data indicating the configuration of the verified logic circuit. Also, in a logic circuit verification method for observing the logic state of an internal net signal and verifying the function and operation of the logic circuit to be verified based on these observation results, a tristate logic gate for output and a logic for input are provided. With respect to the verified logic circuit having a bidirectional buffer circuit composed of gates, first, regarding the output tri-state logic gate,
Based on the input logic state, the buffer side logic state I1 to be output is obtained while considering the signal delay time, and the output of the output tri-state logic gate and the input of the input logic gate are A bidirectional input / output IO of the bidirectional buffer circuit, which is connected together, and a pair-to-buffer logic state IO input from the outside of the bidirectional buffer circuit.
1 is obtained, and error information utilized for logic circuit verification is generated based on the buffer side logic state I1 and the paired buffer logic state IO1. 4. A bidirectional buffer circuit comprising an output tristate logic gate and an input logic gate, wherein the output of the output tristate logic gate is U.
When the input of the input logic gate is V and the bidirectional input / output of the bidirectional buffer circuit is IO, the output U, the input V, and the bidirectional input / output IO are
The input I1 is connected to the output U, the output Y1 is connected to the input V, and the bidirectional input / output IO1 is connected to the bidirectional input / output IO. An input / output state detection circuit having an output IO1 is provided, and the input / output state detection circuit is based on the logical state input to the input I1 and the logical state input to the bidirectional input / output IO1. And a logic state output from the output Y1 and a logic state output from the bidirectional input / output IO1.