JP2001060216A - Logic equivalence verifying device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decide a discrepancy of logic equivalance by detecting a racing phenomenon. SOLUTION: Gate level data after logic composition are inputted 103 and when a gate level version cone and a racing checkpoint are present, a subcone (called a racing check cone) having the racing checkpoint as the end point of the cone is generated as additional information on the cone. Then stored information is used to compare cones before and after the logic composition and make cones correspond to each other and the equivalence of logic is examined for every cone which are made to correspond by comparing Boolean expressions as the additional information and racing check cone information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for verifying logic equivalence, and relates to a technique for converting data designed and described in HDL function into gate level logic by logic synthesis or manual work.
This is an effective technique to verify the equivalence before and after the logical data conversion.

[0002]

2. Description of the Related Art Conventionally, in a functional design method using HDL, when a function is designed in HDL and a gate level logic is generated by a logic synthesis tool or manual work, it is necessary to guarantee the equivalence of the logic. Conventionally, equivalence was determined by comparing the results of functional simulations before and after logic generation.

However, since recent LSIs have become large-scale and high-performance, it is difficult to create a test pattern for operating the entire inside of the LSI. Therefore, a technique for verifying logical equivalence based on Boolean comparison, which is disclosed in Japanese Unexamined Patent Application Publication No. 8-22485, has been used.

[0004] This system employs an FF (flip-flop) -F
A circuit that cuts out a combination circuit surrounded by F and FF-edges (hereinafter referred to as a cone), associates the circuits before and after the gate level logic is generated, and determines whether or not the logic is equivalent by a Boolean comparison method. Met.

[0005]

However, the conventional Boolean comparison method can detect a generation failure related to a functional operation at the time of generating a gate level logic, but requires a circuit in consideration of a gate delay. If generated,
The verification result of equivalence cannot be guaranteed. This is because the pre-logic synthesis circuit 200 shown in FIG.
In the case of generating as shown in FIG. 01, when a circuit determined to be equivalent by the Boolean comparison method performs a timing simulation, a racing 203 occurs at the falling edges of the signals * 1 and * 2 as shown in the time chart 202. Output Q
The logical value of the _P signal becomes the uncertain value 'X' 204, and the functions do not match.

Therefore, even when a verification method using a Boolean comparison method is used, it is necessary to perform a timing simulation at the gate level, and it is necessary to create test data for testing all operations. The problem from the method has recurred.

An object of the present invention is to detect and point out a racing phenomenon, which cannot be detected without timing simulation, based on a Boolean comparison method.
It is to improve the coincidence / mismatch verification accuracy of logical equivalence.

[0008]

The logic equivalence checking apparatus of the present invention detects a phenomenon in which data and a clock are racing in a conventional function for verifying the coincidence of the cone extraction logic between FFs by a Boolean comparison method. By adding such a function, it is possible to guarantee the equivalence of logic without gate level simulation.

For this reason, in addition to the conventional functional operation expression (Boolean expression), the combination information of the pin to be subjected to the racing check can be input to the gate-level library. The default value of this combination is a data pin and a clock pin of the FF, and enables customization by the user. or,
The SR latch element is also handled as a cone cutting target point.

In the racing check, at the time of cone cutting in the gate level circuit, the racing check combination information defined in the FF library is read, and if the racing check information is defined, the fan-in trace is performed from this check point. Cone (hereinafter referred to as racing check cone)
Is stored in the storage means.

[0011] When a plurality of racing check cones exist in the same cone at the time of logical equivalence verification and all pieces of racing check cone configuration set information match at the time of logical equivalence verification, all of the event propagation sources to the racing check point are transmitted. Means the same. Therefore, a racing phenomenon occurs in which all check points change simultaneously.
When this phenomenon occurs on the data pin and the clock pin of the FF, the logic operation at the gate level cannot be guaranteed. Therefore, even if the circuit is determined to be equal by the Boolean comparison method, it is determined again that the logic does not match, and the mismatch information can be output.

This makes it possible to detect a racing phenomenon, which was previously undetectable only by timing simulation, without preparing test data.

[0013]

FIG. 1 is a flowchart showing an example of the operation of a logical equivalence checking method according to an embodiment of the present invention. FIG. 3 is a conceptual diagram showing an example of a method of extracting a cone and a Boolean expression of HDL description design data. FIG. 4 is a flowchart for extracting a cone, a racing check cone, and a Boolean expression in the case of gate level data. FIG. 5 is a conceptual diagram showing an example of a method of extracting a cone and a Boolean expression when there is no racing checkpoint in gate level data. FIG. 6 is a conceptual diagram showing an example of a method of extracting a cone and a Boolean expression and a racing check cone when a racing check point is included in the gate level data. FIG. 7 is a conceptual diagram illustrating an example of a configuration of a logical equivalence checking device according to an embodiment of the present invention.

First, referring to FIG. 7, an example of the configuration of the logical equivalence verifying apparatus according to the present embodiment will be described. The system bus 700 includes a microprocessor 702 for controlling the entire operation and basic software and a user program for controlling the microprocessor 702 (in the case of the present embodiment, a logical equivalence check for performing the processing shown in the flowchart of FIG. 1). Program) and various control information used in the process of logic equivalence verification as described below.
5. HDD in which information such as a logical equivalence verification program and design data to be subjected to logical equivalence verification described later is stored.
An external storage device 706 such as a device, and a display 70 for visualizing and providing information such as a logical diagram and processing result information to an operator
1, a keyboard 703 used by the operator for inputting commands and data, a pointing device 70 such as a mouse, etc.
4, etc. are connected.

The logical equivalence verifying program is loaded into the main memory 705 from the external storage device 706 at an arbitrary timing and activated, thereby executing the logical equivalence verifying program of the present embodiment illustrated in FIGS. Implement sex verification method. Also,
Information on the execution process of the logical equivalence verification program is output to the display 701 as needed.

FIG. 1 is an overall flow diagram of the logical equivalence verification according to the present embodiment, and all the processes are automatically performed by a logical equivalence assurance program. Design data (HDL)
The input processing 100 inputs the design data of the HDL description from the external storage device 706. Next, in the HDL description version cone / Boolean expression generation processing 101, the HDL data read from the external storage device 706 is generated as cone information 301 and a cone unit Boolean expression 302 and stored in the main memory 705.
Next, the gate level data for verifying the logic equivalence with the HDL description design data already read is stored in the external storage device 706.
Read more. Next, in the gate level version cone / racing check cone / Boolean expression generation processing 104, cone information 502, cone unit Boolean expression 503, and racing check cone information 603 are generated and stored in the main memory 705. Then, according to the generated cone information in the main memory, the HD
The cones of the L-description version and the gate-level version are associated with each other, and by comparing the corresponding cone unit Boolean expressions and comparing the racing check information, it is determined whether the HDL description data is logically equivalent to the gate level. The determination is made, and the determination result is output to the display 701 and the external storage device 706.

Hereinafter, the generation of the cone Boolean expression of the HDL description design data will be described in detail with reference to FIG. 3, and the generation of the cone racing check cone Boolean expression of the gate level data will be described in detail with reference to FIGS.

The HDL description design data 30 shown in FIG.
0 is fan-in traced from the edge signal of the FF or the top layer of the logical equivalence assurance target by the syntax analysis.
Trace is performed until the edge signal reaches the edge signal of F or the highest hierarchy of the logical equivalence guarantee target. In the case of the HDL of the embodiment 300, tracing starts from the edge signal C310 and reaches the edge signals A311 and B312. Therefore, a single cone having C = {A, B} as an aggregate can be generated as a generated cone. Also, for the generated cone C, a Boolean expression 302 C representing a functional operation
= A andB, the generated cone information 313 and the cone unit Boolean information 302 are paired, and
5 in the HDL description version 710.

Next, FIG. 4 is a partial flow of the cone generation, the racing check cone generation, and the Boolean expression generation processing unit of the gate level data generated by logic synthesis or manual operation, which are compared with the HDL description design data. is there. As an implementation example, FIG.
In the present example, a gate element AND2 510 is present. The operation contents of AND2 are as follows.
The gate library configuration 501 is described in the gate library of the external storage device 706, and has I / O information, functional operation information (such as a Boolean expression), and racing checkpoint information. The racing checkpoint information will be described later in detail.

Gate library development processing 401 shown in FIG.
Reads the gate level design data 500 in FIG. 5 and searches for the position of the gate level element. In this embodiment, AD
It recognizes that N2510 is a gate level element.
In each gate level element, a gate library 50
1 is read and the gate library configuration 501 of the corresponding element is read.
The processing of temporarily converting the gate level data into the HDL description design data is performed by incorporating the I / O information and the Boolean expression information. The data converted to HDL format is HDL
Using the cone / Boolean expression generation processing unit of the description design data, a cone generation 502 and a cone set 511C = ｛A,
B｝ and cone unit Boolean expression extraction 503C = AandB are generated and stored as gate level version information 711 in the external storage device 705 in FIG.

The stored data is stored in the Boolean comparison process 1 shown in FIG.
In part 06, correspondence is made based on cone set information. In this embodiment, C = {A, B} is associated,
The information of the cone unit Boolean expression held by each cone set, 302 in FIG. 3 and 503 in FIG. 5 match, so that it can be determined that the logic operations before and after the logic synthesis match.

On the other hand, for a circuit having a D Latch Type FF 610 as shown in an example of the gate level data in FIG. 6, CK = D, etc. 61 at the racing check point in the gate library information 601.
There is a portion having three pieces of information. This is CK pin 6
It is checked whether 11 and the D pin 612 change at the same time, and if there is a simultaneous change, it means that the logical equivalence does not match. In the determination process 403 of the presence or absence of the racing check point in FIG. 4, it is determined that the racing check point is present, and the initial cone 613 in FIG. 6 is generated using the racing check point as an input terminal of the cone.

Next, cone generation processing 406 is performed in which the racing check point in FIG. 4 is regarded as the end of the cone. The cone generated in this way is called a racing check cone, and two racing check cones 614 and 615 are extracted. In addition, as the racing check cone information, the cone components are respectively represented by CK =
{S, R} and D = {S, R} 603 are generated as set information.

The generated information is stored in a racing check cone information storage process 406 shown in FIG.
As the additional information of the {S, R} set, the main storage device 7 in FIG.
CK = ｛S on the racing check cone 712 of 05
R｝, D = {S, R}. If the racing check cone information is present in the racing presence / absence verification processing 106 in FIG. 1 and the set elements of all the racing check cones match, it is determined that racing has occurred, and the logical mismatch information Is output to the display and the logical equivalence verification processing result information 713 of the external storage device 706. In this example, the set elements of the racing check cones CK and D are both {S, R}, and the set elements of all the racing check cones match, so it can be determined that they are logically unequal.

As a result, the HDL description data 200 shown in FIG.
It is possible to point out that the circuits are logically inconsistent without performing the simulation at 1.

Although the invention made by the present inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is.

[0027]

According to the logical equivalence verifying device of the present invention,
When verifying the equivalence of functions with gate-level data obtained by converting data created by HDL description design by logic synthesis or manual work, a racing phenomenon in which the data pin and clock pin of the FF element change simultaneously is considered. It is possible to detect a logic mismatch when a circuit having the same is generated.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an example of the operation of a logical equivalence checking method according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an example of a logical conversion that cannot be detected by a logical equivalence verifying method using only a conventional Boolean comparison method.

FIG. 3 is a conceptual diagram illustrating an example of cone information generation of HDL description logic in a logic equivalence guarantee method according to an embodiment of the present invention.

FIG. 4 is a flowchart illustrating an example of generating cone information of gate level data in the logic equivalence guarantee method according to an embodiment of the present invention.

FIG. 5 is a conceptual diagram showing an example of cone information generation when there is no gate-level data racing checkpoint in the logical equivalence guarantee method according to one embodiment of the present invention.

FIG. 6 is a conceptual diagram showing an example of cone information generation in the case of having a gate level data racing checkpoint in the logical equivalence guarantee method according to one embodiment of the present invention.

FIG. 7 is a conceptual diagram illustrating an example of a configuration of a logical equivalence checking device according to an embodiment of the present invention.

[Explanation of symbols]

100 to 107: Functional processing part in the logic equivalence assurance program flowchart, 200: Circuit before logic synthesis, 201: Circuit after logic synthesis, 202: Time chart at timing simulation, 203 ...
Racing phenomenon, 204 ... logical value uncertain, 300
..HDL description design data, 301: cone generation,
302: cone unit Boolean expression, 310 to 312 ...
-Edge signal, 313 ... generated cone information, 401-
407: function processing part in the flowchart of the gate level data processing unit; 500: gate level data;
501: gate library information, 502: generated cone, 503: cone unit Boolean expression, 510 ...
.Gate-level elements, 511... Generated cone information, 6
00: gate level data, 601: gate library information, 602: generated cone, 603 ...
Racing check cone information, 613 ... initial cone, 614-615 ... racing check cone,
700 system bus, 701 display, 702 microprocessor, 703 keyboard, 704 pointing device, 70
5 Main memory, 706 External storage device, 710
712... Corn Boolean expression information.

Claims (4)

[Claims] 1. An HDL (Hardware Decr.)
This is a method of verifying the matching of the logic operation before and after logic synthesis when the function level is designed by a logic synthesis tool or manually by designing a function, and a gate library for detecting an operation mismatch due to a racing phenomenon. The sub-cone (called a racing check cone in the text) is generated with the racing check point at the end of the cone, the sub-cone configuration information is stored as the sub-information in the cone information, and logic synthesis is performed. A logical equivalence verifying device comprising means for judging the presence or absence of a racing phenomenon based on configuration information of a sub-cone and verifying logical equivalence at the time of logical equivalence verification after cone association with preceding and following data. 2. The logical equivalence verifying apparatus according to claim 1, further comprising means for detecting a logical equivalence mismatch due to a racing phenomenon without performing a timing simulation. 3. The logical equivalence verifying apparatus according to claim 1, further comprising: means for cutting out a sub-cone from a racing check point at the time of cutting out the cone and storing configuration information of the sub-cone in pairs with the cone. 4. A means for performing a racing check for improving the accuracy of detecting a mismatch in logic equivalence verification when the HDL function is designed and converted into gate level data by some means. 2. The logical equivalence verifying device according to 1.