JPH06266792A - Fault simulation processing method - Google Patents

Abstract

PURPOSE:To reduce the processing amount for a fault simulation processing by stopping to perform the subsequent simulation processing when the propagation destination of the influence of a fault reaches the element within an observation impossible area. CONSTITUTION:Element Nos.205 and 206 are NOT gates, Nos.217 to 219 are OR gates and others are AND gates. Nos.001 to 049 show temporary fault points which are possible to occur within this logical circuit or the temporary fault points to be processed in a fault simulation. When a fault simulation is performed for the fault on an observation possible route registered as a fault simulation object and the propagation destination of influence of the fault reaches the element within a observation impossible area, the subsequent simulation processing is not performed. Thus, even when all the combination which can be logically set are not always used, the range of the patterns where the observation impossible area can be extracted is expanded and the processing amount for the fault simulation processing can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure simulation processing method for a logic circuit, and more particularly to a method for reducing the processing amount during failure simulation.

[0002]

2. Description of the Related Art In recent years, with the increase in the scale of logic circuits, it is expected that the number of hypothetical faults and the number of input test patterns will reach enormous numbers, and fault simulation processing for all possible faults in the circuit will be performed. It is considered that the time required will also increase significantly.

Therefore, in order to reduce even a small amount of processing at the time of failure simulation, in the prior art, theoretical undetected failures that cannot be detected by any test pattern and logical expressions of a plurality of failures are the same. If there is an equivalent fault, the former has been deleted, and the latter has carried out a method of performing simulation processing with only one of them as the representative fault.

These can be recognized by utilizing only the connection relation of the logic circuit before the failure simulation processing.

However, there has been a problem that the amount of reduction with respect to increasing the scale of the logic circuit is insufficient.

Therefore, in order to further reduce the processing amount, as disclosed in Japanese Patent Laid-Open No. 04-245338,
In the test pattern applied to the external input terminal, when there is at least one external input terminal whose logic value is fixed to either "0" or "1", the external input terminal has "0" or "1". With the fixed value of "" applied and the non-fixed value "X" applied to the other external input terminals, the logical operation is performed prior to the failure simulation, and the logical values on all the signal lines are calculated and used. The number of faults to be processed in the failure simulation is determined by distinguishing between observable routes and unobservable routes, registering the observable routes as fault simulation processing targets, and not registering the unobservable routes as processing targets. Have been proposed.

[0007]

Some logic circuits include, for example, an address decoder which receives an address signal of a plurality of bits and decodes the address signal to selectively operate a specific element.

In such a case, the address signal of each bit can take a value of "0" or "1", but all the combinations that can be logically set are not always used for the entire bit. Absent. That is, when considering a 2-bit address signal, there are four kinds of combinations that can be logically set, "00", "10", "01", and "11". Of these, "00", Only "10" and "01" may be used.

However, in the above-mentioned prior art, when there is at least one external input terminal fixed to either "0" or "1", the external input terminal is fixed to "0" or "1". The value is applied and the non-fixed value "X" is applied to the other external input terminals to reduce the number of faults to be processed. Therefore, none of the bits have a fixed value of "0" or "1". The above example of the address signal cannot be applied, and there is a problem that the processing amount cannot be reduced.

The object of the present invention is not only when a certain external input terminal has a fixed value of "0" or "1", but also when all combinations that can be logically set are not always used. An object of the present invention is to provide a failure simulation processing method capable of reducing the processing amount related to.

[0011]

In order to solve the above-mentioned problems, the present invention provides a method in which the type of an input test pattern is one or more less than the number of combinations of signal values that can be logically set. Input test pattern is logical 0 or logical 1
Is divided into a first group having a fixed value and a second group having a fixed value by a combination of logic 0 and logic 1, and a fixed value is applied to the corresponding external input terminal in each divided group. , Non-fixed values are applied to the other external input terminals, the logical values on all the signal lines in the relevant logic circuit are obtained, and these logical values are followed in order from the external output terminal to the element on the input side. A failure included in the common unobservable area of each group is calculated by calculating whether or not the signal change of the input terminal can be observed at the output terminal, recognizing the area that cannot be traced as an observable path as the unobservable area. Is not registered as a processing target when performing a failure simulation on the input test pattern, and only the failure on the observable path is subjected to the failure simulation on the input test pattern. When performing a fault simulation for a fault on an observable path registered as a target for processing at the time and further registered as a target for the fault simulation, the propagation destination of the influence of the fault is an element in the unobservable region. When it arrives, the subsequent simulation processing is not executed.

[0012]

According to the above means, the failure simulation is carried out in the following order.

(1) Find out whether there is a number of external input terminals whose type of input test pattern is one or more less than the number of combinations of signal values that can be logically set, and if there is a corresponding external input terminal, The input test pattern applied to the input terminal is divided into a first group having a fixed value of logic 0 or logic 1 and a second group having a fixed value of a combination of logic 0 and logic 1.

(2) In each divided group, a fixed value is applied to the corresponding external input terminal, a non-fixed value is applied to the other external input terminals, and logical values on all signal lines in the logic circuit are applied. Ask.

(3) According to the obtained logical value, the external output terminal is sequentially traced to the input side element, and it is calculated whether or not the signal change of the input terminal can be observed at the output terminal of each element,
A region that cannot be traced as an observable route is recognized as an unobservable region.

(4) The fault included in the common unobservable region of each group is not registered as the processing target when the fault simulation is performed on the input test pattern, and only the fault on the observable path is input-tested. It is registered as a processing target when the failure simulation is performed on the pattern.

(5) The fault simulation is carried out for the fault on the observable route registered as the target of the fault simulation. At that time, if the propagation destination of the influence of the failure reaches the element in the unobservable region, the subsequent simulation processing is not executed.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a processing flow chart showing an embodiment of the failure simulation processing method of the present invention.

First, as a file relating to input information,
The input test pattern information file 1100 and the connection relation information file 1110 of the logic circuit to be inspected are used.

Input test pattern information file 1100
Is an input test pattern indicating a time series of signal values given to each input terminal, test pattern group information indicating a test pattern belonging to each group necessary for group division of the test pattern, and pattern division information (for each pattern pin). Group division information), fixed value information to be assigned to a number of external input terminals (hereinafter, referred to as specific input terminals) whose number of input test pattern types is one or more less than the number of combinations of signal values that can be logically set. Is stored.

FIG. 2 is a circuit diagram showing an example of a logic circuit to be inspected, and FIG. 3 is a diagram showing an example of an input test pattern 30 for this logic circuit.

In the logic circuit of FIG. 2, 101 to 106
Is an external input terminal, and 107 is an output terminal. Also, 10
1 to 219 are element numbers assigned to the respective elements in the circuit, and element numbers 205 and 206 are NOT gates, 217,
218 and 219 are OR gates, and the others are AND gates. Further, reference numerals 001 to 049 indicate possible failure points that may occur in this logic circuit, that is, assumed failure points to be processed in the failure simulation.

The input test pattern 30 of FIG. 3 is composed of a combination of logic 0 and logic 1 signals which are sequentially applied to the external input terminals 101 to 106 in time series. Here, the signals of patterns # 1 to # 25 are arranged. It is shown. In FIG. 3, focusing on the input terminals 103 and 104, when a logical 0 is input to both of these terminals 103 and 104, when a logical 1 is input to both of them, and when one is a logical 0 Has three patterns in which the logic 1 is input to the other, and both are patterns in which there is no combination of the logic 1.

According to the present invention, the input terminals 103 and 104 to which such a pattern is input are found, and the input test pattern 30 of FIG. 3A is changed to the test patterns 31, 32 and 33 as shown in FIG. 3B. Split into. That is, logical 0
Alternatively, it is divided into a first group of test patterns 32 and 33 having a fixed value of logic 1 and a second group of test patterns 31 having a fixed value of a combination of logic 0 and logic 1.

Then, fixed value patterns 34, 35, 3 as shown in FIG. 3C in which a non-fixed value X is assigned to the external input terminals other than the fixed value in each of the divided groups.
6 is generated and applied to the logic circuit to be inspected.

In this case, as shown in FIG. 4A, the test pattern of the first group having a fixed value of logic 0,
A test pattern 40 in which the test pattern of the second group having a fixed value due to the combination of the logic 0 and the logic 1 is already clearly divided is shown in FIG. Such a fixed value pattern 41 is generated.

First, the case where the pattern group is not divided as shown in FIG. 3A will be described.

When the pattern group is not divided, after inputting the external input terminal numbers 103 and 104 to be noticed in the dividing process to the pattern dividing process 1020, the pattern is stored in the input test pattern information file 1100.
The test pattern 30 as shown in FIG.
As shown in (b), test patterns 31, 32, and 33 divided into groups are created.

Next, in the fixed value pattern generation processing 1030, fixed value patterns 34, 35 and 36 as shown in FIG. 3C are generated for each of the divided pattern groups.

Next, the input test pattern information file 11
00 to read the fixed values belonging to each pattern group, further read the connection relation information from the connection relation information file 1110, execute the fixed value simulation 1040, and perform the unobservable region tracking process 1050 to determine the unobservable region in the logic circuit. It recognizes and stores the unobservable area in the observation information storage table 1120.

The fixed value simulation 1040 and the unobservable region tracking process 1050 are the fixed value patterns 34, 3 of FIG.
It carries out about each of 5,36.

The unobservable region tracking process 1050 will be described in detail later.

Next, based on the information of the unobservable area for each fixed value pattern detected by the unobservable area tracking processing 1050, the processing target having the unobservable flags respectively corresponding to the assumed failure points 001 to 049 in FIG. Failure table 11
Each unobservable flag in 30 is set. Then, the common unobservable region when the fixed value pattern of each group is input is obtained.

Therefore, the processing target failure table 1130
Is the total of possible failures in the logic circuit, with the failures in the unobservable region removed.

Therefore, this processing target failure table 113
0 and the connection relation information file 1110 of the logic circuit,
The failure simulation 1080 is performed using the input test pattern information file 1100 as an input until there are no unexecuted test patterns.

As a result, the failure detection rate 1140, the expected output value 1150, and the failure dictionary 1160 are obtained.

Next, a case where the pattern group is already divided as shown in FIG. 4A will be described.

When the pattern group is divided, a fixed value pattern as shown in FIG. 4B is directly generated,
A fixed value simulation 1040 is executed based on this fixed value pattern and the connection relation information file 1110. The process after the fixed value simulation is the same as the process when the pattern group is not divided, and thus the description thereof is omitted.

Next, an example of the pattern division processing 1020 will be described.

With respect to the input terminals (input terminals 103 and 104 in the example of FIG. 2) for which a fixed value is manually specified, the input patterns are sequentially examined, and the combination of the logical values of the applied patterns is one type. As long as it is determined that the patterns belong to the same pattern group.

If a pattern group consisting of a sufficient number of patterns cannot be formed by collecting one type of pattern, it is determined that the patterns belong to the same pattern group as long as they are represented by two types of patterns. I will do it. This operation is repeated up to the number of possible combinations of logical values minus one.

Here, the test pattern 30 shown in FIG.
As an example, the number of possible combinations of logical values of the two input terminals 103 and 104 for manually inputting fixed values is four. Therefore, it is necessary to divide into groups that can be represented by patterns that are one less than all combinations, that is, three or less patterns. First, 1
Looking at whether it is possible to divide into groups by type,
In the input terminals 103 and 104, pattern numbers 11 to 11
It takes a constant value "0" up to 15, and pattern numbers 16-25
Up to the above, it is possible to take a constant value "0", and these are each made into a group.

Next, the remaining pattern numbers 1 to 10 are mutually contradictory combinations, and group division represented by two types is possible. Let this be one group.

Therefore, FIG. 3 (a) is divided into three groups as shown in FIG. 3 (b).

Here, the example of FIG. 3 (a) is a case where the logic values applied to the designated terminal are applied with only a smaller number of combinations than all possible pattern combinations, and the designated terminal is applied. When the same number of combinations of all possible patterns having the logical value applied to the same are applied, the pattern group cannot be obtained. In such a case, if the simulation target circuit is a combinational circuit, the input order of the patterns is rearranged and the patterns are divided into pattern groups that can extract the unobservable region most efficiently. The most efficient pattern group is a group in which the number of pattern types is as small as possible and the number of divided pattern groups is small.

Since the fixed value simulation is carried out for the number of pattern groups, the smaller the number of pattern groups, the smaller the number of fixed value simulations, and the shorter the processing time.

Next, the unobservable region tracking process 1050 will be described. This process uses the calculation result of the fixed value simulation, sets the unobservable flag in the circuit by tracing the unobservable region, and detects the fault in the unobservable region with respect to the fixed value pattern in this pattern group. Not subject to failure simulation processing.

Here, the unobservable means that the failure propagation path is not continuous to the external output terminal, that is, the signal change of the failure disappears before reaching the external output terminal, and the unobservable failure occurs. Is a failure that cannot be detected. The unobservable flag indicates whether or not it is included in the unobservable region, and is unobservable region information of the logic circuit added for each failure in the logic circuit. When the unobservable flag is on, That is, when it is "1", it is included in the unobservable region, and when it is off, that is, "1", it is not included in the unobservable region.

More specifically, before assigning a fixed value to each input terminal and performing a fixed value simulation, all the unobservable flags in the observation information storage table 1120 are initialized to ON as shown in FIG. After that, the following processing is repeated for all external output terminals.

When the element number 215 in FIG. 6 is taken as an example, a logical operation is performed to obtain a logical value on the signal line, and by using this, a signal change at the input terminal can be observed sequentially from the output terminal to the input terminal. Calculate whether or not. In this case,
The logical value "0" is input to the 033th input terminal of
Because "X" is input to the 4th input terminal,
The logical value "0" is transmitted to the output side, and the "0" and "1" changes of the 034th "X" input terminal are not transmitted to the output terminal.

Therefore, when a change of "0" or "1" is transmitted to the input terminal 033 of "0", it is changed to "0" or "X" and transmitted to the output terminal. Therefore, the terminal 033 having the input logical value “0” is observable, and the unobservable flag is turned off.

On the other hand, the input terminal 0 of "X" which is not activated
Since the 34th is an unobservable region, the unobservable flag is left on. This process is executed for all input pins that are determined to be observable, from the external output terminal to the external input terminal. As a result, the unobservable region in each fixed value pattern can be obtained.

Next, the process of extracting a common unobservable region will be described using the circuit example of FIG.

The specified fixed value input target terminal is the input terminal 1.
In the case of 03 and 104, reference is made to the input test pattern 30 and it is investigated whether the number is smaller than the total number of logically conceivable patterns.

In the case of the input test pattern 40 of FIG.
"0" and "1" are applied to the input terminals 103 and 104, respectively, from the 1st to the 15th of the input pattern numbers, and from the 16th to the 25th, both terminals are "0". Is being applied.

Conventionally, the unobservable region can be defined only for the 16th to 25th pattern groups, but in the present invention, the 1st pattern to the 15th pattern group can be further defined as the 1st pattern. The non-observable region can be defined even for the group including all patterns from 1 to 25.

In this example, the case where all the 1st to 25th patterns are grouped will be described.

The fixed value pattern groups belonging to this pattern group are input terminals 103, 10 as shown in FIG. 4B.
Input “0”, “1” or “1”, “0” or “0”, “0” to 4 respectively, and input “0” to other terminals,
It consists of three patterns in which a non-fixed value "X" that can take both "1" is input.

At that time, the observation information storage table 1120
5, the hypothetical failure points obtained from the connection relation information file 1110 are set, and all the unobservable flags of all the hypothetical failure points are turned on, that is, initialized to "1", and ), A fixed value simulation is performed for each of the three fixed value patterns, and a logical operation is performed on each element at the fanout destination.

For example, when performing a logical operation, a fixed value "0",
A ternary truth table of "1" and non-fixed value "X" is used. FIG. 7A shows an AND gate, FIG. 7B shows an OR gate, and FIG.
Table 1 shows the truth table of NOT gate.

The signal values on the logic circuit when the first fixed value pattern in which the input terminal 103 is "0", the 104th is "1" and the other input terminals are "X" are shown in FIG.
Shown in.

The areas that cannot be traced as observable areas in this first fixed value pattern are 301, 302, 304.
This is the area indicated by. The unobservable assumed failure points included in this are 005, 011, 029, 006, 012, 03.
They are 1, 010, 016 and 036.

Therefore, the unobservable flags of these unobservable assumed failure points remain "1". However, since other hypothetical failure points are observable, "0" is set to the unobservable flag.

Next, the signal values on the logic circuit when the second fixed value pattern in which the input terminal 103 is "1", 104 is "0" and the other input terminals are "X" are input are shown in FIG.
Shown in.

The regions which cannot be traced as the observable regions in this second pattern are the regions 301, 303 and 304. The unobservable hypothetical failure points included in this are 00
5, 011, 029, 009, 015, 034, 01
0, 016 and 036.

In this unobservable assumed failure point 009,
For 015 and 034, since it is determined that the first fixed value pattern is unobservable in the unobservable region tracking, the unobservable flag of the observation information storage table 1120 remains “0”. On the contrary, 006,0 which was unobservable in the unobservable region tracking for the first fixed value pattern
Since 12, 031 can be observed in the second unobservable region tracking, “0” is set in the unobservable flag.

Therefore, when the processing for the second fixed value pattern is completed, the unobservable hypothetical failure point is 005,
011, 029, 010, 016 and 036.

Finally, the input terminal 103 is "0", 104
6 shows the signal value on the logic circuit when the third fixed value pattern in which the other terminal is “0” and the other terminals are “X” is input.
Shown in.

The areas which cannot be traced as the observable areas in the third fixed value pattern are the areas 301, 302 and 303. The unobservable assumed failure points included in this are 005, 011, 029, 006, 012, 03.
1, 009, 015, 034.

In this unobservable hypothetical failure point 009,
015 and 034 are observable by the unobservable region tracking for the first fixed value pattern, and 006 and 01
With respect to 2,031 as well, the unobservable flag remains "0" because it can be observed by the unobservable region tracking for the second fixed value pattern. In addition, 0 was not observable by tracing the unobservable region for the first and second fixed value patterns.
Nos. 10, 016, and 036 are observable in the unobservable region tracking for the third fixed value pattern, and therefore "0" is set in the unobservable flag.

Therefore, finally unobservable hypothetical failure points are 005, 011 and 029. Therefore, 005,
The unobservable flags of 011 and 029 remain "1", and the unobservable flag in the observation information storage table 1120 at the time when the processing for the three fixed value patterns is completed is as shown in FIG. .

Subsequently, the processing target failure table 1130 to be input to the failure simulation is created based on the unobservable information obtained by such a fixed value simulation.

FIG. 11 shows the processing target failure table 1130. This processing target failure table 1130 stores items of a hypothetical failure point and an unobservable flag, and all the flags of the hypothetical failure point are turned on, that is, initialized to "1".

Therefore, based on the unobservable information of the observation information storage table 1120 obtained by the fixed value simulation, the observable hypothetical fault point in the processing target fault table 1130 has the flag turned off as shown in FIG. set.

Therefore, as a result of referring to all the hypothetical fault points, only the unobservable hypothetical fault points have their flags set to be on. A failure simulation is executed based on this information.

Originally, it is necessary to carry out the failure simulation for the failures at all the hypothetical failure points indicated by 001 to 049. However, this unobservable region recognition processing creates a processing target failure table 1130 in which only observable assumed failure points are registered, and unobservable information for the processing target failure table 1130 is obtained, so the processing can be reduced.

In the case of this example, 005, 011 and 029
It is not necessary to perform simulation for the three assumed failure points of

Next, consider the case where the input test pattern of FIG. 3 is input.

In this case, since four types of patterns are input, inputting a fixed value as it is has no effect.
Therefore, it is divided into groups in which the same pattern is input.

First, the test pattern 3 shown in FIG.
Referring to 0, the 1st to 10th patterns assign "0" and "1" contradictory to each other, and the 11th to 15th patterns assign "0" to both input terminals. In the 16th to 25th patterns, "1" is assigned to both input terminals.

Therefore, the input pattern group is shown in FIG.
As shown in the test patterns 31, 32, and 33 of (b), it is divided into three types of pattern groups, the assumed failure points are registered in the observation information storage table 1120 for each pattern group, and one type of fixed value simulation is performed. The unobservable flag is initialized to ON each time is executed.

Then, the fixed value pattern 3 in FIG.
A fixed value simulation is executed using 4, 35, and 36 as inputs, and if observable, the unobservable flag is turned off, and the unobservable region for each pattern group is obtained. Then, each time the fixed value simulation of one type of pattern group is completed, the failure simulation is executed and the propagation range of the failure is reduced based on the information obtained by the previous fixed value simulation. This can reduce processing.

[0084]

As described above, according to the present invention, an input test including a combination of signal values created to detect a failure that may occur in a logic circuit to be inspected in the external input terminal group of the logic circuit to be inspected. In the fault simulation processing method of applying a pattern and simulating a fault in the circuit based on the change in the signal value in the logic circuit reaching the external output terminal, the signal value in which the type of the input test pattern can be logically set If the number is one or more less than the number of combinations, the input test pattern is a first group having a fixed value of logic 0 or logic 1 and a first group having a combination of logic 0 and logic 1 has a fixed value. In each group, the fixed value is applied to the corresponding external input terminal and the non-fixed value is applied to the other external input terminals. Obtains the logical values of all the signal lines,
These logical values are used to sequentially trace from the external output terminal to the element on the input side, calculate whether or not the signal change of the input terminal can be observed at the output terminal of each element, and determine the area that cannot be traced as an observable path. After recognizing as an unobservable region, the faults included in the common unobservable region of each group are not registered as the processing target when performing the fault simulation on the input test pattern, and only the faults on the observable route are registered. The effect of the fault when the fault simulation is performed on the observable path registered as the processing target when the fault simulation is performed on the input test pattern, and is further registered as the target of the fault simulation. When the propagation destination of reaches the element in the unobservable area, the subsequent simulation processing is not executed. It is obtained by the.

Therefore, the unobservable region is extracted not only when a certain external input terminal has a fixed value of "0" or "1" but also when not all logically settable combinations are always used. The range of possible patterns is expanded, and the processing amount related to the failure simulation processing can be reduced.

[Brief description of drawings]

FIG. 1 is a processing flow showing an embodiment of a failure simulation processing method of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a logic circuit that is a processing target of a failure simulation according to an embodiment.

FIG. 3 is a pattern diagram showing an example of an input test pattern that requires pattern division processing.

FIG. 4 is a pattern diagram showing an example of an input test pattern that does not require pattern division processing.

FIG. 5 is a configuration diagram of an observation information storage table in which connection relations of logic circuits, failure assumption points, and unobservable flags are stored in the embodiment.

FIG. 6 is an explanatory diagram in which a fault propagation and an unobservable area when a third fixed value pattern is input to a logic circuit to be processed are expressed on the logic circuit.

FIG. 7 is an explanatory diagram showing an example of a truth table used in a logical operation.

FIG. 8 is an explanatory diagram in which a fault propagation and an unobservable region when a first fixed value pattern is input to a logic circuit to be processed are expressed on the logic circuit.

FIG. 9 is an explanatory diagram in which a fault propagation and an unobservable region when a second fixed value pattern is input to a logic circuit to be processed are expressed on the logic circuit.

FIG. 10 is an explanatory diagram showing the contents of an observation information storage table after a common unobservable region recognition process.

FIG. 11 is a configuration diagram of a processing target failure table that stores processing target failure points.

FIG. 12 is an explanatory diagram showing the contents of a processing target failure table excluding unobservable failures after the common unobservable area recognition processing.

[Explanation of symbols]

001,002,003,004,005,006,0
07,008,009,010,011,012,01
3,014,015,016,017,018,01
9,020,021,022,023,024,02
5,026,027,028,029,030,03
1,032,033,034,035,036,03
7,038,039,040,041,042,04
3,044,045,046,047,048,049
... Assumed failure point, 101, 102, 103, 104, 10
5, 106 ... External input terminal, 107 ... External output terminal, 2
01, 202, 203, 204, 207, 208, 20
9, 210, 211, 212, 213, 214, 21
5, 216 ... AND gates, 217, 218, 219 ...
OR gate, 205, 206 ... NOT gate, 301,
302, 303, 304 ... Unobservable area, 1010 ... Fixed value input terminal designation processing, 1020 ... Pattern division processing, 1
030 ... Fixed value pattern generation processing, 1050 ... Unobservable area tracking processing, 1070 ... Common unobservable area recognition processing, 1
100 ... Input test pattern information file, 1110 ... Connection relation information file, 1120 ... Observation information storage table, 1130 ... Process failure table, 1140 ... Failure detection rate, 1150 ... Failure expected value, 1160 ... Failure dictionary.

Claims (1)

[Claims] 1. An input test pattern composed of a combination of signal values created to detect a fault that may occur in the logic circuit is applied to an external input terminal group of the logic circuit to be inspected, and the external output terminal is applied to the external output terminal. In a fault simulation processing method for simulating a fault in a circuit based on an upcoming change in a signal value in the logic circuit, the type of the input test pattern is one or more less than the number of signal value combinations that can be logically set. , The input test pattern is divided into a first group having a fixed value of logic 0 or logic 1 and a second group having a fixed value of a combination of logic 0 and logic 1, Apply a fixed value to the corresponding external input terminal in each divided group, apply a non-fixed value to the other external input terminals, and set the logical values on all signal lines in the logic circuit. Obtained, traced in order from the external output terminal to the input side element by these logical values, calculated whether the signal change of the input terminal could be observed at the output terminal of each element, and could not be traced as an observable path Faults on observable paths are recognized without recognizing the region as an unobservable region and registering the faults included in the common unobservable region of each group as the processing target when performing the fault simulation on the input test pattern. Only the input test pattern is registered as a processing target when a fault simulation is performed, and when the fault simulation is performed for the fault on the observable path registered as the target of the fault simulation, the fault is detected. When the propagation destination of the influence of reaches the element in the unobservable area, the subsequent simulation processing is executed. A failure simulation processing method characterized by the absence thereof.