JPH04245338A - Throughput reducing method for fault simulation - Google Patents

Abstract

PURPOSE:To reduce the throughput of a fault simulation by recognizing an area wherein the influence of a fault can not be observed. CONSTITUTION:When one of the divided groups of an input pattern set is called as a pattern group, fixed value simulation which aims at the fixed value of an external input terminal is performed in a pattern group unit and an observable path is traced from the external output terminal to an input side in consideration of an observable path by using the simulation results to recognize the area 350 which can not be observed, thereby excluding the fault in the area from the objects of the process of the fault simulation. Further, a fault on a fixed line signal line is propagated as much as possible by previous fault propagation. The number of process object faults of the fault simulation is decreased and the propagation range of the faults is reduced so the throughput of the fault simulation is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault simulation method for logic circuits, and more particularly to a method for reducing the processing amount in fault simulation.

0002

2. Description of the Related Art Fault simulation involves calculating signal changes within a circuit for all test patterns for all possible faults that may occur within the circuit. Therefore, the processing amount of fault simulation is proportional to the product of the number of input test patterns, the number of hypothetical faults, and the number of gates corresponding to the logic circuit scale. In recent years, with the increase in the scale of logic circuits,
Both the number of hypothetical failures and the number of input test patterns are expected to reach a huge number, and the time required for failure simulation is also expected to increase significantly.

To deal with this problem, there is a method of reducing the number of faults to be processed as a method for speeding up fault simulation. Conventionally, the principle of deleting undetected faults,
Methods such as equivalent fault deletion are used. The former principle undetected fault is a fault that cannot be detected against any test pattern. Furthermore, the latter equivalent faults are mutually equivalent faults in which the logical expressions of a plurality of faults match, and it is sufficient to simulate them by using one of them as a representative fault. These faults could be recognized prior to fault simulation by using only the wiring relationships of the logic circuit to be inspected.

[0004] Also, 20th Design Automation Conference (1983), pages 214 to 220 (20th DAC 1983 (p.
p. 214-p. p. Critical Path Tracing - Alternative Tow Fault Simulation (Bell 220)
Laboratories) (CRITICAL PATH T
RACING-AN ALTERNATIVE TO
FAULT SIMLATION (Bell Labor
atories), the following methods are used. In other words, by tracing the critical path from the output side to the input side, where the effects of failure can be observed for each input test pattern, without performing failure simulation,
This makes it possible to recognize faults that can be detected with each input test pattern.

[0005]

[Problems to be Solved by the Invention] The above-mentioned prior art has the following problems. Methods such as principle-based undetected fault deletion and equivalent fault deletion are statically determined based on the connection relationships of logic circuits. In fault simulation, the fault detection status depends on both the wiring relationship of the logic circuit and the input test pattern. Therefore, in order to deal with the rapid increase in fault simulation time due to the recent increase in the scale of logic circuits, it is necessary to achieve an even greater effect of reducing the number of faults to be processed. To do this, it is necessary to adopt a dynamic method that takes into account not only the wiring relationships of logic circuits but also input test patterns.

On the other hand, the critical path tracing method can be said to be a dynamic method that takes into account the input test patterns, since it is possible to recognize detectable faults in the circuit under test for each test pattern. . However, even if the fault simulation time can be shortened by reducing the number of faults to be processed for each test pattern using the critical path tracing method, the problem is that the overhead required for processing to reduce the number of faults to be processed is too high. There is. Another problem is that the critical path tracing method does not take into account cases including reconvergence paths, and therefore cannot guarantee accurate failure simulation. Here, a reconvergence path is one in which a certain signal line branches, and the branch destinations are input to the same element again.
Refers to a signal path that consists of two signal lines. For example, this will be explained using FIGS. 15 and 16. These are cases where different test patterns are input to the same circuit with a reconvergence path. With the critical path tracing method,
When tracing the critical path from the output side, sensitivity calculations are performed for the input terminals of each element. That is, it calculates whether a signal change at an input terminal of a certain element is observable at its output terminal. Sensitive input terminals are observable, and insensitive input terminals are unobservable. AND gate 99
In the case of 0, the logic value 0 is input to the input terminals 940 and 950 in both FIG. 15(a) and FIG. 16(a). At this time, in the critical path tracing method, both input terminals 940 and 950 are determined to be insensitive. As a result, the region on the input side of the AND gate 990 is not traced, and faults within that region are considered to have no possibility of being detected in fault simulation. Actually, let's propagate a fault on the signal line 920. Failure 1210 in FIG. 15(b) is caused by element 97
Since the propagation of the fault stops up to 0,980, it can be seen that there is no detectability. However, since the fault 1010 in FIG. 16(b) propagates to the elements 970 and 980 and further propagates to the output terminal 960 of the element 990, it can be seen that this fault can be detected. Since the critical path tracing method does not recognize faults that can be detected by such reconvergence, it is excluded from the processing of fault simulation. As a result, the fault dictionary created as a result of the fault simulation may be inaccurate because the faults that should have been detected are not simulated and are therefore not registered. Many common logic circuits include reconvergence paths. Therefore, to ensure accurate fault simulation, it is necessary to consider circuits that include reconvergence paths.

An object of the present invention is to increase the effect of reducing the number of faults to be processed by a dynamic method using input test patterns in order to reduce the number of faults to be processed in fault simulation, and to reduce the overhead required for the processing. The purpose is to ensure the accuracy of the fault simulation by reducing the number of faults as much as possible and by considering the reconvergence path and making all detectable faults the subject of the fault simulation.

[0008]

[Means for Solving the Problems] In order to achieve the above object, an input test pattern is used as input information. However, this input test pattern is divided into one or more groups, each group includes multiple test patterns, and the test patterns in the group set a certain external input terminal to a logical value of 0 or 1. It is assumed that a fault in the logic circuit to be inspected is always detected by a test pattern within a certain group. Therefore, grouping test patterns does not affect the failure detection rate.

The present invention executes the following process for each group of test patterns prior to the failure simulation process.

First, a fixed value simulation focuses on the fixed value of an external input terminal that is always fixed in a test pattern in a group. A non-fixed value X is assigned to an external input terminal that is not a fixed value in order to distinguish it from a fixed value, and a logical operation is performed on the elements in the circuit using a fixed value pattern composed of these fixed values and non-fixed values as input. , find the logical value of each signal line.

Next, using the logic values of the signal lines in the logic circuit obtained as a result of this fixed value simulation, it is determined whether or not the signal change at the input terminal of each element can be observed at its output terminal. Evaluate the input terminal, follow the path in which signal changes can be observed from the external output terminal to the input side, and
For each element in the logic circuit, information indicating whether or not it is on this observable path is stored, and faults on the observable path are registered as faults to be processed in fault simulation. . Note that when evaluating the observability of the input terminal, we will perform the evaluation by considering the circuit when it includes a reconvergence path. In other words, if a certain element has multiple input logic values that control its output value,
All input terminals with these control logic values are observable,
Input terminals with other logical values are determined to be unobservable.

Furthermore, among the faults registered as processing targets in the fault simulation above, for faults for which the logical value of the fixed value simulation result of the signal line at the assumed fault position is a fixed value, a new Perform pre-failure propagation processing. In other words, a fault is propagated on a fixed value signal line, and faults where all the fault values at the propagation destination match the logical values of the fixed value simulation result and have become fixed values are excluded from the fault simulation target. Further, for a fault whose propagation destination fault value has become a non-fixed value X, the position just before the fault value changed to the non-fixed value is stored.

[0013]

[Operation] By reducing the processing amount of failure simulation for each group of test patterns, the present invention can reduce the overhead required for this processing compared to the case where the processing is performed for each test pattern. It is.

Furthermore, by performing a fixed value simulation, it is possible to recognize, in a logic circuit, a signal line having a fixed value whose logic value always remains unchanged in test patterns within the group. Using this result, it is possible to determine whether or not the influence of the failure is observable for all test patterns in the group. When making this determination, by using a determination method that takes the reconvergence path into consideration, it is possible to avoid overlooking failures that become observable due to reconvergence. By following an observable path, the logic circuit is eventually divided into an area on the observable path and an area other than that, that is, an unobservable area. As a result, faults included in the unobservable region can be excluded from the processing target of fault simulation because they are unobservable faults. In addition, by memorizing whether each element in the logic circuit is on an observable path or in an unobservable area, this information can be referenced for the element to which the fault propagates during fault simulation. Therefore, if the fault is within the unobservable region, it is possible to suppress the propagation of the fault from then on.

Furthermore, for faults on fixed value signal lines, all test patterns within a group perform the same operation as long as the fault value at the destination of the fault is a fixed value, so that these faults can be prevented in advance. By performing propagation, the same processing for the test patterns in the group is required to be performed only once, so that it is possible to avoid redundant processing of fault simulation. In addition, even if the fault value at the propagation destination becomes a non-fixed value X during pre-fault propagation, by memorizing the position just before the fault became the non-fixed value X, that position can be used in the fault simulation. This can be used as the starting position, and redundant processing of failure simulation can be avoided.

[0016]

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an input/output configuration diagram of the processing amount reduction method in failure simulation according to the present invention. As input, an input test pattern information file 100 and a connection relationship information file 110 of the logic circuit to be tested are used. In the present invention, input test patterns are divided into one or more groups, each group includes a plurality of test patterns, and at least one external input terminal whose logical value is always fixed within the group is divided into one or more groups. Use one or more existing ones. For example, if the circuit to be tested is a scan circuit added to facilitate diagnosis, all flip-flops in the circuit are addressed. Therefore, it is possible to group flip-flops with consecutive addresses. By using the test patterns generated for each group of flip-flops, test patterns can be grouped, and since the addresses of flip-flops in that group are fixed so that flip-flops other than that group are not activated, There may be a fixed external input terminal. in this way,
The input test pattern information file 100 includes an input test pattern 105 indicating a signal sequence of each test pattern,
Stored are test pattern information 115 in which the test patterns are divided into groups and which shows the test patterns belonging to each group, and fixed value information 125 which shows the external input terminals and their fixed values that are fixed within each group. Using these as input, the unobservable areas in the logic circuit are recognized using the processing amount reduction method 120 in fault simulation of the present invention for each group of test patterns. The unobservable area information 140 is determined. Here, unobservable means that when there is a fault in a certain signal line, the signal change between the normal logic value and the fault logic value when the fault is propagated does not reach the external output terminal, and within this area. Since the faults included in are unobservable, they cannot be detected even by fault simulation. The fault table 130 to be processed in the fault simulation obtained in this manner is obtained by removing faults in the unobservable region from all faults that may occur in the logic circuit. Further, the unobservable information of the logic circuit indicates whether each element in the logic circuit is included in the unobservable region. The failure simulation is performed using the obtained results, the logic circuit connection relationship information file, and the input test pattern information file as input. As a result, the failure detection rate was 160 and the expected output value was 1.
70 and the fault dictionary 180 are found. In the present invention, a fault that cannot be detected within a certain test pattern group can be detected within any other test pattern group, so the undetectable range is subject to simulation. By setting it outside, the failure detection rate 160 will not be affected in any way. Also,
When recognizing an unobservable area, it is taken into consideration that detectable faults are not included in the area, so a simulation of detectable faults is always performed. Therefore, the fault dictionary 180 does not lack accuracy.

Next, the processing flow of the method for reducing the amount of failure simulation processing according to the present invention will be explained in order with reference to FIGS. 2 to 5. If a group of test patterns is called a pattern group, each pattern group has
Prior to fault simulation, a series of processes including fixed value simulation 200, unobservable area recognition processing 230, and preliminary fault propagation processing 270 are performed. Hereinafter, each process will be explained in detail using an example.

FIG. 3 shows the processing flow of the fixed value simulation 200. The purpose of this processing is to obtain fixed values for signal lines in the circuit. First, in initialization 209, the output value of each element in the target logic circuit is assigned a non-fixed value X that can take on both 0 and 1 within the pattern group. Next, in step 210 of assigning the fixed value of the pattern group to the external input terminal, for example, the test pattern group information 115 in FIG. 7 and the fixed value information 125 in FIG. 8 are used. In the test pattern group information 115, pattern groups are numbered, and the test numbers and fixed value input numbers belonging to the pattern groups are shown in the order of pattern group numbers 400. The fixed value information 125 is
Information for 430 fixed value inputs is shown in order of pattern group number 400, that is, fixed value input element numbers 460 indicating external input terminals to which fixed values are input and their fixed values 470. Now, if we look at the case where pattern group number 400 is 1, pattern group number 1 includes test patterns with test pattern numbers 1 to 100.
It can be seen that the number of fixed value inputs 430 is two. This 2
It can be seen that the fixed values 0 and 1 are input to external input terminals 2 and 5, respectively. Assume that the target logic circuit is 315 in FIG. Each element in the circuit is numbered from 1 to 11, element numbers 1 to 5 are external input terminals, element numbers 10 and 11 are external output terminals, element numbers 6 and 8 are OR gates, and element number 7 ,9
is an AND gate. Further, the faults that may occur in this logic circuit, that is, the faults that should be processed in the fault simulation, are the faults F1 to F13. The connection relationship 110 of the elements in this logic circuit has a table structure as shown in FIG. This table consists of multiple rows corresponding to each element. Corresponding to the element number 500 in the logic circuit, an element type 505 indicating the type of the element, an output value 510 of the element, an unobservable flag 505 indicating whether it is included in the observable area, 520, 525, 530 are element numbers input to the element, 535, 540 are element numbers to which the element is output, 545, 550, 555 are input failures of the element, and 560, 565 are output failures. The unobservable flag 505 will be explained in the next unobservable area recognition process. In this circuit, when the pattern group number 400 in FIG. 7 is 1, the number of fixed value inputs is two, and the breakdown is as shown in the fixed value information in FIG.
The external input terminals PI2 and PI5 of No. 5 have fixed values of 0 and 1, respectively. Therefore, fixed values are assigned to external input terminals PI2 and PI5 as shown in FIG. Since no fixed value is input to the external input terminals PI1, PI3, and PI4 to which a fixed value is not assigned, a non-fixed value X that can take on both 0 and 1 within the pattern group is assigned. In this way, a pattern consisting of fixed values and non-fixed values is assigned to the external input terminal. This pattern will be referred to as a fixed value pattern. Therefore, using the fixed value pattern as input, a logical operation is performed 215 on each fan-out destination element. When performing logical operations, a three-value truth table of fixed values 0 and 1 and non-fixed value X is used. For example, (a) in FIG.
The truth table shows 1500 in the case of a 2-input AND gate, and 1510 in the case of a 2-input OR gate in (b). 1520 represents the logical value of the input terminal I1, and 1530 represents the logical value of the input terminal I2. The calculation result is stored at 220, and the output value 510 of the element is stored. Processes 215 and 220 are repeated until 225, in which the calculation result is not a fixed value or the calculation result is an external output terminal, is satisfied. As a result, the logical values of each signal line in the circuit are determined, and the signal lines 341, 341,
It can be seen that 344, 345, 347, and 348 are fixed values within this pattern group.

Next, FIG. 4 shows the unobservable area recognition process.
Explain using. In terms of the logic circuit 315, this processing involves recognizing an unobservable area 350 in the circuit, determining an unobservable flag 505 for each element in the circuit, and detecting a failure in the unobservable area. The test patterns in the pattern group are excluded from failure simulation processing. Here, unobservable means that the propagation path of the fault is not continuous to the external output terminal, that is, the signal change of the fault disappears before reaching the external output terminal, and an unobservable fault is not detected. This is an unavoidable malfunction. Further, the unobservable flag 505 indicates whether or not the unobservable area is included, and is the unobservable area information 140 of the logic circuit added to each element in the logic circuit, and the unobservable flag 505 is on. When it is OFF, that is, when it is 1, it indicates that it is included in the unobservable region, and when it is OFF, that is, when it is 0, it indicates that it is not included in the unobservable region.

Specifically, first, in process 235, the unobservable flags 505 of all elements in the circuit are initialized to ON. After that, the following process is repeated for all external output terminals. This will be explained using FIGS. 10 and 11. The logic circuit 315 first selects the external output terminal 329 of element number 10 as the observability evaluation element 240. Since it is clear that the external output terminal is observable, the unobservable flag 505 of this element number 10 is turned off, that is, set to 0.
Fault table 1 to be processed by fault simulation
This input fault F12 is registered in 30. FIG. 14 shows an example of a target failure table for failure simulation. This table stores a fault position 800 indicating a hypothetical fault position in the logic circuit, and a fault value 810 which is a logical value when a fault is assumed. Next, shift the evaluation element to the OR gate 327 of element number 8, which is the element on the input side.
50, and in process 255, the observability is evaluated by sensitivity calculation.

The sensitivity calculation performed here focuses on whether a control logic value that controls the output value of the element is input, and calculates whether a signal change at the input terminal can be observed at the output terminal. Each input terminal is evaluated. Here, the control logic value refers to a logic value that, if at least one exists at the input of an element, determines the output value of that element regardless of other inputs; in the case of an OR gate, it is 1. , if it is an AND gate, it is 0. Also,
As the logical value of the signal line in this calculation, the logical value obtained as a result of the fixed value simulation described above is used. As a result of this calculation, each input terminal is classified into a sensitive input terminal and an insensitive input terminal. A sensitive input terminal means that the signal change on that terminal is observable, and an insensitive input terminal means that it is not observable. For example, FIGS. 12A and 12B show sensitivity calculation results for a 2-input OR gate and a 2-input AND gate, respectively. This shows a respective sensitivity flag 710 for each input logic value 700 of input terminals I1, I2. Both the OR gate and the AND gate are sensitive if no control logic value is input to both input terminals. Furthermore, if a control logic value is input to either one, the input terminal to which that control logic value is input is sensitive, and the other input terminals are not sensitive.

According to this, OR gate 3 of element number 8
27 has inputs of logical values 1 and X, so that the input terminal for logical value 1 is sensitive and the input terminal for X is not sensitive. For sensitive input terminals, the OR gate 3 of element number 6, which is the element on the input side,
25 is selected as the evaluation element, and processes 245 and 250 are repeated. Also, for non-sensitive input terminals,
Since that input side is unobservable, observability is not evaluated thereafter. As a result, the external output terminal 32 of element number 10
The path taken from 9 is the external input terminal 321 of element number 2.
reach. In addition, the external output terminal 330 of element number 11
The path to follow is the sensitivity calculation of the AND gate 328 with element number 9, and the input logic value is a non-fixed value X,
Since the control logic value of the AND gate is 0, the signal line 34
It reaches the external input terminal 324 of element number 5, which is the input side of element number 4.

In this way, from the external output terminal, the observability of each element on the input side is evaluated by sensitivity calculation in order, and the route of the sensitive signal line is traced. As shown in judgment statements 251 and 252, the stop condition for tracing is that there is no sensitive input terminal, or that the unobservable flag 505 of the element on the input side of the sensitive input terminal is off, or that there is no external input terminal. This is a case where you are satisfied with something. As a result, the unobservable flag 505 of each element is determined, and the faults on that path are registered as faults to be processed in the fault simulation, and the fault table 130 to be processed in the fault simulation for the test patterns in this pattern group is shown in FIG. Decide as follows. As a result, there are 26 possible failures in the logic circuit 315, as shown in FIG. Normally, it would be necessary to perform failure simulation for all of these. However, due to this unobservable area recognition process,
FIG. 1 shows a fault table 130 for fault simulation processing in which only observable faults within this pattern group are registered.
4, it is sufficient to simulate these 6 faults within this pattern group. Therefore, it can be seen that the number of failures to be processed in failure simulation can be significantly reduced. Regarding the faults in the fault table to be processed for fault simulation processing determined here, during fault simulation for the test patterns in this pattern group, the unobservable flag 505 of the element to which the fault is propagated is referred to, and if the unobservable flag 505 If it is on, it is unobservable even if it propagates from then on, so it cannot be detected at the external output terminal. Therefore, by propagating a fault only when the unobservable flag 505 of the propagation destination element is off, the range of fault propagation can be reduced. Further effects can be expected by recognizing the unobservable area as wide as possible. In the present invention, the following points are taken into consideration when recognizing an unobservable area. If a detectable fault is included in that area, fault simulation will not be performed for that fault. Therefore, the fault dictionary obtained as a result of the simulation becomes inaccurate because the faults that should be detected are not registered because they are not simulated. Therefore, all detected faults were processed to be subject to fault simulation. The above may occur when a logic circuit includes a reconvergence path. For example, in FIG. 15, signal line 920 is branched into two and input to elements 970 and 980. The output destinations of these elements are both input to element 990. In this way, a path in which a once-branched signal line inputs into one element again and becomes one is called a reconvergence path. The logical values in the figure are the results of fixed value simulation. Suppose that element 990 is reached after following the path of a sensitive signal line from a certain output side. Therefore, sensitivity calculation is performed for this element. Both input terminals 940 and 950 have AND gate control logic value 0.
is inputting. Therefore, even if a signal change propagates to either of the inputs, the other input is 0, so
Since the output value of the AND gate does not change, conventionally, both of these two input terminals have been determined to be non-sensitive. As a result, the elements 970 and 980 are included in the unobservable region, and the faults F20, 21, and 22 in that region are not subject to processing in the fault simulation. (b) in Figure 15
), a fixed zero fault 1210 on the signal line 920
When actually simulated, the propagation destination stops at elements 970 and 980, so it becomes unobservable on the output side beyond that point. Therefore, in such a case, this sensitivity calculation is correct.

However, consider a case as shown in FIG. Compared with FIG. 15, FIG. 16 shows a case in which the logic circuit is the same, but the fixed value simulation results for signal lines 910, 920, and 930 are different. In this case, element 99
Since the logic value of the 0 input terminal is the control logic value 0 of the AND gate, if sensitivity calculation is performed in the conventional manner, an unobservable region similar to that shown in FIG. 15 can be recognized. Fault F20 on signal line 920 also becomes unobservable. However, as shown in FIG. 16(b), when we actually simulate the 1-fixed fault 1010 on the signal line 920, the propagation destination is input to elements 970 and 980, and furthermore, their output terminals 940, It can be observed at 950, and then by inputting it simultaneously to element 990, it becomes observable at the output terminal of element 990. Therefore, if the effects of this fault propagate further, this fault can be detected at the external output terminal. Therefore, it is a mistake to include this fault in the unobservable region.

Therefore, in the present invention, a new sensitive input terminal (uncertain) is provided for the sensitivity flag, and when a plurality of control logic values of a certain element are input, the control logic values are input. Set this flag for all input terminals. Sensitive input terminals (uncertain) are handled in the same way as sensitive input terminals when recognizing unobservable regions. This makes it possible to recognize the unobservable region considering the reconvergence path, and to deal with the above problem.

However, such processing that takes reconvergence paths into consideration causes the following problems. By regarding non-sensitive input terminals as sensitive input terminals, the unobservable region becomes narrower, thereby increasing the number of faults to be processed in fault simulation and expanding the range of fault propagation during fault simulation. To address this problem, a preliminary fault propagation process 270 is implemented. This process is based on the faults in the fault table for fault simulation processing created by the unobservable region recognition process.
For faults on fixed value signal lines, fault propagation is performed as much as possible before fault simulation. Here, a failure on a fixed value signal line means that the logical value of the signal line that assumes a failure is the fixed value 0 as a result of a fixed value simulation.
or 1. When a fault simulation is performed for such a fault, as long as the fault value is a fixed value, all test patterns in the current target pattern group will be affected by the propagation of the fault on the fixed value signal line. The signal change is the same. In advance fault propagation processing, the same processing that is performed for the number of test patterns in a pattern group in fault simulation is performed only once for each pattern group, thereby making it possible to avoid redundant processing in fault simulation.

FIG. 5 shows a flowchart of the preliminary fault propagation process 270. In step 275, a fault is extracted from the fault table to be processed in the fault simulation, determined by the unobservable region recognition processing. In process 285, if this fault is a fault on a fixed value signal line, the fault is inserted into the logic circuit. That is, a failure value is set at the assumed failure position. In process 290, this fault logic value is propagated to the fan-out destination, and logical operations are performed on each element one by one to perform processing equivalent to fault simulation. When performing logical operations, the logical values of the input terminals of each element are determined as a result of fixed value simulation.

The conditions for stopping the simulation in the pre-propagation process are: first, all logical values at the destination of fault propagation are fixed values, and the logical values of the fixed value simulation result match the fault logical values; be. This fault cannot be detected because it is always unobservable even in fault simulation in test patterns within the pattern group. Therefore, it is deleted from the fault table to be processed in the fault simulation. Thereby, the number of failures to be processed in the failure simulation can be reduced, and the processing time for the failure simulation can be reduced.

The simulation is also stopped when the fault logic value of the faulty propagation destination is a non-fixed value X. Further, in step 305, the position of the propagation destination immediately before the element whose logical operation result has changed to the non-fixed value X is stored for each fault, and the starting position in the fault simulation is set from this propagation destination position.

In order to omit the determination of whether the fault is on a fixed value signal line in the judgment statement 280, when registering a fault in the fault table 140 to be processed for fault simulation in the unobservable region recognition process, the fault is detected as a fixed value signal line. It is best to distinguish whether or not it is a line failure before registering it.

FIG. 17 is an example of simulating the fixed 0 fault 1426 on the signal line 1417 using a certain pattern group using prior fault propagation. The logic value of the signal line is the logic value determined as a result of fixed value simulation, the fault propagation destination is shown above the /, and the bottom of the / shows the fault logic value. First, this failure occurs when the fan-out destination element 1411 and
412. As a result of performing a logical operation on these elements, the output value of the element 1411 becomes a fixed value of 0, and since the normal logical value and the faulty logical value are different, it is further propagated to the fan-out destination element 1413, and a logical operation is performed on the element 1413. Then, the fault logic value becomes a non-fixed value X. On the other hand, the output value of the element 1412 is a fixed value of 1, and the normal logic value and the faulty logic value match. Therefore, as a result of the prior fault propagation of this fault, the element 141 changed to a non-fixed value
3 is stored. In the fault simulation, for the test patterns in this pattern group, what is performed for the fault 1426 can be performed for the fault 1427, so that the processing range of the fault simulation can be reduced. In advance fault propagation processing, the wider the range in which the fault value of the fault propagation destination is a fixed value, the more the effect of reducing the processing amount of fault simulation can be expected.

FIG. 18 is an example of a table structure of faults during preliminary fault propagation. (a) shows the fault position 800 and the fault value 81 corresponding to the fault on the fixed value signal line that was the target of the preliminary fault propagation processing in the unobservable region recognition processing.
0, the number of propagation destination registered failures 1220, and the pointer 1230.
is stored. The number of propagation registered faults 1220 is the number of registered fault positions immediately before changing to a non-fixed value X as a result of preliminary fault propagation, and is initialized to 0 before preliminary fault propagation. Further, a pointer 1230 indicates the registered table position. (b) shows a table of the registered failures. For example, the number of registered propagation destinations for a 0-fixed fault at the fault location F14 is one, and the registered fault at the propagation destination is the fault location F that is stored in the first location pointed to by the pointer 1230.
15 fixed zero failures. A failure in which the number of registered propagation destinations 1220 is 0 is a failure in which all propagation destinations have disappeared. Therefore, for faults on the fixed value signal line, fault simulation is performed only for faults in which the number of registered propagation destinations 1220 is 1 or more, and the starting position is set as the registered fault in the propagation destination.

Furthermore, if the fault propagates to the external output terminal due to preliminary fault propagation, it means that the fault has been detected. Therefore, such a fault can be registered in the fault dictionaries of all test patterns in this pattern group without performing fault simulation.

[0034]

According to the present invention, by performing processing for reducing the processing amount of failure simulation for each pattern group, the overhead can be reduced compared to the case where processing is performed for each test pattern. In addition, by excluding unobservable faults within a pattern group, the number of faults to be processed in fault simulation can be reduced, and by setting the fault propagation range during fault simulation outside the unobservable region, The propagation range can be reduced. Furthermore, by applying advance fault propagation processing to faults on fixed value signal lines, it is possible to perform fault simulation processing for the number of test patterns in one pattern group only once per pattern group. , as redundant processing in fault simulation can be omitted, processing time can be shortened, and as a result of preliminary fault propagation, all propagation destinations have disappeared, and faults that are recognized as undetectable faults are not subject to fault simulation. This has the effect of reducing the number of faults to be processed, and by moving the fault simulation start position of a fault whose propagation destination has not disappeared to its propagation destination, the propagation range of the fault simulation can be shortened.

[Brief explanation of the drawing]

FIG. 1 is an input/output configuration diagram of a method for reducing processing amount in failure simulation according to the present invention.

FIG. 2 is a flowchart of a schematic process of a method for reducing processing amount in failure simulation according to the present invention.

FIG. 3 is a flowchart of fixed value simulation in the present invention.

FIG. 4 is a flowchart of unobservable area recognition processing in the present invention.

FIG. 5 is a flowchart of advance fault propagation processing in the present invention.

FIG. 6 is a conceptual diagram on a logic circuit of a method for reducing processing amount in failure simulation according to the present invention.

FIG. 7 is an example of a table structure of test pattern group information that stores information regarding pattern groups that are processing units of the present invention.

FIG. 8 is an example of a table structure storing fixed value information for each pattern group in the present invention.

FIG. 9 is an example of a table structure storing connection relationships of logic circuits that are input in the present invention.

FIG. 10 is a diagram expressing on a logic circuit a route that follows a signal line more sensitive than the external output terminal PO1 in the unobservable area recognition process according to the present invention.

FIG. 11 is a diagram expressing on a logic circuit a route that follows a signal line more sensitive than the external output terminal PO2 in the unobservable area recognition process according to the present invention.

FIG. 12 is an example of sensitivity calculation for observability evaluation in the present invention.

FIG. 13 is an example of a table structure of all faults in a circuit to be processed in a fault simulation when the fault simulation processing amount reduction method of the present invention is not implemented.

FIG. 14 is an example of a table structure of failures to be processed in failure simulation when the method for reducing the processing amount of failure simulation according to the present invention is implemented.

FIG. 15 is an example in which a conventional sensitivity calculation does not cause any problem even if the reconvergence path is not recognized.

FIG. 16 is an example in which a problem occurs if the reconvergence path is not recognized in conventional sensitivity calculation.

FIG. 17 is a diagram expressing the advance fault propagation process in the present invention on a logic circuit.

FIG. 18 is an example of a fault table structure after preliminary fault propagation in the present invention.

FIG. 19 is an example of a truth table used during logical operations in the present invention.

[Explanation of symbols]

100...Input test pattern information file, 105...Input test pattern, 115...Test pattern group information, 1
25...Fixed value information, 110...Logic circuit connection relationship information file, 130...Fault table for failure simulation processing, 140...Unobservable area information of logic circuit, 150
...fault simulation, 160...fault coverage rate, 170
...Expected output value, 180...Fault dictionary, 200...Fixed value simulation, 230...Unobservable area recognition process, 270
...Preliminary fault propagation processing, 350...Unobservable region, 505
...unobservable flag, 710...sensitivity flag,
1010...1 fixed failure, 1210, 1426, 1427
...0 fixed failure, 320, 321, 322, 323, 32
4...External input terminal, 329, 330...External output terminal, 3
25, 327, 1412, 1413, 1414...OR gate, 326, 328, 970, 980, 990, 14
10, 1411...AND gate, 1500...2 input AN
Truth table of D gate, 1510...truth table of 2-input OR gate.

Claims (2)

[Claims] Claim 1: A connection relationship information file of a logic circuit to be inspected, a set of input test patterns created to detect all possible failures in the logic circuit, and a set of input test patterns that are based on some criteria. If the input test pattern set has already been divided into three or more groups, or if the input test pattern set is arbitrarily divided, and each group contains multiple test patterns, all test patterns belonging to the group are If there is at least one external input terminal that inputs a fixed value whose logical value is fixed to 0 or 1, first, before performing a failure simulation for each test pattern, the logical value is input for each group. For external input terminals whose values are fixed to 0 or 1, a fixed value of 0 or 1 is assigned respectively, and a logic value of 0 or 1 is assigned to the external input terminal.
A non-fixed value Find the logical values on all signal lines, and use these logical values to calculate whether or not the signal change at the input terminal can be observed at the output terminal of each element in order from the external output terminal to the input side element. , as long as there are observable input terminals or until an external input terminal is reached, areas that have not been traced as observable routes can be traced within the group within the logic circuit. When performing fault simulation on the test patterns in the group, only faults that are not included in the unobservable region, that is, faults on observable paths, are recognized as areas where the effects of failures are unobservable. By not registering faults included in the unobservable area as being subject to failure simulation, it is possible to reduce the number of failures subject to failure simulation. When performing a fault simulation for a fault on an observable path, if the propagation destination of the fault reaches an unobservable region, the propagation is suppressed from then on, so that the fault during the fault simulation is A method for reducing the amount of processing in fault simulation characterized by shortening the propagation range. [Claim 2] In the method for reducing the amount of processing in fault simulation as set forth in claim 1 of the claims, for each group of test patterns obtained by dividing an input test pattern, a test pattern on an observable path as a processing target of fault simulation is provided. When registering a fault, the logical values of the signal lines at the registered fault hypothetical positions, that is, the fixed values and non-fixed values in the test patterns in the group, are assigned to external input terminals and logical operations are performed on the elements in the circuit. The resulting logical value is either a fixed value that remains unchanged in all test patterns in the group, or a non-standard value that can take on both logical values 0 and 1 within the test patterns in the group. For faults in which the logic value of the signal line at the fault location is a fixed value, the logic value of the signal line at the fault location is registered separately, and the fault propagation is performed using the logic value of the result of the logic operation prior to fault simulation. As a result, the number of simulations for the number of test patterns in the group is reduced to one.
It is possible to reduce redundant processing in fault simulation by completing the process in one cycle, and also to ensure that the output logic values of the elements to which the fault is propagated all match the values before the fault propagation and become fixed values. In this case, the propagation of the fault is suppressed from then on, and the number of faults to be processed in the fault simulation is reduced by excluding the fault from the processing target of the fault simulation. If the output logical value becomes a non-fixed value The method is characterized in that the fault propagation range in fault simulation for each test pattern in the group is reduced by shifting the insertion position of A method for reducing the amount of processing in failure simulation.