JP2773148B2 - Circuit design method for testability - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a logic circuit, and more particularly to a design method for testability.

[Conventional technology]

In order to eliminate defective products in the manufactured integrated circuit, a test pattern is applied to the input terminal and a test for observing the pattern on the output terminal is performed. In particular, in a large-scale integrated circuit, it is often difficult to detect a failure in the circuit from an output pattern with a high probability only by selecting an input pattern. For this purpose, a testability design method is used.

The design method for testability includes a circuit division method in which a circuit is added so that the output inside the circuit can be observed and led to an output terminal, and a scan configuration method in which a circuit that can observe the output of the flip-flop circuit is added. . In these design methods, an increase in circuit scale due to an additional circuit poses a problem.

Therefore, a design method that achieves the required fault coverage with as few circuits as possible becomes important. For this purpose, a conventionally used design method is to add a circuit by trial and error while checking a failure detection rate by a failure simulation.

[Problems to be solved by the invention]

In the above-described conventional design method, a high fault detection rate can be obtained by (1) a step of examining a fault that has not been detected by the fault simulation and (2) a step of adding a circuit for detecting the fault based on the fault. And it takes a lot of trouble.

[Means for solving the problem]

According to the present invention, in a logic circuit design method including a logic gate composed of one or a plurality of basic logic elements, a failure simulation is performed on the logic circuit, and all the gates or a specific function is performed up to the logic gate. A method for designing a testable circuit is provided in which the number of propagated faults that do not propagate to an output terminal is recorded, and a circuit that makes it possible to externally observe the output of a logic gate having a certain number or more is obtained.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart of one embodiment of the present invention.
The circuit 1 and the test pattern 2 are input to the fault simulation 3 to perform a fault simulation. At this time, a fault propagated to each logic gate composed of one or a plurality of basic logic elements is transmitted to the propagation fault memory 5 and to an external fault memory. The detected fault is output to the detected fault memory 4 which holds the fault detected at the output terminal.

The contents of the propagation fault memory 4 and the detected fault memory 5 are input, and the number of the gate faults not included in the detected fault memory 4 included in the propagated fault memory 5 is determined for each gate by the divided gate selection means 6. A dividing circuit 9 in which a gate exceeding the gate is extracted, and a circuit for inputting the circuit 1 by the circuit dividing means 8 and enabling the output of the gate in the circuit 1 to be directly observed from outside is added.
Is output.

FIG. 2 is a flowchart showing details of the division gate selection means 6. Refer to the propagation fault memory and the detected fault memory for each gate in the circuit, and count the number of faults included in the propagation fault memory and not included in the detected fault memory, that is, the number of faults that have propagated to the gate and have not been detected. The number is obtained and compared with the judgment value. If the number is larger than the judgment value, it is determined as the target gate of the circuit dividing means.

FIG. 3 is a circuit diagram of a circuit for implementing one embodiment of the present invention.

In FIG. 3, partial circuits 20, 21 and logic gates 30 to 32 are shown.
Constitutes a logic circuit 50 before application of the present invention. Logic circuit 50
A test pattern is input from input terminals 15 and 16 to perform a failure simulation. As a result, fn (n = 1 to 30)
The fault shown in 9) propagates, and among these faults, f1, f2, f
It is assumed that 4, f5 and f8 are detected at the output terminals 40 to 41.

The number of faults that have propagated to the logic gates 30 to 32 and have not been detected are 1, 1, and 2, respectively. Here, the logic gate 32 is selected by comparing with an appropriate judgment value 1. next,
If a test circuit 60 consisting of an output terminal 43 and a wiring leading from the output of the logic gate 32 to the output terminal 43 is added, the undetected fault is f
3, f6 only. In this way, the position where the test circuit should be added can be easily determined. Here, the logic gates 30 to 32 are described as an example of the determination target, but the logic gates in the partial circuits 20 and 21 may be determined.

FIG. 4 is a flowchart of another embodiment of the present invention.

In the present embodiment, the target gate of the method of the present invention is limited to a flip-flop gate (hereinafter referred to as F / F).
As a circuit for observing the output of / F, a circuit that realizes a scan configuration such as a scan path (Kenji Kani, Basics of Ultra LSICAD, Ohmsha, 1983, pp. 181-184) is used. The circuit 1 and the test pattern 2 are input to the fault simulator 3 to perform a fault simulation.
For each F, a fault propagated there is output to the propagation fault memory 5 and a fault detected at the external output terminal is output to the detected fault memory 4. The contents of the propagation fault memory 5 and the detected fault memory 4 are inputted, and the number of the ones included in the propagation fault memory 5 and not included in the detected fault memory 4 for each F / F is obtained by the F / F gate selecting means 10. An F / F exceeding the judgment value 7 is extracted, and the circuit 1 is inputted to the scan configuration means 11 to add a circuit necessary for scan configuration of the F / F in the circuit 1.
Is output.

FIG. 5 is a flowchart showing details of the scan F / F selection means 6. Refer to the propagation fault memory for each F / F,
The number of faults included in the corresponding propagation fault and not included in the detected fault memory is obtained, and compared with a determination value to determine whether or not to use the scan F / F, and input the scan F / F.

FIG. 6 is a circuit diagram of a circuit for implementing another embodiment of the present invention. In FIG. 6, the partial circuits 20, 21 and the logic gates 30 to 32 constitute a logic circuit 50 before application of the present invention. A test pattern is input from the input terminals 15 and 16 to the logic circuit 50 to perform a fault simulation. As a result, F /
It is assumed that faults indicated by fn (n = 1 to 9) propagate to F30 to F32, and among these faults, f1, f2, f4, f5, and f8 are detected at the output terminals 40 to 41. The number of faults that have propagated to the F / Fs 30 to 32 and have not been detected are 1, 1, and 2, respectively. Here, the F / F 32 is selected by comparing with an appropriate determination value 1.

Next, the F / F32 is changed to a scan F / F33 in which a circuit for a scan configuration is added, and a test circuit for connecting to the input terminal 17 and the output terminal 43 is added to the scan configuration. Only f6. So easily,
The position where the test circuit should be added can be determined. Here, the determination targets are F / Fs 30 to 32 as an example, but the F / Fs in the partial circuits 20 and 21 may be determined.

[Effects of the Invention] As described above, according to the present invention, it is possible to design a logic circuit having a high fault detection rate with a small amount of trouble, and particularly, there is a great effect in designing a large-scale integrated logic circuit.

[Brief description of the drawings]

FIG. 1 is a flowchart of one embodiment of the present invention, FIG. 2 is a flow chart showing details of the divided gate selecting means 6, FIG. 3 is a circuit diagram of a circuit used in one embodiment of the present invention, FIG. 4 is a flowchart of another embodiment of the present invention;
FIG. 5 is a flowchart showing details of the F / F gate selecting means 10 of FIG. 4, and FIG. 6 is a circuit diagram of a circuit used in another embodiment of the present invention. 1 ... circuit, 2 ... test pattern, 3 ... fault simulator, 4 ... detected fault memory, 5 ... propagation fault memory,
6 divided gate selection means, 7 judgment number, 8 circuit division means, 9 divided circuit, 10 F / F gate selection means, 11 scan configuration means, 12 scan configuration circuit , 15 to 17 Input terminals, 20 to 21 Partial circuits, 30 to 32
… F / F gate, 33… Scan F / F, 40 to 43… Output terminal, 50… Logic circuit, 60… Test circuit.

Claims (1)

(57) [Claims] In a logic circuit design method comprising a logic gate composed of one or a plurality of basic logic elements, a fault simulation is performed for the logic circuit, and all the logic gates or specific function gates are processed up to the logic gate. A test facilitating circuit design method characterized in that the number of propagated faults that do not propagate to an output terminal is recorded, and a circuit for externally observing the output of a logic gate having a certain number or more is added.