JPS6375576A - Fault detection system for integrated circuit - Google Patents

Abstract

PURPOSE:To improve a fault detection rate by detecting whether or not signal values of external output terminals of all fault circuits are different from the signal value of a normal circuit and deciding that fault circuits whose signal values are different from the signal value of the normal circuit can be detected as faults. CONSTITUTION:A characteristics initial value indicating 0 or 1 is assigned by a characteristic value assigning means 4 to output values of respective storage elements whose output signal values can not be determined under the influence of a fault. Then a fault detecting and deciding means 6 decides that the combination of the characteristic initial value assigned by the means 4 and an output value when an integrated circuit is normal and the combination of the characteristic initial value and an output value 1 when the integrated circuit is normal are detected at an external output terminal. Then either of the two combinations which are observed at the external output terminal is considered to be caused under the influence of the fault to detect the fault of the integrated circuit, so the high fault detection rate can be obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for inputting an input pattern sequence to an external input terminal of an integrated circuit to propagate the influence of a stuck-at fault determined inside the integrated circuit to an external output terminal. The present invention relates to an integrated circuit failure detection method for detecting a failure in an integrated circuit.

[Conventional technology]

As the density of semiconductor integrated circuits (LSI) increases, it is becoming increasingly difficult to determine whether the LSI is of good quality. LSI testing is performed by applying a pattern to an external input terminal and determining whether the pattern appearing at the external output terminal matches an expected value.

A stuck-at fault is usually used as a model for LSI failures. A stuck-at fault is a fault in which the signal value of a signal line is fixed at a certain value.A fault in which the signal value is fixed at 0 is called a stuck-at-0 fault, and a fault in which the signal value is fixed at 1 is called a stuck-at-1 fault. That's what it means.

Figure 10 is a diagram showing an example of such a stuck-at fault.
This shows a case where the signal value of the signal line F of the ND circuit is fixed to a signal value of 0.

The human cover turn applied to the external input terminal as a test of the LSI should be able to detect as many stuck-at faults as possible inside the LSI, and the fault detection rate is used as a measure of its quality. Fault coverage is the number of stuck-at faults whose influence can be observed at the external output terminal (i.e., the output cover pattern differs from the expected value if a fault exists), expressed as a percentage of the total number of stuck-at faults that can be assumed inside the LSI. be.

A fault simulator is usually used to determine the fault coverage rate. A fault simulator simulates a normal circuit with no faults and a faulty circuit for all possible faults in the LSI, and determines that it has detected a fault in the faulty circuit that causes a signal value different from that of the normal circuit at the external output terminal. Then, when the simulation of all human cover turns is completed, the failure detection rate for that person cover turn is determined.

A logic simulator simulates only normal circuits, whereas a fault simulator needs to simulate not only normal circuits but also faulty circuits corresponding to the number of faults that can be assumed in the circuit, resulting in an enormous amount of calculation. Therefore, methods for efficiently simulating a large number of faulty circuits have been considered, and representative methods include parallel methods and concurrent methods. All of these fault simulators are equipped with fault detection and determination means that determines that a fault has been detected when the signal value at the external output terminal of a faulty circuit differs from the signal value at the external output terminal of a normal circuit.

FIG. 11 is a table showing signal values handled by a conventional fault simulator. Figure 12 is a table showing the combinations of the signal values shown in Figure 11 between the normal circuit and the faulty circuit, and the signal values are different between the normal circuit and the faulty circuit indicated by the circle in Figure 12 at the external output terminal. In the case of combinations, the failure detection and determination means determines that the failure can be detected, and in the case of combinations in which the signal values of the normal circuit and the faulty circuit match, as indicated by the x marks in FIG. is not determined to be fault detectable.

The fault simulator uses AND gate, ΦR gate, N
In addition to basic gates such as oT gates, functional elements such as memory elements are treated as constituent elements of a logic circuit.

[Problem that the invention seeks to solve]

By the way, in conventional fault simulators, in the case of a faulty circuit in which the clock does not enter a memory element due to a fault, as shown in Figure 13, the output of this memory element remains at an undefined value X forever in the simulation, and no This failure was not detected even for such input patterns.

However, if such a faulty circuit actually exists, the output value of this memory element will remain either signal value 0 or signal value 1, and the fault can be detected, so the memory in the simulation There was a problem in that the element model did not adequately represent the actual circuit, and it could not be determined that the above-mentioned failures could be detected.

This invention was made to solve the above-mentioned problems, and provides a failure detection method in which even if a failure causes a clock to not be input to a storage element, the effect of the failure is detected at an external output terminal. The purpose is to

[Failure to solve the problem]

For this reason, the present invention provides a unique initial value allocating means 4 that expresses 0 or 1 to the output value of each storage element whose output value cannot be determined due to the influence of a failure, and a unique initial value assigned by the unique initial value allocating means 4 and an integrated value. Failure detection determination that determines that the combination of the output value O when the circuit is normal and the combination of the above specific initial value and the output value 1 when the integrated circuit is normal can be detected at the external output terminal. The device is characterized in that it detects a failure in the integrated circuit by detecting either of the above two combinations observed at the external output terminal as the influence of the failure.

[Effect]

In this invention, a unique initial value is assigned to each failure signal value of the output of each storage element whose output signal value cannot be determined due to the influence of a failure, and a normal signal value 0 and a unique initial value, and a normal signal value 1 and a unique initial value are assigned. If the combination of both propagates to the external output terminal, it is determined that the failure has been detected.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing an example of the failure detection method of the present invention. In the figure, 1 initializes the signal values of the signal lines of all the elements constituting the logic circuit to an undefined value X for the normal circuit and all the faulty circuits. 2 is a faulty circuit implication operating means for determining the signal value of a signal line whose value is determined by a fault for all faulty circuits; 3 is a faulty circuit implication operating means for determining a signal value of a signal line whose value is determined by a fault for all faulty circuits; Faulty storage element detection means for detecting a missing memory element; 4 indicates a memory element i detected by the faulty storage element detection means 3 for each faulty circuit;
5 is a fault simulation means for simulating normal circuits and all faulty circuits; 6 is a fault simulation means for allocating signal values of external output terminals to all faulty circuits; Fault detection and determination means compares whether the signal value is different from the signal value of the normal circuit and determines that a faulty circuit that is different from the signal value of the normal circuit can be detected as a fault; This is a fault coverage calculation means that calculates a ratio to the number of faults as a fault coverage rate.

Next, the operation of the present invention will be explained with reference to FIG.

FIG. 2 shows the flow of a logic circuit fault detection method according to the present invention. In FIG. 2, initial value setting means 1 sets all internal signal values and external input terminals in normal circuits and all faulty circuits.

The signal value of the external output terminal is initialized to an undefined value X, and all failures are marked as undetected (step Fl). The faulty circuit implication operating means 2 determines the signal values of signal lines whose signal values are determined by faults in all faulty circuits.
(Step F2). The faulty storage element detection means 3 determines whether there is a memory element in all the faulty circuits in which a clock cannot be input to the clock input terminal due to a fault and the output signal value cannot be determined. If there is, the process proceeds to step F4; if not, to step F5. Go to (Step F3).

The unique initial value allocating means 4 allocates a unique initial value Xi to the output failure signal value of the storage element i whose output signal value cannot be determined in each failed circuit (step F4). The fault simulation means 5 simulates a normal circuit and all faulty circuits for one-person cover turn (step F5). The fault detection and determination means 6 compares the signal value of the normal circuit and the signal value of each faulty circuit at the external output terminal, and marks the faults of the faulty circuits with different signal values as detectable (step F6). If there are still input patterns, go to step F5; if there are no more input patterns, go to step F8 ((step F7). A failure coverage rate expressed as a percentage is calculated (step F8).

FIG. 3 shows signal values handled in the logic circuit fault detection method to which the present invention is applied. Xi and Xi are signal values newly introduced in the present invention, and represent the unique initial value of the storage element i whose output signal value cannot be determined due to a failure. This Xi and Xi
is a signal value that appears only in a faulty circuit and is a type of indefinite value, but in the present invention, it is a signal value unique to the storage element i, so it is treated in the same way as signal values 0 and 1.

Figure 4 shows the truth table for the two-man AND gate when handling the signal values in Figure 3, Figure 5 shows the truth table for the two-man 5R gate, and Figure 6 shows the NOT gate. FIG. 7 is a front page showing the truth table of the D latch, which is a storage element. These truth tables are the second
Faulty circuit implication operation in step F2 and step F5
applied to the simulation of normal and faulty circuits.

Figure 8 shows the criteria for determining whether or not the failure can be detected by comparing the signal value at the external output terminal of the normal circuit and the signal value at the external output terminal of each faulty circuit in step F6 of Figure 2. This is the front door, and the signal value is 1 in a normal circuit. In the case of a combination shown by O in FIG. 8 in which the signal value is different between a normal circuit and a faulty circuit, such as a signal value of 0 in a faulty circuit, it is determined that the fault is detectable at that point. Also,
Either the signal value of the normal circuit and the signal value of the faulty circuit are the same, or the signal value of either the normal circuit or the faulty circuit is an indefinite value
In the case of the combination indicated by the X mark in FIG. 8, the failure is not determined to be detectable.

The combination indicated by Δ in Figure 8 has a signal value of 0.1 in a normal circuit.
and the signal values Xi and Xi of the faulty circuit, and these cannot be determined to be detectable as they are. That is, 0
/Xi (normal circuit/faulty circuit) and 1/Xi, O/X
The fault can only be detected when any of the four combinations i and 1/Xi, 0/Xi and 0/Xi, and 1/Xi and 1/Xi are observed at the external output terminal. It will be judged.

The above will be explained according to the circuit example shown in FIG. Figure 9(a) is an example of a circuit consisting of two two-manual AND gates and one D latch.
Consider a faulty circuit with an O stuck-at fault at the output of 2.

FIG. 9(b) is a left diagram showing changes in the signal values of each signal line in the circuit and the determination of failure detection at the end of each step in FIG. 2 when a five-person cover turn is given. First, step F
1, the signal values of all signal lines in the circuit are initialized to an undefined value X, and faults are marked as undetected. Next, in step F2, a contemplative operation regarding the fault is performed, and the output of the AND gate G2 becomes a signal value 0 in the faulty circuit. In step F3, the memory element D latch 1 does not receive a clock to its clock input terminal due to a failure.
is detected, and a unique initial value X+ is assigned to the signal value of the faulty circuit of this D latch 1 in step F4. Since there are five input patterns, steps F5 and F6 are repeated five times. In the second step F6, the signal value of the normal circuit is 0/the signal value of the faulty circuit is X at the external output terminal 01.
r was observed, but since 1/X1 or 0/X+ has not been observed yet, it cannot be determined that it is detectable, and it is remembered that 0/X1 was observed. 4th step F6
Since 1/X1 is observed at the external output terminal 01 and 0/X1 has been observed as I I- in the past, it is determined that this failure is detectable for the first time at this point.

If a stuck-at fault exists in an actual logic circuit, not shown in FIG. When the signal value is 1, it can be detected using the second pattern. While conventional methods could not determine that such faults are detectable, by using the unique initial values of the present invention, it is now possible to determine that such faults are detectable. became.

Note that although the above embodiment describes the case where the present invention is applied to a D latch, it is clear that the present invention can also be applied to memory elements other than D latches.

Further, although the above embodiments are implemented using software, it is also possible to implement this system using a hardware device.

〔Effect of the invention〕

As explained above, the present invention provides unique initial value assignment means that assigns a unique initial value representing O or ] to the output value of each storage element whose output value cannot be determined due to the influence of a failure; The combination of the specific initial value and the output value 0 when the integrated circuit is assumed to be normal, and the combination of the above specific initial value and the output value 1 when the integrated circuit is assumed to be normal are detected at the external output terminal. The present invention is configured to detect a failure in the integrated circuit by detecting either of the above two combinations observed at the external output terminal as the influence of the failure. This also has the effect of ensuring a high failure detection rate.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the flow of operation of the present invention. Figure 3 is the left diagram of signal values handled in the present invention, Figure 4 is the left diagram showing the truth table of the two-man-powered AND gate, and Figure 5 is the truth table of the two-man-powered OR game 1).゛The left diagram, 2 Figure 15 is the left diagram showing the truth table of the NOT gate, Figure 1 is the truth table of the D latch. The left diagram shows the criteria for determining whether it is possible or not, Figure 9 is a diagram showing an example of a circuit to which the present invention is applied, Figure 10 is a diagram showing an example of a stuck-at fault, and Figure 11 is a diagram of a conventional circuit. The left diagram shows the signal values handled by the fault simulator, Figure 12 shows the criteria for determining whether a fault can be detected in the conventional method, and Figure 13 shows the fact that the output of the D Lasoge cannot be determined due to a fault in the conventional method. FIG. DESCRIPTION OF SYMBOLS 1... Initial value setting means, 2... Fault circuit implication operation means, 3... Fault storage element detection means, 4... Unique initial value assignment means, 5... Fault simulation means, 6.
. . . Failure detection determination means; 7. . . Failure detection rate calculation means. Agent Masuo Oiwa (2 idiots) Fig. υA" 7 □ Fig. 12

Claims (1)

[Claims] An integrated circuit that detects a failure in an integrated circuit by inputting to an external input terminal of the integrated circuit an input pattern sequence that propagates the influence of a stuck-at fault assumed inside the integrated circuit to an external terminal of the integrated circuit. In a circuit failure detection method, a unique initial value assigning means assigns a unique initial value representing 0 or 1 to the output value of each storage element whose output value cannot be determined due to the influence of the failure, and a unique initial value assigned by the unique initial value assigning means. A combination of the initial value and an output value of 0 when the integrated circuit is assumed to be normal, and a combination of the above specific initial value and an output value of 1 when the integrated circuit is assumed to be normal are detected at the external output terminal. failure detection determination means for determining the failure detection of an integrated circuit, and detects a failure of the integrated circuit by detecting one of the above two combinations observed at an external output terminal as an influence of the failure. method.