JPH0798365A - Fault detection factor calculating method for test pattern and device thereof - Google Patents

Abstract

PURPOSE:To provide the fault detection factor calculating method for a test pattern and its device capable of calculating the fault detection factor on the bridging fault of the test pattern. CONSTITUTION:Two nodes A1, B1 are selected in a net list, an exOR gate D inputted with signals from two selected nodes A1, B1 is virtually inserted into the net list, and the new net list is logically simulated, with the output signal from the exOR gate D used as a virtual external output terminal T. Whether '1' is outputted from the virtual external output terminal T for a sufficiently long period during this logical simulation or not is checked, this check is repeated for a combination of two other nodes, and the fault detection factor of the test pattern is calculated from the ratio between the number of all combinations and the number of detections of '1'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern fault coverage detection method and apparatus for calculating the fault coverage of a test pattern.

[0002]

2. Description of the Related Art A manufactured digital circuit chip is subjected to a test for normal operation before shipment. In this test, a digital signal called a test pattern is input to the digital circuit chip, and the quality of the chip is judged from the output result.

The reliability of this test depends on the fault coverage of the test pattern. That is, if the failure detection rate of the test pattern is not 100%, even if it is determined that the product is a good product in this test, defective products are actually mixed with a certain probability.

Therefore, it is ideal that the above test pattern can detect all possible faults in the digital circuit (fault detection rate 100%), and the test pattern having the highest possible fault detection rate is adopted. It is desired to improve the quality of the test itself.

A device called "fault simulator" is known as a device for calculating the fault detection rate of a test pattern. This device is a device that assumes a failure in the netlist and investigates by simulation whether this failure is detected by a prepared test pattern. For simplification of description, for example, assuming that the digital circuit to be tested is the inverter 20 of FIG. 5 and a failure in which the output section is always "1" is assumed, the test pattern including the digital signal "1" is input. If so, "0" should be output from the output unit, so that if the output unit becomes "1" as described above, it can be determined as a failure. That is, it can be determined that the test pattern described above is effective for the assumed failure.
On the other hand, when it is assumed that the output section is always "0", the failure cannot be found by the test pattern composed of the digital signal "1".

Regarding the above-mentioned inverter 20, it is considered that the input section is always "1" or "0" and the output section is always "1" or "0". The test pattern consisting of is effective for a failure in which the input section is always "0" and a failure in which the output section is always "1", and two of the four possible failures can be found. The pattern failure detection rate is 50
% Will be calculated. Further, the failure detection rate of the test pattern composed of the digital signal "1" is 50% as well. Then, by using a test pattern composed of these two digital signals "1" and "0", the failure detection rate becomes 100%. As described above, the method of fixing a specific part of the circuit to “1” or “0” is STU.
They are called CK-AT-1 and STUCK-AT-0.

[0007]

However, in the above STUCK-AT-1 and STUCK-AT-0, only the stuck-at fault is taken into consideration, and between two nodes which are likely to occur in a miniaturized CMOS. Short circuit failure (B
Ridging Fault) is not considered. Therefore, even if the failure detection rate of the test pattern is sufficiently high, there is a problem that it is not known whether the test pattern is effective for the Bridging Fault.

For example, as shown in FIG. 6, in a circuit including two inverters 21 and 22, when a Bridging Fault as shown by a dotted line in the drawing exists, "0" and "0" are placed in the inverters 21 and 22. "And" 1 ",
Even if a test pattern consisting of "1" is input, the Bridge
The ging Fault cannot be detected. However, in the above-mentioned conventional failure simulator, the above "0",
Even with a test pattern composed of "0", "1", and "1", as described above, the failure detection rate becomes as high as 100%. That is, even if the failure detection rate of the test pattern is sufficiently high, the Bridging
It may not be valid for Fault.

By the way, the above-mentioned Bridging Fa
There is "cross check" as a technique in which ult is also targeted for failure. This is emb in a grid pattern on the actual circuit.
The bridging fault can also be detected by embedding a test point called eded-array and checking the potential of each node from an external terminal (see US Pat. No. 4,749,947).

However, this conventional technique has a drawback of lacking versatility because the circuit can be constructed only by a designing method of regularly arranging cells in which grid-shaped test points are embedded in advance.

In view of the above circumstances, it is an object of the present invention to provide a test pattern failure detection rate calculation method and apparatus capable of calculating the failure detection rate of a test pattern with respect to the Bridging Fault.

[0012]

In order to solve the above-mentioned problems, the test pattern fault coverage calculating method of the present invention comprises a first step of selecting two nodes in a netlist of a digital circuit, and A second step of inserting into the netlist an exclusive logic circuit which inputs signals from two selected nodes and outputs a signal indicating that when both inputs have different values, the exclusive logic circuit Third step of adding an output signal from the virtual output terminal to the netlist as a virtual external output terminal, a fourth step of logically simulating a new netlist including the exclusive logic circuit and the virtual external output terminal, and a virtual external during the logic simulation. Check whether a signal indicating that the above two inputs have different values is output from the output terminal for a sufficiently long time. And a fifth step, the first
It is characterized in that the processes from the second step to the fifth step are repeated for the combination of the other two nodes selected in the step.

Further, the test pattern failure detection rate calculation apparatus of the present invention receives the first means for selecting two nodes in the netlist of the digital circuit and the signals from the two selected nodes as inputs. When the two inputs have different values, a second means for inserting an exclusive logic circuit that outputs a signal indicating that input into the netlist, and an output signal from the exclusive logic circuit as a virtual external output terminal A third means for adding to the list, a fourth means for logically simulating a new netlist including the exclusive logic circuit and the virtual external output terminal, and both inputs from the virtual external output terminal during the logical simulation. Fifth means for checking whether signals indicating different values are output for a sufficiently long time, and the first means
It is characterized in that the processing in the second to fifth means is repeated for the combination of the other two nodes selected by the means.

Further, in the above-mentioned first configuration, the first step may be configured to select two nodes that are close to or adjacent to each other, judging from the mask layout data of the digital circuit.

Further, in the above-mentioned second structure, the first means may be arranged to judge from the mask layout data of the digital circuit and select two nodes which are close to or adjacent to each other.

[0016]

In the above first and second configurations, a test pattern is input to a new netlist including an exclusive logic circuit and a virtual external output terminal to perform logic simulation,
In this simulation, it is checked whether or not signals having different values are output from the two selected nodes.

If signals having different values are output from the two nodes in this check, the test pattern input at this time is the Bri signal between the two nodes.
It can be said that the pattern can detect a dogging fault.

Then, the above-mentioned check is repeated for the combination of the other two nodes selected in the first step or the first means to calculate the fault detection rate for the Bridging Fault of the test pattern.

Further, in the third and fourth configurations, the above check is not performed for all combinations of two nodes in the netlist, but they are judged to be close to or adjacent to each other by judging from the mask layout data of the digital circuit. Will be performed for the combination of the two nodes selected as. This is a bridge between two nodes that are far apart from each other on the mask layout.
It is focused on that the ging fault is unlikely to occur, and it is possible to make the calculation of the fault coverage of the test pattern quick and maintain the reliability of the calculated fault coverage.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments.

FIG. 1 shows the basic configuration of the test pattern failure detection rate calculation apparatus of this embodiment. This failure detection rate calculation device has the same basic configuration as a logic simulator used in digital circuit design, and is composed of an external storage device 1, a computer main body 2, and a display device 3.

The external storage device 1 stores test pattern data to be inspected, netlist data, and the like. Further, the external storage device 1 can store the calculation result by the computer main body 2.

The computer main body 2 comprises an arithmetic unit, a main storage device and the like. The arithmetic unit executes a test pattern failure detection rate calculation process described later, and a program for the above process is stored in the main storage device. Further, the main storage device includes the external storage device 1 described above.
The netlist data is loaded from.

The display device 3 is the computer main body 2 described above.
In addition to displaying a netlist based on the netlist data on the screen, the result of the above processing can be displayed.

Next, the test pattern failure detection rate calculation processing performed by the computer main body 2 will be described with reference to the flowchart of FIG.

First, as initial setting, X1 = 0, Y = 0
Is performed (step 1). The above X1 indicates the remaining number of repetitions of the processing described below, and Y is incremented when the test pattern is valid. Then, based on the loaded netlist data,
The combination of every two nodes in the netlist is determined, the number of combinations X and the circuit connection data of each combination are stored, and the process of X1 = X is performed (step 2).

Next, one combination is selected from the above determined combinations, and X1 ← X1-1
Is performed (step 3). Then, an exclusive OR gate (hereinafter abbreviated as exOR gate) that receives signals from the above-mentioned two selected nodes is virtually inserted into the netlist, and the output of the exOR gate is used as an external output terminal. It is virtually added to the netlist (step 4).

Visually showing the processes of steps 3 and 4 described above, for example, as shown in FIG. 3, the partial circuits A, B and C are provided, and the input terminals I _{1 to} I ₃ and the output terminal O _{1 are included.} in the digital circuit with a ~ O _3, FIG. 4
, The partial circuits A and B are provided as the two nodes.
Lines A1 and B1 (indicated by thick lines in the figure) are selected, the exOR gate D is virtually connected so that the signals of the partial circuits A and B are input, and its output is used as a virtual external output terminal T. It will be added to the netlist.

Next, the new netlist including the exOR gate D and the virtual external output terminal T is logically simulated (step 5). That is, the test pattern to be inspected is input to the new netlist.

Then, during the above logic simulation, it is checked whether "1" is output from the virtual external output terminal T for a sufficiently long time (step 6). The fact that "1" is output from the virtual external output terminal T means that
The inputs of the exOR gates D are not the same, that is, "1",
Indicates "0" or "0" or "1".

If "1" is detected by the above check, the process of Y ← Y + 1 is performed (step 7). on the other hand,
If "1" is not detected, the process directly proceeds to step 8.

In step 8, it is judged whether or not the above check is completed for all combinations of two nodes on the net list. That is, it is determined whether or not X1 = 0.

If X1 = 0 is not satisfied, there is an unchecked combination, so the routine proceeds to step 3 and the above processing is repeated. It should be noted that the already selected combinations are not selected again.

On the other hand, if X1 = 0, the above check has been completed for all combinations, so Y / X is calculated to calculate the fault detection rate of the test pattern (step 9). In this embodiment, the calculation result is displayed on the display device 3 and stored in the external storage device 1.

According to the above configuration, a test pattern is input to a new netlist including the exOR gate D and the virtual external output terminal T to perform a logic simulation, and two nodes arbitrarily selected in this simulation are different from each other. It is checked whether a value signal is output. If signals having different values are output from the two nodes in this check, it can be said that the test pattern input at this time is a pattern capable of detecting the Bridging Fault between the two nodes.

Then, the above-mentioned check is performed for all combinations of every two nodes in the netlist, thereby bridging the test pattern.
The fault detection rate for Fault is calculated.

It should be noted that it is best to perform the above-mentioned check for every combination of two nodes in the netlist as in the above embodiment, in order to calculate an accurate fault coverage, but this is not always the case. It doesn't have to be.

For example, instead of judging the combination of every two nodes in the netlist based on the process of the step 2, that is, based on the loaded netlist data, the judgment is made from the mask layout data of the digital circuit and they are close to each other. -Determine the combination of two adjacent nodes. Then, one combination may be sequentially selected from the group of combinations determined to be adjacent and adjacent to each other, and the check may be repeated.

Bridging Fa is present between two nodes located far away from each other on the mask layout.
Since the fault is unlikely to occur, even if such Bridging Fault between two nodes is excluded from consideration in the calculation of the fault coverage, the reliability of the calculated fault coverage is not deteriorated. Rather, Bri calculated by considering only the combinations in which the Bridging Fault is likely to occur is calculated.
It can be said that the fault coverage for the dogging fault becomes more accurate. Further, since the combination limited in this way is used, the number of times the check is repeated is reduced, and the failure detection rate calculation of the test pattern can be speeded up accordingly.

The selection of the combination in step 3 of the above embodiment may be performed in consideration of the priority order. For example, it is assumed that a combination of two nodes that are adjacent to or close to each other on the mask layout has a higher priority, and such a combination with a higher priority is processed first, and the combination with a higher priority is checked (step 6). If "0" is detected at, the test pattern is Bridged Fa at that stage.
It is also possible to terminate the processing as an ineffective one for the ult.

In the above embodiment, the exclusive OR gate is used as the exclusive logic circuit that is virtually added to the netlist, but an exclusive NOR gate may be used instead. In this case, in step 6,
It will be checked whether "0" is output from the virtual external output terminal T for a sufficiently long time.

[0042]

As described above, according to the present invention, it becomes possible to calculate the failure detection rate for the Bridging Fault of the prepared test pattern.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a test pattern failure detection rate calculation device of the present invention.

FIG. 2 is a flow chart showing a method of calculating a fault coverage of a test pattern, which is executed by the apparatus of FIG.

FIG. 3 is an explanatory diagram visually showing an example of a net list.

FIG. 4 is an explanatory diagram visually showing a state in which an exOR gate is virtually connected to a netlist and its output is a virtual external output terminal.

FIG. 5 is a circuit diagram showing an example of a digital circuit.

FIG. 6 is a circuit diagram illustrating a Bridging Fault.

[Explanation of symbols]

 1 External Storage Device 2 Computer Main Body 3 Display Device D Exclusive OR Gate

Claims (4)

[Claims] 1. A first step of selecting two nodes in a netlist of a digital circuit, and showing signals from the selected two nodes as inputs when both inputs have different values. A second step of inserting an exclusive logic circuit that outputs a signal into the netlist, a third step of adding an output signal from the exclusive logic circuit to the netlist as a virtual external output terminal, and the exclusive logic circuit The fourth step of logically simulating a new netlist including a virtual external output terminal, and whether a signal indicating that the two inputs have different values from each other is output for a sufficiently long time during the logical simulation. And a fifth step of checking whether or not the combination of the other two nodes selected in the first step is described above. A method of calculating a fault coverage for a test pattern, characterized in that the processes of the second to fifth steps are repeated. 2. A first means for selecting two nodes in a netlist of a digital circuit and a signal from the selected two nodes as an input, and when both inputs have different values, the first means is selected. Second means for inserting an exclusive logic circuit for outputting a signal shown in the netlist; third means for adding an output signal from the exclusive logic circuit to the netlist as a virtual external output terminal; A fourth means for logically simulating a new netlist including a logic circuit and a virtual external output terminal, and a signal from the virtual external output terminal indicating that the both inputs have different values during the logic simulation for a sufficiently long time. And a fifth means for checking whether or not it is output,
The test pattern failure detection rate calculation device is configured to repeat the processes in the second to fifth means for the combination of the other two nodes selected by the means. 3. The first step of selecting two nodes in a netlist of a digital circuit is to select two nodes that are close to or adjacent to each other, judging from the mask layout data of the digital circuit. The test pattern failure detection rate calculation method according to claim 1. 4. The first means for selecting two nodes in a netlist of a digital circuit is adapted to select two nodes which are close to or adjacent to each other, judging from the mask layout data of the digital circuit. The fault detection rate calculation device for a test pattern according to claim 2, wherein.