JP3184023B2 - Method and apparatus for calculating failure detection rate of test pattern - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for calculating a fault coverage of a test pattern, which can calculate the fault coverage of the test pattern.

[0002]

2. Description of the Related Art A manufactured digital circuit chip undergoes a test before shipment to see if it operates normally. In this test, a digital signal called a test pattern is input to a digital circuit chip, and the quality of the chip is determined from the output result.

[0003] The reliability of this test depends on the failure detection rate of the test pattern. That is, if the failure detection rate of the test pattern is not 100%, defective products are actually mixed at a certain probability even if it is determined to be good products in this test.

Therefore, it is ideal that the test pattern can detect all possible faults in a digital circuit (fault detection rate 100%), and employs a test pattern having a fault detection rate as high as possible. It is desirable to improve the quality of the test itself.

[0005] As an apparatus for calculating a failure detection rate of a test pattern, an apparatus called a "fault simulator" is known. This device is a device that assumes a failure in a netlist and checks by simulation whether this failure is detected by a prepared test pattern. For the sake of simplicity, for example, assume that the digital circuit to be tested is the inverter 20 in FIG. 5 and that a test pattern consisting of a digital signal "1" is input when a failure in which the output section is always "1" is assumed. Then, since "0" should normally be output from the output unit, if the output unit becomes "1" as described above, this can be determined as a failure. That is, it can be determined that the test pattern is effective for the assumed failure.
On the other hand, when it is assumed that a failure in which the output section is always "0", the failure cannot be found in the test pattern including the digital signal "1".

With respect to the above-mentioned inverter 20, a fault in which the input portion is always "1" or "0" and a fault in which the output portion is always "1" or "0" are considered, and the digital signal "1" is considered. Is effective for a fault in which the input section is always "0" and a fault in which the output section is always "1", and two out of four possible faults can be found. The failure detection rate of the pattern is 50
% Will be calculated. Similarly, the test pattern composed of the digital signal "1" also has a failure detection rate of 50%. By using a test pattern composed of these two digital signals "1" and "0", the failure detection rate becomes 100%. In this way, failure
Assuming that a specific part of the circuit is "1" or "0"
In many cases, the failure model is fixed.
Fault models such as STUCK-AT-1, STU
It is called CK-AT-0.

[0007]

However, in the above-mentioned STUCK-AT-1 and STUCK-AT-0, only the stuck-at fault is considered, and the STUTCK-AT-1 and the STUCK-AT-0 are connected between two nodes which are likely to occur in a miniaturized CMOS. Short failure (B
Ridging Fault is not considered. For this reason, even if the failure detection rate of the test pattern is sufficiently high, there is a problem that it is not known whether the test pattern is valid for the bridging fault.

For example, as shown in FIG. 6, in a circuit having two inverters 21 and 22, when a bridging fault as shown by a dotted line in the drawing exists, "0" and "0" are supplied to the inverters 21 and 22. "And" 1 ",
Even if a test pattern consisting of “1” is entered,
ging Fault cannot be detected. However, in the conventional failure simulator, the above “0”,
Even with a test pattern consisting of "0", "1", and "1", as described above , the failure detection rate becomes extremely high, such as 100%. That is, even if the failure detection rate of the test pattern is sufficiently high, the bridging
It may not be valid for Fault.

The above-mentioned Bridging Fa
“Cross-check” is a technology that also targets “ult” for failure. This is because emb
A bridging fault can be detected by embedding a test point called an eded-array and checking the potential of each node from an external terminal (see US Pat. No. 4,749,947).

However, this prior art has a drawback that it lacks versatility because a circuit can be formed only by a design method of regularly arranging cells in which grid-like test points are embedded in advance.

The present invention has been made in view of the above circumstances, and has as its object to provide a method and an apparatus for calculating a failure detection rate of a test pattern capable of calculating a failure detection rate for a bridging fault of a test pattern.

[0012]

According to the present invention, there is provided a method for calculating a fault coverage of a test pattern, comprising the steps of: selecting two nodes in a netlist of a digital circuit; A second step of inserting in a netlist an exclusive logic circuit that receives signals from the two selected nodes as inputs and outputs a signal indicating that both inputs have different values from each other; A third step of adding an output signal from the external circuit to the netlist as a virtual external output terminal, a fourth step of performing a logical simulation of a new netlist including the exclusive logic circuit and the virtual external output terminal, Check whether a signal indicating that the two inputs have different values from the output terminal is output for a sufficiently long time. And a fifth step, the first
It is characterized in that the processing of the second step to the fifth step is repeated for another combination of two nodes selected in the step.

The test pattern fault coverage calculating apparatus according to the present invention comprises a first means for selecting two nodes in a digital circuit netlist, and a signal from the selected two nodes as an input. A second means for inserting into the netlist an exclusive logic circuit for outputting a signal indicating that both inputs have different values from each other, and a net output signal from the exclusive logic circuit as a virtual external output terminal A third means for adding to the list, a fourth means for performing a logic simulation of the new netlist including the exclusive logic circuit and the virtual external output terminal, and the two inputs being mutually connected from the virtual external output terminal during the logic simulation. Fifth means for checking whether or not a signal indicating a different value is output for a sufficiently long time;
It is characterized in that the processing in the second means to the fifth means is repeated for the combination of the other two nodes selected by the means.

In the above-mentioned first configuration, the first step may be configured to select two nodes that are close to or adjacent to each other, based on the mask layout data of the digital circuit.

Further, in the second configuration, the first means may be configured to select two nodes which are close to or adjacent to each other, based on the mask layout data of the digital circuit.

[0016]

In the first and second configurations, a logic simulation is performed by inputting a test pattern to a new netlist including an exclusive logic circuit and a virtual external output terminal,
In this simulation, it is checked whether or not signals having different values are output from the two selected nodes.

In this check, if signals having different values are output from the two nodes, the test pattern input at this time indicates that the Bri
It can be said that the pattern is a pattern that can detect the dging Fault.

By repeating the above check for the first step or the combination of the other two nodes selected by the first means, the fault detection rate for the bridging fault of the test pattern is calculated.

In the third and fourth configurations, the above check is not performed for all combinations of two nodes in the netlist, but is determined based on mask layout data of a digital circuit and is close to or adjacent to each other. Is performed for a combination of two nodes selected as. This is because a bridge between two nodes that are far apart from each other on the mask layout.
It is noted that ging fault is unlikely to occur, and it is possible to achieve both quick calculation of the failure detection rate of the test pattern and maintenance of the reliability of the calculated failure detection rate.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing the embodiments.

FIG. 1 shows the basic configuration of the test pattern fault coverage calculating apparatus according to the present embodiment. This failure detection rate calculation device has the same basic configuration as a logic simulator used in digital circuit design, and includes an external storage device 1, a computer main body 2, and a display device 3.

The external storage device 1 stores test pattern data to be inspected, netlist data, and the like. In addition, the external storage device 1 can store a calculation result by the computer main body 2.

The computer main unit 2 includes an arithmetic unit, a main storage device, and the like. The arithmetic device executes a process of calculating a failure detection rate of a test pattern, which will be described later, and a main storage device stores a program for the process. The main storage device includes the external storage device 1 described above.
Is loaded with netlist data.

The display device 3 includes the computer main body 2
Can display the netlist based on the netlist data on the screen and also display the result of the above processing.

Next, a process of calculating a failure detection rate of a test pattern performed by the computer main unit 2 will be described with reference to the flowchart of FIG.

First, as initial settings, X1 = 0, Y = 0
(Step 1). X1 indicates the remaining number of repetitions of the processing described below, and Y is incremented when the test pattern is valid. Next, based on the loaded netlist data,
The combination of every two nodes in the netlist is determined, the number of combinations X and the circuit connection data of each combination are stored, and the processing of X1 = X is performed (step 2).

Next, one of the combinations determined above is selected, and X1 ← X1-1.
(Step 3). Then, an exclusive OR gate (hereinafter, abbreviated as an exOR gate) that receives signals from the two selected nodes is virtually inserted into a netlist, and the output of the exOR gate is used as an external output terminal. It is virtually added to the netlist (step 4).

If the processing of the above steps 3 and 4 is visually shown, for example, as shown in FIG. 3, it is composed of partial circuits A, B and C, and has input terminals I _{1 to} I ₃ and output terminal O _1. in the digital circuit with a ~ O _3, FIG. 4
As shown in FIG.
(Shown in bold in the figure), and an exOR gate D is virtually connected so that the signals of the partial circuits A and B are input, and the output thereof is used as a virtual external output terminal T. It will be added to the netlist.

Next, a new netlist including the exOR gate D and the virtual external output terminal T is logically simulated (step 5). That is, a test pattern to be inspected is input to the new netlist.

Then, it is checked whether "1" is output from the virtual external output terminal T for a sufficiently long time during the above logic simulation (step 6). The fact that “1” is output from the virtual external output terminal T means that
The inputs of the exOR gate D are not the same, that is, "1",
Indicates “0” or “0” or “1”.

If "1" is detected by the above check, the processing of Y ← Y + 1 is performed (step 7). on the other hand,
If "1" is not detected, the process directly proceeds to step 8.

In step 8, it is determined whether or not the above check has been completed for all combinations of two nodes on the netlist. That is, it is determined whether or not X1 = 0.

If X1 is not equal to 0, there is an unchecked combination, so the process proceeds to step 3 and the above processing is repeated. Note that the already selected combinations are not selected repeatedly.

On the other hand, if X1 = 0, the above-mentioned check has been completed for all combinations, and the Y / X calculation is performed to calculate the failure detection rate of the test pattern (step 9). In the present embodiment, the calculation result is displayed on the display device 3 and stored in the external storage device 1.

According to the above configuration, a test pattern is input to a new netlist including the exOR gate D and the virtual external output terminal T to perform a logic simulation, and two different nodes selected arbitrarily in this simulation are different from each other. It is checked whether a value signal is output. If signals having different values are output from the two nodes in this check, it can be said that the test pattern input at this time is a pattern that can detect a bridging fault between the two nodes.

The above check is performed for all combinations of every two nodes in the netlist, so that the bridging of the test pattern is performed.
A fault detection rate for Fault is calculated.

It should be noted that, as in the above-described embodiment, it is best to perform the above-described check for any combination of two nodes in the netlist in order to calculate an accurate fault coverage. It is not necessary.

For example, instead of judging the combination of every two nodes in the netlist based on the loaded netlist data, instead of judging from the mask layout data of the digital circuit, the processing of step 2 is considered to be close to each other. -Determine the combination of two adjacent nodes. Then, one check may be sequentially selected from a group of combinations determined to be close to and adjacent to each other, and the check may be repeatedly performed.

The bridging fa between two nodes located far apart from each other on the mask layout.
Since the fault is unlikely to occur, even if the bridging fault between the two nodes is excluded from consideration in the calculation of the fault coverage, the reliability of the calculated fault coverage is not reduced. Rather, by considering only combinations that are likely to cause a bridging fault in this way, the calculated Bri
It can also be said that the fault coverage for the dging Fault is more accurate. Since the limited combination is used, the number of times of repetition of the check is reduced, and the calculation of the failure detection rate of the test pattern can be accelerated accordingly.

Further, the selection of the combination in step 3 of the above embodiment may be performed in consideration of the priority order. For example, a combination of two nodes that are adjacent or close to each other on the mask layout is set to have a higher priority, and the processing is performed first on the combination having the higher priority, and the combination having the higher priority is checked (step 6). If "0" is detected in the test, the test pattern is changed to Bridging Fa at that stage.
Alternatively, the process may be terminated as a case where there is no validity for the ult.

In the above embodiment, the exclusive OR gate is used as the exclusive logic circuit virtually added to the netlist. However, an exclusive NOR gate may be used instead. In this case, in step 6,
It is checked whether "0" is output from the virtual external output terminal T for a sufficiently long time.

[0042]

As described above, according to the present invention, it is possible to calculate the failure detection rate of the prepared test pattern with respect to the bridging fault.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an apparatus for calculating a fault coverage of a test pattern according to the present invention.

FIG. 2 is a flowchart illustrating a method of calculating a failure detection rate of a test pattern executed by the apparatus of FIG. 1;

FIG. 3 is an explanatory diagram visually illustrating an example of a net list.

FIG. 4 is an explanatory diagram visually showing a state where an exOR gate is virtually connected to a netlist and an output thereof is used as a virtual external output terminal.

FIG. 5 is a circuit diagram illustrating an example of a digital circuit.

FIG. 6 is a circuit diagram illustrating a bridging fault.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 External storage device 2 Computer main body 3 Display device D Exclusive OR gate

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-77562 (JP, A) JP-A-7-55894 (JP, A) JP-A-7-55887 (JP, A) JP-A-6-55887 194418 (JP, A) JP-A-5-264676 (JP, A) JP-A-58-207719 (JP, A) JP-A-56-82467 (JP, A) (58) Fields investigated (Int. Cl. ^7, DB name) G01R 31/3183 G01R 31/28 G06F 11/25 G06F 17/50

Claims (4)

(57) [Claims] 1. A first step of selecting two nodes in a netlist of a digital circuit, and when signals from the selected two nodes are input and both inputs have different values, this is indicated. A second step of inserting an exclusive logic circuit that outputs a signal into the netlist, a third step of adding an output signal from the exclusive logic circuit to the netlist as a virtual external output terminal, A fourth step of logic-simulating a new netlist including a virtual external output terminal, and whether a signal indicating that the two inputs have different values is output from the virtual external output terminal for a sufficiently long time during the logic simulation A fifth step of checking whether the other two node combinations selected in the first step are combined. A method for calculating a fault coverage of a test pattern, comprising repeating a process from a second step to a fifth step. 2. A first means for selecting two nodes in a netlist of a digital circuit, and inputting signals from the selected two nodes. A second means for inserting an exclusive logic circuit for outputting a signal shown in the netlist, a third means for adding an output signal from the exclusive logic circuit to the netlist as a virtual external output terminal, and Fourth means for logically simulating a new netlist including a logic circuit and a virtual external output terminal, and a signal for indicating that the two inputs have different values from the virtual external output terminal during the logical simulation for a sufficiently long time. Fifth means for checking whether or not the data is output.
A test pattern failure detection rate calculation apparatus characterized in that the processing in the second means to the fifth means is repeated for another combination of two nodes selected by the means. 3. The first step of selecting two nodes in the netlist of the digital circuit is to select two nodes that are close to or adjacent to each other, based on the mask layout data of the digital circuit. The method of calculating a fault coverage of a test pattern according to claim 1, wherein: 4. A first means for selecting two nodes in a netlist of a digital circuit selects two nodes which are close to and adjacent to each other, based on mask layout data of the digital circuit. 3. The apparatus for calculating a fault coverage of a test pattern according to claim 2, wherein: