JP2785901B2 - Test sequence generation method and test sequence generation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test sequence generation method and a test sequence generation apparatus for generating a test sequence used for a fault test of a digital circuit.

[0002]

2. Description of the Related Art In recent years, digital circuits have been greatly developed into LSIs, and have been used in various fields.
Since the LSI cannot directly observe the internal signal,
With the increase in the scale of I, techniques relating to failure inspection in the inspection stage have become important.

[0003] With respect to the failure inspection of digital circuits, various methods have been proposed for automatically generating a test sequence for detecting a failure in advance. In general, the presence or absence of a failure is determined by adding a suitable input sequence to the input terminal of the circuit under test and comparing the result obtained from the output terminal with the expected result. The input sequence used for this is a test sequence. This test sequence is generated so that each of the previously assumed faults can be tested.

[0004] A conventional test sequence generation method is the PRENTI
CE-HALL, Englewood Cliff, N
"FAULT TOLERAN" published by ew Jersey
T COMPUTING Theory and Tech
nicks VolumeI ", Chapter 1 1.4.2" Stuck at Fault Testi "
ng "and the material of the 1991 European Design Automation Conference [T. Nier
mann and J.M. H. Patel, "HITEC:
A TEST GENERATION PACKAGE
FOR SEQUENTIAL CIRCUIT
S, "1991", etc. The test sequence generation method in the above-described conventional technique will be described below.

[0005] As a prerequisite for generation of a test sequence, a fault to be tested is a fault assumed based on a circuit under test and is modeled. Specifically, it is a stuck-at fault. That is, a fault in which the signal line of the circuit has a value fixed to logic 0 or 1, and there are a 0 stuck-at fault and a 1 stuck-at fault. These stuck-at faults are listed in advance for each signal line based on the netlist of the LSI to be tested and registered in the fault table. An example of this failure table is shown in FIG.
It is shown in FIG. In the figure, “signal line” indicates each signal line existing in the circuit under test, “fault” indicates whether stuck-at-0 fault (sa-0) or 1 stuck-at fault (sa−1), and “detection” indicates “1”. "Processing" has been processed by "1" to indicate that the test sequence has been successfully generated for the fault or that the fault can be detected by a test sequence that detects another fault. In other words, the fact that the generation process (regardless of whether the process was successful or unsuccessful) has been executed by being selected as the subject of the test sequence generation process indicates that the “redundant fault” is “1” and that the fault is a redundant fault. Indicates an undetectable failure, respectively. For example, the sa-0 failure of the signal line a in FIG. 3A indicates that a test sequence generation process has been performed, and as a result, it is found that the test sequence is not a redundant failure, and that the test sequence generation has been successful. In addition, the sa-1 failure of the signal line c indicates that the test sequence generation processing has been executed and is not a redundant failure, indicating that the generation of the test sequence has failed. FIG. 12 is a diagram showing a conventional test circuit generation method for a sequential circuit.

In FIG. 1, step 401 indicates the start of a test sequence generation process for a sequential circuit. In step 402,
Referring to the failure table, a failure in which a test sequence other than the redundant failure has not been generated (the “detection” column is 0, hereinafter, referred to as an undetected fault), and a process of generating a test sequence is still being executed. It is determined whether or not there is no failure ("Process" column is 0; hereinafter, referred to as an unprocessed failure). If there is, the process proceeds to step 403. If not, the process proceeds to step 408.

At step 403, one fault (hereinafter referred to as a target fault) for which a test sequence is to be generated is selected from a group of undetected and unprocessed faults. At this time, the “processing” column of the failure table corresponding to the target failure is set to “1”. In step 404, as a pre-stage of the test sequence generation of the sequential circuit, first, only the combinational circuit portion is targeted.
By generating a test input for the target fault, it is determined whether or not the fault is a logically undetectable fault (hereinafter, redundant fault). As a result, if the target fault is a redundant fault, the corresponding “redundant fault” in the fault table is set to “1”, and the process proceeds to step 402. By this step, undetectable faults can be eliminated in advance before the test sequence is generated.

In step 405, for the target fault selected in step 403, a process of generating a sequence that propagates the influence of the target fault from the fault location to any external output pin (hereinafter, fault propagation process) is performed. If the failure propagation process succeeds, the process proceeds to step 406;
Proceed to 2 to process the next target failure. Step 406
In the following, a process of generating a sequence for transitioning from the initial state of the circuit to the state of the circuit at the time when the failure propagation processing has been completed (hereinafter, referred to as “the series”)
State initialization processing). If the generation of the series succeeds, the process proceeds to step 407. If the generation of the sequence fails, the process proceeds to step 402 to process the next target failure. Here, the initial state may be an arbitrary state, but generally, all FFs of the circuit under test are set to don't care or unknowm.
In this state, it is possible to obtain a test sequence that can execute the fault test regardless of the state of the sequential circuit. In practice, if the state of the circuit at the time when the immediately preceding failure test is completed during the execution of the failure test, the inspection time for performing the failure test continuously can be reduced.

In step 407, a fault simulation is executed using the test sequence of the target fault selected in step 403, and a fault detected at an arbitrary external output pin is determined.
Set the “Detection” column to “1”. The fault detected by this is not always one target fault. This is because, along with the simulation of the target failure, another failure such as a failure on the same path as the target failure is also simulated.

Step 408 indicates the end of the test sequence generation processing of the sequential circuit. FIG. 13 is a flowchart showing the failure propagation processing in step 405 described above. This flow is
The fault propagation process based on the RTP (Reverse Time Processing) method is shown. In the RTP method, a sequential circuit is logically divided into a combinational circuit portion and a flip-flop circuit (hereinafter, FF circuit) portion, and is treated as a circuit developed as a temporal repetition of the combinational circuit portion. In the expanded circuit, the fault propagation process heuristically sets a path from an external output to be a final destination of a target fault to a fault location, and sets an input for the fault signal to propagate along the path. Find the series. At this time, a method of obtaining an input for transmitting a fault signal of a target fault for each circuit unit (hereinafter, a time frame), that is, activating the path is used.

Specifically, in the developed sequential circuit, the following steps are executed for each time frame.
Step 601 indicates the start of the fault propagation process. At step 602, it is determined whether or not the path including the target failure is activated. If the path including the target fault is activated, it is determined that the fault propagation process has succeeded, and the process proceeds to step 605.
The process proceeds to step 603 if not activated.

In step 603, one D frontier is selected from the target fault location or the output of the FF (that is, the input to the combinational circuit) in the target time frame. Further, a fault signal is assigned to the D frontier, and the fault signal is propagated to an arbitrary external output pin or the input of the D frontier selected in the time frame processed immediately before (hereinafter referred to as a target PPO) (that is, the fault signal is transmitted). In order to activate the propagation path), a state value is assigned to the external input pin and the output of the FF. If the fault propagation is successful, the process proceeds to step 604. If the fault is failed, the process proceeds to step 605.
Proceed to.

In step 604, the state value assigned to the external input pin for activating the fault propagation path in step 603 is stored as a test sequence, and the D frontier input is newly set as the target PPO. Step 605 indicates the end of the fault propagation processing. FIG.
FIG. 9 is a diagram showing the state initialization processing in step 406.

In the state initialization processing, contrary to the state transition in the actual failure inspection, a state transition occurs from the state of the circuit at the time when the failure propagation processing is completed (hereinafter, a failure excitation state) toward the initial state. In this process, state values are assigned, state transitions are traced back to the initial state, and an input sequence is obtained based on the state values. Step 5 in FIG.
01 indicates the start of the state initialization processing for test sequence generation of the sequential circuit.

In step 502, it is determined whether or not the current state of the circuit and the initial state match, and if the current state and the initial state match, it is determined that the state initialization has succeeded, and the process proceeds to step 505. If not, step 503
Proceed to. In step 503, a state value is assigned to the external input pin of the circuit and the output of the flip-flop in order to justify the current state. If the current state is justified, the process proceeds to step 504; The process proceeds to step 505 on the assumption that the conversion has failed.

In step 504, the state value assigned to the external input pin for justifying the current state in step 503 is stored as a test sequence, and the state value assigned to the output of the flip-flop, ie, the current state is justified. The set state value is set as the current state, and the process proceeds to step 502. Step 505 indicates the end of the state initialization processing for test sequence generation of the sequential circuit. The operation of the test sequence generation method for a sequential circuit according to the related art configured as described above will be described.

First, in the fault table shown in FIG. 11, one target fault for which a test sequence is to be generated is selected from undetected and unprocessed fault groups (step 40 in FIG. 12).
1-43). Next, since the selected target fault may be a redundant fault or a fault that takes a long time to generate a test input, test input generation is performed on the combinational circuit portion of the circuit under test in order to check the target fault. FIG. 15A is an explanatory diagram of the circuit under test. FIG. 15B shows an example of the circuit. The circuit under test, which is a sequential circuit, can be logically divided into a combinational circuit portion and an FF portion as shown in FIG. Then, the input to the combinational circuit part is an external input pin (hereinafter, referred to as an original input).
Abbreviated as PI. ) And a pseudo input (hereinafter referred to as PPI) output from the FF, and the output of the combinational circuit is an external output pin (hereinafter referred to as PO) which is an original output and a pseudo output (hereinafter referred to as PO) input to the FF. Hereinafter, PPO).

By paying attention to the inputs (PI and PPI) and the outputs (PO and PPO) of the combinational circuit portion, appropriate input values are assigned so that a failure signal of a target failure is propagated to one of the outputs. A test input for the combinational circuit portion is generated (step 404).
As a result, if the generation of the test input is successful, step 40
When the process proceeds to step 5, if the target failure is a redundant failure, "1" is set in the "redundant failure" column of the failure table, and the process proceeds to step 402 to select the next target failure. If the test input generation succeeds, a fault propagation process is performed to generate a test sequence for the target fault (step 405). An explanatory diagram of this fault propagation is shown in FIG.

In FIG. 1, reference numeral 701 denotes a time frame of a sequential circuit to be processed first, 702 denotes a time frame of a sequential circuit to be processed second, and 703 denotes a time frame of a third circuit to be processed. These timeframes are
Dividing the sequential circuit into a combinational circuit part and an FF part,
This corresponds to a combinational circuit portion when time-expanded according to the state transition of the FF. (For reference, the time-expanded result in the case of the circuit example shown in FIG. 15B is shown in FIG. 17.) In FIG. 16, only three time frames are shown for convenience of explanation, but the actual LSI , It is usually necessary to propagate a fairly large number of time frames. A point to be noted in the fault propagation is that the actual operation of the circuit operates in the order of 703 to 701, but the propagation process is performed for each time frame by going back in time from 701 to 703. 704
Is an external output pin of the sequential circuit. Reference numeral 705 denotes a failure signal propagation path in the time frame 701, and reference numeral 706 denotes a failure propagation path in the time frame 702. 707
709 are flip-flops used in the processing of the time frame 701. 710 to 712 are time frames 7
02 is a flip-flop used in the processing of No. 02. Reference numeral 713 denotes a failure location of the target failure a. A description will be given along the flow of the fault propagation processing in FIG. 13 with reference to FIG.

In the first time frame 701, since the path including the target failure 713 cannot be activated yet (step 602 in FIG. 13), the FF as the D frontier
3 (709) is heuristically selected. This FF3
A fault signal is assigned to (709), and a fault propagation path 705 is activated to propagate the signal to the external output pin 704. That is, the external output pin 70 is output from the FF3 (709).
The state value of the external input pin and the state value of the FF are assigned so as to activate the path to 4 (step 603). The state value that has been successfully assigned is stored as a test sequence, and the input of FF3, which is the D frontier, is set as a new target PPO.
The process returns to step 602 (step 604). At this point, since the path including the target failure has not been activated yet, the process proceeds to step 603 (step 602).

Proceeding to the processing of the time frame 702, the FF 3 (709) selected as the D frontier in the processing of the time frame 701 is set as the target PPO, and the FF 3 is found heuristically.
2 (711) is selected as the D frontier, and FF2
In order to allocate a fault signal to (711) and propagate it to the target PPO FF3 (709), the fault propagation path 706 is activated (step 603), and the state value that has been successfully allocated is stored as a test sequence, FF2 is set as a new target PPO (step 604).

In the processing of the time frame 703, the F selected as the D frontier in the time frame 702
Although F2 (711) is set as the target PPO, here, regardless of which D frontier is selected, FF which is the target PPO is selected.
Assume that a failure signal could not be propagated to 2 (711) (step 603). Then, the failure propagation processing for the failure 713 has failed, and the failure propagation processing ends (step 604).

If the failure propagation process fails, the process proceeds to step 402 in FIG. 12 (step 405), and the next new target fault is selected and the process is executed similarly (steps 402 to 405). The above operation example is an example in which the failure propagation processing has failed. However, in step 405 in the time frame 703, when the failure signal has been successfully propagated to the target failure 713, the following is performed.

In this case, the state value assigned to the external input pin in each time frame is generated as a test sequence. However, the state of each FF is a state of the circuit at the time when the failure propagation processing is completed (hereinafter, a failure excitation state). In the above example, the state value has been successfully allocated in the time frame 703. The test sequence generated by the process is a valid test sequence only in the state at the end of the propagation process. Therefore, it is necessary to perform a process for obtaining a sequence for changing the state of the circuit from the initial state to the fault excitation state so that the failure inspection can be performed in a desired initial state. This processing is state initialization processing. The operation of the state initialization processing will be described using an example of the state transition of the circuit under test shown in FIG.

In the figure, reference numerals 801 to 804 denote circuit states, in particular, state 801 is a state of the circuit at the time when the fault propagation processing is completed, that is, a fault excitation state, and state 804 is an initial state. Reference numeral 805 denotes a branch indicating that transition from the state 802 to the state 801 is possible, reference numeral 806 indicates a branch indicating that transition from the state 803 to the state 802 is possible, and reference numeral 807 indicates a branch indicating that transition from the state 801 to the state 803 is possible. , 808 are branches indicating that transition from the state 804 to the state 803 is possible.

At the end of the fault propagation process, the current state is the state 801 (S1), which does not match the initial state (step 502 in FIG. 14), so that the current state is justified, that is, the state is shifted to the current state. Is assigned to the state of the external input and FF. Here, state 802 is set to FF.
It is assumed that the state of (S2) is justified when the state is assigned (step 503). The justified state is newly set as the current state (S2) (step 504).

Similarly, the current state is justified, and the current state is newly set to S3 (steps 502 to 504).
Further, similarly, the current state S3 is justified, but in the case of FIG. 18, the state transition to the current state S3 is S1.
And a transition from S4. If the justified state is S4, the state initialization is successful. In this case, a fault test sequence can be obtained by combining the input sequence obtained in the previous fault propagation process and the input sequence selected in the state initialization process.

On the other hand, if the justified state is S1, the same process as above is repeated again and fails, resulting in a state transition loop, so that the initial state cannot be obtained. After the state initialization process, a fault simulation is performed on the target fault using the obtained test sequence, and it is confirmed that the fault is detected at the external output pin. It is set to “1” (Step 407 in FIG. 12), and the process proceeds to Step 402. Further, the above operation is repeated, and a test sequence generation process is performed for each target failure. Finally, the test sequence generation processing in the case of the circuit example of FIG. 17 will be described. The target fault is the signal line marked with a cross.

(First Time Frame of Propagation Process) Since the activation of the path including the target failure (marked by x) has not been completed (step 602 in FIG. 16), F is set as the D frontier.
It is assumed that the output Y2 of F2 is selected (the first half of step 603). In the combinational circuit portion, a state value for activating the path from the input signal y2 to the external output pin Z is assigned as follows. That is, in order for the failure signal D to be output to the external output pin Z, the two inputs (I, y2) of the AND gate G2 must be (1, D). At this time, the input y1 may be don't care. Therefore, the state value (I, y1, y2) = (1, X, D) is assigned (the latter half of step 603).

This state value (1, X, D) is stored as a part of the test sequence, and a new target PPO is stored in the input Y2 of the FF2.
(Step 604). (Second Time Frame of Propagation Processing) It is assumed that a target failure (x mark) is selected as the D frontier (step 6).
02, 603).

In the combinational circuit portion, a state value for activating the path from the target fault to the target PPO Y2 is assigned as follows. That is, the failure signal D is applied to Y2.
Must be input to the OR gate G3 (output of G1, y1) = (D, 0). In addition, two inputs (I, target fault) of AND gate G1 =
(1, D). Therefore, the state values (I,
(y1, y2) = (1, 0, 0) is assigned (the latter half of step 603).

This state value (1, 0, 0) is stored as a part of the test sequence, and a new target PPO is stored in the input Y1 of the FF1.
(Step 604), the path including the target fault is activated (step 602), and the propagation process ends (step 605). (State initialization processing) Subsequently, state initialization processing is performed. If the initial state is (FF1, FF2) = (0, 0), the state initialization processing is immediately terminated (step 5 in FIG. 14).
02, 505).

Here, the initial state is (FF1, FF2)
= (X, X) That is, the case of don't care will be described. Since the initial state (X, X) does not match the current state (0, 0) (step 502), a state value that justifies the current state is assigned. That is, in order to justify FF1 (Y1 = 0), two inputs (I,
y2) = (0, X). At this time, y2 may be X. Therefore, if I = 0 is assigned as an input value, the state (0, 0) can be justified (step 503).

The input value I = 0 is stored as a part of the test sequence, and the justified state (0, X) is set as the current state (step 504). Since it does not match the initial state (step 502) ), Justify the current state. That is, to justify FF1 (Y1 = 0), AND
The two inputs (I, y1) of the gate G1 may be (0, X),
In order to justify FF2 (Y2 = X), two inputs (output of G1, y1) of the OR gate G3 may be set to (0, X). At this time, y1 may be X. Therefore, if I = 0 is assigned as an input value, the state (0, X) can be justified (step 503).

The input value I = 0 is stored as a part of the test sequence, and the justified state (X, X) is set as the current state (step 504). ), The justification process ends (step 505). As a result, {0011} is obtained as a test sequence to be input to the input signal I.

[0036]

However, according to the test sequence generation method in the prior art described above, the failure propagation process or the state initialization process often fails, and the test sequence cannot be generated in many cases. there were. In other words, if failure occurs in the fault propagation process or the state initialization process, it is not established how to treat the failed fault, such as giving up the generation of the test sequence for the target fault and proceeding to the next target fault. For this reason, the success rate of the test sequence generation, that is, the failure detection rate has not been improved.

[0037] In view of the above problems, an object of the present invention is to provide a fault test sequence generation method and a test sequence generation device capable of obtaining a high fault detection rate.

[0038]

In order to achieve the above object, a test sequence generation method according to the present invention expands a sequential circuit, which is a circuit under test, into a time frame, and performs a test on a assumed stuck-at fault in the sequential circuit. A test sequence generation method for performing a fault propagation process for trying to activate a propagation path of a fault signal of the fault for each time frame and generating a sequence for checking the fault, wherein the fault signal is transmitted in one time frame. A fault that selects a path to be activated, assigns an input value in the time frame so that the path is activated, and performs this processing retroactively in the time frame from the output pin to which the final fault propagates to the fault location In the propagation processing step and in any of the time frames, if the activation failure is detected, the failed time frame from the first time frame An allocation failure detection step of setting at least a part of the routes among the routes in the prohibition information, and a failure propagation processing step so as not to select the route set as the prohibition information when the activation fails. And a re-failure propagation processing step to be executed.

Here, the prohibition information information may be a D frontier representing a signal line to be a failure propagation destination from a time frame of the immediately preceding time selected in a predetermined time frame. The predetermined time frame may be a time frame for activating a fault propagation path first.

[0040] The prohibition information may be a set of a D frontier and a target PPO representing a propagation path in a predetermined time frame. The prohibition information includes a D frontier and a target PPO representing a propagation path in a time frame processed immediately before a time frame in which failure propagation has failed.
May be a set. The test sequence generation method according to claim 1, wherein:

Further, a sequential circuit, which is a circuit under test, is expanded into a time frame, and a fault propagation for trying to activate a propagation path of a fault signal of the fault with respect to an assumed stuck-at fault in the sequential circuit for each time frame. A test sequence generating method for performing a process and generating a sequence for testing the fault,
A first step of counting the number of times the fault propagation process has been performed for all of the target faults, and determining whether the count value has exceeded a predetermined number. And the second step of ending
The first step is a first sub-step of selecting one of target faults whose fault propagation process is unprocessed or simulated as unprocessed and whose test sequence is not yet generated. If the D frontier indicating the input side of the path to be activated is registered as a prohibited D frontier in the time frame for propagating the target fault to the external output pin with respect to the target fault, the D frontier other than the prohibited D frontier is used. And a third sub-step of performing a fault propagation process by selecting the following, a third sub-step of determining whether the fault propagation process has succeeded or failed in the second sub-step, Registering a D frontier selected in a time frame for transmitting the influence of the target failure to an external output pin as a prohibited D frontier of the target failure. And when the first to fourth sub-steps are executed for all the target faults, the fault that failed in the fault propagation processing is assumed to be unprocessed by the fault propagation processing, and the count value is counted. 5
May be composed of the following sub-steps.

Further, a sequential circuit, which is a circuit under test, is expanded into a time frame, and a fault propagation for trying to activate a propagation path of a fault signal of the fault with respect to an assumed stuck-at fault in the sequential circuit for each time frame. A test sequence generating method for performing a process and generating a sequence for testing the fault,
A first step of performing a fault propagation process on one time frame for a certain target failure, and a propagation path selected in a time frame immediately before the time frame to be processed in the first step Is stored as a pair of a signal line indicating the exit side of the route (hereinafter referred to as a target PPO) and a D frontier indicating the entrance side, and whether the failure propagation process in the first step is successful or not is determined. If the judgment is successful, the first step is executed for the next time frame. If the judgment is failed, the combination of the target PPO and the D frontier stored in the second step is registered as a prohibited route. And when the failure propagation processing in the first step fails, at least one time frame before the failed time frame in the already generated test sequence. A fourth step of clearing the generated partial after chromatography beam, D registered as the prohibited path
A fifth step of executing the first step from the corresponding time frame of the cleared portion so as not to select the combination of the frontier and the target PPO may be adopted.

In order to change the state of the sequential circuit, which is the circuit under test, from the initial state to the state at the end of the fault propagation processing for a certain stuck-at fault, an input signal to be given in time series to the input pin of the sequential circuit Is a test sequence generating method for generating a test sequence for testing the fault, and in a sequential circuit, the state of the storage element of the sequential circuit and the state of the storage element of the sequential circuit are justified so as to justify the state at that time. An input signal to be applied to an external input pin, a justification step of executing the processing to obtain an initial state of the sequential circuit from a state of the sequential circuit when the fault propagation processing ends, and A match detection step for determining whether the state matches the state at the end of the fault propagation processing or the state that has already been assigned. And an assignment control step of canceling the assignment of the matched state and the signal given to the external input pin when it is determined that they match, and performing a new justification step avoiding the state. It is characterized by.

Here, in the assignment control step, a new justification step may be executed from the state at the time of completion of the fault propagation processing. Further, in the assignment control step, the justification step may be newly executed from a state before the matched state. Further, in the sequential circuit, which is the circuit under test, a state in which an input signal to be given in time series to the input pin of the sequential circuit in order to transition the state from the initial state to the state at the time of completion of the fault propagation processing for a certain stuck-at fault. A first step of performing an initialization process and generating a test sequence for generating a sequence for testing the failure by a test sequence generation method, the first step of determining whether a current state matches the initial state; A second step of assigning a state value that justifies the state, a third step of storing the justified state as a state transition history, and a state newly stored in the third step is already in the state transition history. A fourth step of determining whether or not the state exists in the second step. If the fourth step determines that the state exists, the state is registered as prohibition information, deleted from the state transition history, and The process may include a fifth step of returning to the first step, and a sixth step of returning to the first state with the justified state as the current state when it is determined in the fourth step that the state does not exist. .

Further, the test sequence generation apparatus of the present invention expands a sequential circuit, which is a circuit under test, into a time frame, and, for each of the assumed stuck-at faults in the sequential circuit, generates a fault signal of the fault for each time frame. A test sequence generator for performing a fault propagation process for activating a propagation path and generating a sequence for testing the fault, wherein the test sequence generator selects a path through which a fault signal is to be transmitted in one time frame, and activates the path. Fault propagation processing means for allocating an input value in the time frame so as to perform the process, going back to the time frame from the output pin, which is the ultimate fault propagation destination, to the fault location; and ,
When the activation failure is detected, at least a part of the routes from the first time frame to the failed time frame is prohibition information, and the prohibition information is associated with the failure. Prohibition information storage means for storing, and when activation fails, prohibition means for prohibiting the selection of the path designated as the prohibition information and newly activating the fault propagation processing means for the fault. It is characterized by having.

Here, the prohibition information information may be a D frontier representing a signal line to be a failure propagation destination from an adjacent time frame selected in a predetermined time frame. The predetermined time frame may be a first time frame. The prohibition information may be a set of a D frontier representing a propagation path in a predetermined time frame and a target PPO.

The prohibition information may be a set of a D frontier and a target PPO representing a propagation path in a time frame processed immediately before a time frame in which failure propagation has failed. Further, in the sequential circuit, which is the circuit under test, a state in which an input signal to be given in time series to the input pin of the sequential circuit in order to transition the state from the initial state to the state at the time of completion of the fault propagation processing for a certain stuck-at fault. A test sequence generating apparatus for performing a initialization process and generating a sequence for testing the fault is a test sequence generating apparatus, and in a sequential circuit, states of storage elements of the sequential circuit and external input pins so as to justify the state at that time. And the justification means for executing the processing to obtain the initial state of the sequential circuit from the state of the sequential circuit when the fault propagation processing ends, the state of the sequential circuit assigned in the means, A coincidence detecting means for judging whether or not the state at the time of the failure propagation processing end or the state which has already been assigned is determined; If it and cancel the assignment of the input signal applied to the matched state and the external input pins, and wherein the providing the allocation control means for executing a new justification means to avoid the condition.

Here, the allocation control means may newly execute the justification means from the state at the time when the failure propagation processing is completed. The assignment control unit may newly execute the justification unit from a state immediately before the matched state.

[0049]

According to the test sequence generation method (apparatus) of the present invention, when the failure propagation processing of the target fault fails in the fault propagation processing step (means), the allocation failure detecting step (means) detects the target failure. At least a part of the route for transmitting the influence is set as the prohibition information. The re-failure propagation processing step (prohibition means) newly performs a failure propagation process for generating a test sequence for the same target fault without selecting the prohibition information for the target fault as a path.

In the state initialization processing, the coincidence detection step (means) determines whether the state transition has fallen into a loop in the justification step (means) (if the same state
Is detected). The assignment control step (means)
The state that caused the loop is set to the prohibited state,
Try again.

[0051]

【Example】

(Embodiment 1) FIG. 1 is an overall flowchart of a method for generating a test sequence of a sequential circuit in an embodiment of the present invention. The faults to be inspected by the test sequence are the same as those described in the section of the related art, and are listed in advance for each signal line based on the netlist of the LSI to be tested and are stored in the fault table. It is registered (see the example of the failure table in FIG. 11).

In FIG. 1, step 101 indicates the start of the processing of the test sequence generation method. In step 102, the maximum number of test sequence generation processes to be executed for an undetected fault in the fault table is set. The number of times should be determined in consideration of the complexity of the circuit to be inspected, the circuit scale, the time allowed for the test sequence generation processing, and the like. In many cases, about five times is appropriate.

In step 103, the number of test sequence generation processes is initialized to zero. In step 104, it is determined whether or not the number of test sequence generation processes does not exceed the maximum number of test sequence generation processes for undetected faults set in step 102, and if not, the process proceeds to step 105, If so, the process proceeds to step 115.

In step 105, it is determined whether or not there is an undetected and unprocessed fault other than the redundant fault in the fault table. If it exists, the process proceeds to step 106; otherwise, the process proceeds to step 113. In steps 106 and 107, one target fault is selected from the undetected and unprocessed fault groups, and only the combinational circuit portion is inspected before the test sequence generation to check whether it is an undetectable fault. Generate input. This corresponds to steps 403 and 404 in FIG.
Is the same as

In step 108, a fault propagation process is performed on the selected target fault. Steps 109 and 11
At 0, state initialization processing and failure simulation are performed. This is the same as steps 406 and 407 in FIG. 12 described in the description of the related art. In step 111, it is determined whether or not the failure propagation processing for test sequence generation processed in step 107 is successful. If the processing is successful, the processing proceeds to step 105;

In step 112, the D frontier selected in the time frame in which the influence of the target fault is propagated to an arbitrary external output pin is registered in the set of prohibited D frontiers of the target fault. FIG. 2 shows an example of registration of a prohibited D frontier set. In the figure, “signal line” indicates a target fault location, “failure” indicates a type of fault, and “D frontier” indicates a D frontier whose selection is prohibited. As shown in the figure, in this embodiment, the prohibited D frontier is registered for each failure.

In step 113, undetected faults other than redundant faults in the fault table are regarded as unprocessed faults. That is,
The “Process” column for a failure in which the “detection” column is 0 and the “redundant failure” is not 1 is set to 0. As a result, the failure for which the test sequence generation has failed is selected again in step 106. In step 114, the number of test sequence generation processes for undetected faults is counted up by one.

Step 115 indicates the end of the processing of the test sequence generation method. FIG. 3 is a diagram showing a more detailed flow of the fault propagation processing in step 108 of FIG. This diagram differs from the flow of the fault propagation process of FIG. 13 described in the prior art only in that steps 1403 to 1405 are added. That is, when the D frontier is selected in the k-th time frame, the one registered in the prohibited D frontier set is not selected. As a result, in the k-th time frame of the second and subsequent fault propagation processes, a component other than the previously failed D frontier is selected.

In FIG. 14, in step 1402, it is determined whether or not the path including the target failure is activated. If activated, the process proceeds to step 1409 assuming that the failure propagation process has succeeded, and if not, the process proceeds to step 1403. In step 1403, it is determined whether the time frame to be processed is the k-th time frame. If the time frame is the k-th time frame, the process proceeds to step 1404; otherwise, the process proceeds to step 1406. However, in this embodiment, k = 1.

In step 1404, the target fault location or the output of the FF (that is, the input of the combinational circuit portion)
One of them is selected as D frontier. that time,
With reference to the set of prohibited D frontiers, a set that is not registered as a prohibited D frontier for the failure is selected. In step 1405, the selected D frontier is temporarily stored.

In step 1406, one D frontier is selected from the target fault location or the output of the FF. This selection method is based on the conventional technique (step 603 in FIG. 13).
The first half). Step 1407 assigns a failure signal to the selected D frontier in the time frame of interest, and assigns the failure signal to any external output pin or the input (target PPO) of the D frontier selected in the immediately preceding processed time frame. To propagate a fault signal (that is, activate a fault propagation path), a state value is assigned to the external input pin and the output of the FF. If the fault propagation is successful, the process proceeds to step 1408; The process proceeds to step 1409 as failure. This path activation is performed according to the conventional technique (step 6 in FIG. 13).
02).

In step 1408, step 1407
In step 1402, the input value assigned to the external input pin for activating the fault propagation path is stored as a part of the test sequence, and the input of D frontier is newly set as the target PPO.
Proceed to. Step 1409 indicates the end of the fault propagation processing. The operation of the test sequence generation method according to the first embodiment of the present invention configured as described above will be described.
FIG. 4 is an explanatory diagram of an operation example of this fault propagation.

In FIG. 4, the same reference numerals as in FIG. 16 used in the description of the prior art are the same as those in FIG.
Reference numeral 1001 denotes a prohibited D frontier set of the target failure 713. 1002 to 1004 are fault propagation paths of the time frames 701, 702, and 703 in the second propagation process, respectively. First, in this embodiment, the maximum number of times to repeat when the propagation process fails is set to 5 (step 102 in FIG. 1), and a variable i for controlling the number of times is set to an initial value 0 (step 102). 103). Next, it is determined whether or not the variable i has reached the maximum number. If it has, the process proceeds to step 112, and if not, the process proceeds to step 10.
Go to step 5 (step 104).

Steps 105 to 107 following this are the same as steps 402 to 404 in FIG. 12 in the prior art, and a description thereof will be omitted. If the test input is successfully generated in step 107, a fault propagation process is performed to generate a test sequence for the target fault (step 10).
8). In the first (when i = 0) fault propagation processing, the fault propagation processing for the target fault 713 is assumed to be performed in the same manner as described with reference to FIG. The operation of the propagation processing itself is almost the same as that of the conventional technique, and only different points will be described. That is, in the first time frame (step 1403), when selecting a D frontier, one other than those registered as prohibited D frontiers is selected. However, since nothing is registered as a prohibited D frontier in the first fault propagation processing, as a result, FF3 is
It will be selected as the frontier (step 1404 in FIG. 3). Further, the selected D frontier is temporarily stored (step 1405).

Proceeding to the second and third time frames,
It is assumed that activation of the propagation path has failed in the third time frame as in the related art. Further, the success or failure of the failure propagation processing is determined (step 111). If the failure propagation processing fails, the D frontier 709 temporarily stored in step 1405 in FIG.
3 is registered in the prohibited D frontier set 1001 (step 112).

Thereafter, the above process is executed for each of the unprocessed faults in the fault table (repeated from steps 105 to 111 or 112). In the example, the D frontier in the time frame of k = 1) is registered as the prohibition D frontier of the failure. When the test sequence generation processing is completed for each unprocessed fault, it is determined that there is no unprocessed fault (step 105).
In the failure table, the "detection" column is set to 0, and the "processing" column of a failure whose "redundant failure" is not 1 is set to 0 (step 113). This allows the failed fault to be selected again. The variable i indicating the number of repetitions of the test sequence generation processing is counted up by one (step 114), and the process proceeds to step 105.

In the second (when i = 2) fault propagation processing, the fault 713 which failed when i = 1 is selected again as the target fault (step 106), and the test input generation of the combinational circuit (step 107) ), The fault propagation processing is performed as follows. Time frame 701 in FIG.
In the processing of (1), since this is the first time frame (step 1403), by referring to the forbidden D frontier set 1001 and not selecting the element FF3 (709) as the D frontier, FF1 (707) becomes the D frontier Heuristically selected (step 14
04), is temporarily stored (step 1405), activates the fault propagation path 1002 to the external output pin 704 (step 1407), and sets FF1 (707) to the target PPO.
(Step 1408).

In the second time frame 702,
FF3 (712) is selected as the D frontier (steps 1403 and 1406), and the effect of the failure is determined by FF3 (71).
In order to propagate from 2) to the target PPO FF1 (707), the fault propagation path 1003 is activated (step 1407), and FF3 (712) is set as the target PPO (step 1408).

In the third time frame 703,
The failure location 713 is selected as the D frontier (steps 1403 and 1406), and the effect of the failure is determined by the failure location 713.
To activate the fault propagation path 1004 in order to propagate the target PPO to FF3 (712) (step 1).
407). Here, since the target failure is activated (step 1402), the process proceeds to the state initialization processing in which the propagation processing is successful.

The subsequent state initialization processing is the same as that described in the prior art, and will not be described. As mentioned above,
According to the present embodiment, if the fault propagation process fails as a result of generating a test sequence for a certain target fault, the k-th time frame (in the embodiment, k = 1, that is, the effect of the target fault is determined by the external output pin) Register the D frontier selected in the time frame to be propagated to the prohibited D frontier set,
In addition, by generating a test sequence for a failed target failure again, when the test sequence for the target failure is generated again, the target frame is prohibited from being transmitted in a time frame that propagates the influence of the target failure to an external output pin. By not selecting a signal line belonging to the D frontier as the D frontier and dynamically changing the fault propagation path,
Since the probability of successful generation of the test sequence for the target fault increases, it is possible to generate a test sequence that can obtain a high fault detection rate. (Embodiment 2) FIG. 5 is a diagram showing a fault propagation process of a test sequence generation method for a sequential circuit according to a second embodiment of the present invention. The entire flow of the test sequence generation method is almost the same as that of FIG. 12 used in the description of the related art, except that the fault propagation process 405 of FIG. 12 is the flow of FIG.
Hereinafter, only the fault propagation process will be described.

In FIG. 5, step 301 indicates the start of the fault propagation processing according to the present invention. In step 302, it is determined whether or not the target fault is activated. If the target fault is activated, the process proceeds to step 308, and if not, the process proceeds to step 303. In step 303, one of the target fault and the output of the flip-flop is selected as the D frontier, and the input of the external output pin or the flip-flop selected as the D frontier in the immediately preceding time frame (target PPO) Generate a test input for transmitting a fault signal to the test signal. If this process fails, the process proceeds to step 306, and if successful, the process proceeds to step 304. However, the combination of the D frontier and the target PPO belonging to the prohibited combination set is not selected.

In step 304, the pair of the target PPO and the D frontier is temporarily stored. In step 305, if the D frontier selected in step 303 is a flip-flop, its input is set as the target PPO. In step 306, the combination of the D frontier and the target PPO stored in step 304 is added to the prohibited combination set. FIG. 6 shows an example of a prohibited combination set. In the figure, “signal line” indicates a target fault location, “fault” indicates a fault type, and “D frontier” and “target PP”.
A set of “O” indicates a prohibited route.

In step 307, all test sequences generated halfway are cleared, and the flow advances to step 302. A step 308 clears the prohibited combination set and ends the fault propagation processing. The operation of the fault propagation process of the test sequence generation method for a sequential circuit according to the third embodiment of the present invention configured as described above will be described.

FIG. 7 is a diagram used to explain the operation of the fault propagation processing. In this figure, the same components as those in FIG. 16 used in the description of the related art have the same reference numerals. 1
Reference numeral 201 denotes a prohibited combination set shown in FIG. 1202
Is a fault propagation path of the time frame 702, and 1203 is a fault propagation path of the time frame 703. Target failure 7
13, as described with reference to FIG. 16 in the description of the related art, it is assumed that the failure propagation of the time frame 703 has failed and the generation of the test sequence has failed (step 303 in FIG. 5). . Here, as shown in FIG. 7, when the failure propagation process fails, the output of FF2 (711), which is the D frontier of the time frame 702 immediately before the failed time frame 703, and the target PP
The combination with the input of FF3 (709) which is O is registered in the prohibited combination set 1201 (step 306).

Next, returning to the first time frame 701 for clearing all the sequences generated for the target fault 713 and performing the fault propagation process again (step 307), the D frontier 709 is selected in the time frame 701. ,
In order to propagate the effect of the target fault b (713) to the external output pin, the fault propagation path 705 is activated (step 30).
2, 303), the combination of the D frontier 709 and the external output pin PO, which represents the fault propagation path 705, is temporarily stored (step 304), and the input of the D frontier is set as the next target PPO (step 305).

In the time frame 702, elements of the prohibited combination set 1201 (D frontier 711, target PPO7
09), since the target PPO is now 709, F
As a result of not selecting F2 (711) as the D frontier, FF1 (710) is selected as the D frontier and activates the fault propagation path 1202 to the target PPO FF3 (709) (steps 302 to 3).
05).

Next, the processing of the time frame 703 is performed, the fault location 713 is selected as the D frontier, and the effect of the fault is determined from 713 by the FF1 (71) which is the target PPO.
The fault propagation path 1203 is activated for propagation to 0) (steps 302 to 305). Here, since the target fault is activated, the fault propagation process is successful, and the process proceeds to the state initialization process (step 302).

In step 307, all the test sequences generated so far are cleared, and the propagation process is executed again from the first time frame. However, the present invention is not limited to this. Since the path of the time frame processed immediately before is prohibited, the processing of the time frame processed immediately before the failed time frame may be executed again.

As described above, according to the present embodiment, if the failure propagation processing fails as a result of the generation of a test sequence for a certain target failure, the D frontier of the time frame immediately before the failed time frame is compared with the D frontier of the failed time frame. By registering a combination of target PPOs in a prohibited combination set, clearing all or a part of the generated sequence, and performing fault propagation processing again, it belongs to the prohibited combination set in a certain time frame process. By not selecting a combination and dynamically changing the fault propagation path, the probability of successful generation of a test sequence for a target fault increases, so that a test sequence that can obtain a high fault detection rate can be generated. it can. (Embodiment 3) FIG. 8 is a diagram showing a state initialization process of a test sequence generation method for a sequential circuit according to a third embodiment of the present invention. The entire flow of the test sequence generation method is almost the same as that of FIG. 12 shown in the related art, except for the state initialization processing. Hereinafter, only the state initialization process will be described.

In FIG. 8, step 201 indicates the start of the state initialization processing according to the present invention. In step 202, it is determined whether or not the current state and the initial state of the circuit match, and if the current state and the initial state match, the process proceeds to step 208, and if not, the process proceeds to step 203.

In step 203, the current state is justified by assigning values to the external input pins and flip-flops so that the state does not belong to the prohibited state set registered in step 206. In step 204, the state justified in step 203 is added to the state transition history. The history of the state transition is, for example, a history table shown in FIG. As shown in the figure, each state can be represented by a state name for identifying the state and a state value of each FF constituting the state.

In step 205, it is determined whether or not two states justified in step 203 exist in the history of state transition. If there are two states, the process proceeds to step 206.
If not, the process proceeds to step 207. Step 20
In step 6, the state justified in step 203 is deleted from the state transition history, and the state is registered in the prohibited state set.
If two identical states exist in the state transition history,
Since a state transition loop is formed, a state that has been justified later is set as a prohibited state, thereby making it possible to prevent the state initialization processing from falling into a loop.

In step 207, the state justified in step 203 is newly set as the current state. Step 208
Then, the prohibited state set is deleted. Step 209 indicates the end of the state initialization processing according to the present invention. The operation of the state initialization process of the test sequence generation method for a sequential circuit according to the third embodiment of the present invention configured as described above will be described.

FIG. 10 is a diagram used to explain the operation of the state initialization processing of test sequence generation of a sequential circuit in the second embodiment of the present invention. In FIG. 10, reference numeral 1101 in FIG. 10A represents a history of state transitions when two identical states exist during the state initialization processing of the circuit under test having the state transitions shown in FIG. 1102 in FIG.
Represents the history of state transition when the state assigned later is deleted from the two same states existing from.

Reference numeral 1103 in FIG. 5C indicates the history of the state transition when the state initialization processing of the circuit under test having the state transition shown in FIG. 18 is completed successfully. In FIG. 18 illustrating the operation of the state initialization processing in the related art, a sequence that transitions from the initial state 804 to the failure excited state 801 is generated as follows.

First, the fault excited state 801 is registered in the state transition history (step 201). Next, the failure excitation state 80
As a result of justifying 1, a state 802 is obtained (step 20).
3), register it in the history of state transition (step 204).
Since the state 802 is not the initial state and two identical states do not exist in the state transition history (step 205), the justified state is set as the current state (step 207), and the state 8
02 is justified (steps 202 and 203). Similarly, the states 803 and 801 are justified and registered in the state transition history.

Since two states 801 exist in the state transition history 1101 at this time (step 205, FIG. 1).
0 (a)), the state 801 is deleted from the state transition history 1101, and the state 801 is registered in the prohibited state set (step 206, FIG. 10 (b)). As a result of justifying the state 803 so as not to be the prohibited state 801 again (step 203), the state 804 is obtained and registered in the state transition history (step 204, FIG. 5C). Here, there are no two identical states in the state transition history 1103 (step 205). Further, since the state 804 is equal to the initial state (step 202), the state initialization is successful, and the process ends. As described above, according to the present embodiment, the history of the state transition is stored when performing the state initialization processing of the test sequence generation for a certain target failure, and two or more identical states exist in the history of the state transition. In this case, by deleting the state from the state transition history, registering the state as a prohibited state, and performing a state initialization process so as not to become the prohibited state again,
Since the probability of successful state initialization increases and the test sequence can be successfully generated, it is possible to generate a test sequence that can obtain a high failure detection rate.

[0088]

As described above, according to the test sequence generation method (apparatus) of the present invention, when the failure propagation processing of the target fault fails, at least a part of the path for propagating the influence of the target fault. Is stored as prohibition information. The prohibition information for the target fault is not newly selected as a path, and a fault propagation process for generating a test sequence for the same target fault is performed. This has the effect of improving the probability of successful failure propagation processing and, consequently, the failure detection rate.

Further, in the state initialization processing, it is detected whether or not the state transition has fallen into a loop (whether there are two same states), and the state that caused the formation of the loop is set as the prohibited state, and the processing is repeated again. This has the effect of improving the probability of successful state initialization and, consequently, the failure detection rate.

[Brief description of the drawings]

FIG. 1 is a flowchart of a test sequence generation method for a sequential circuit according to a first embodiment of the present invention.

FIG. 2 is a table showing a prohibited D frontier set in the first embodiment of the present invention.

FIG. 3 is a flowchart of a fault propagation processing part of the test sequence generation method according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of an operation of a fault propagation processing part of the test sequence generation method according to the first embodiment of the present invention.

FIG. 5 is a flowchart of a fault propagation processing part of a method for generating a test sequence of a sequential circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a prohibited combination set according to the second embodiment of the present invention.

FIG. 7 is an explanatory diagram of an operation of a fault propagation processing part of the test sequence generation method according to the second embodiment of the present invention.

FIG. 8 is a flowchart of a state initialization portion of a test sequence generation method for a sequential circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a history of state transitions according to a third embodiment of the present invention.

FIG. 10 is an explanatory diagram of an operation of a state initialization portion of a method for generating a test sequence of a sequential circuit according to a third embodiment of the present invention.

FIG. 11 is a failure table in an example of a circuit under test.

FIG. 12 is a flowchart of a conventional test circuit generation method for a sequential circuit.

FIG. 13 is a flowchart of a fault propagation portion of a conventional test sequence generation method for a sequential circuit based on the RTP (Reverse Time Processing) method.

FIG. 14 is a flowchart of a state initialization portion of a conventional method for generating a test sequence of a sequential circuit.

15A is a diagram illustrating a combinational circuit portion and a flip-flop portion in a sequential circuit. FIG. 15B is a simple circuit example in FIG.

FIG. 16 is an explanatory diagram of an operation of a fault propagation portion in a conventional test sequence generation method for a sequential circuit.

FIG. 17 shows an example of test sequence generation in the circuit example of FIG. 15B.

FIG. 18 is an explanatory diagram of an example of a state transition in a state initialization process.

[Explanation of symbols]

102 A process for setting the maximum number of test sequence generation processes to be executed for an undetected fault in the fault table. 103 Processing for initializing the number of test sequence generation processing to zero. 104 Processing to judge whether the number of test sequence generation processing does not exceed the maximum number. 105 A process of determining whether or not there is an undetected and unprocessed fault in the fault table. 106, 107 One target fault is selected from the undetected and unprocessed fault groups, and a test input is generated only for the combinational circuit portion in order to check whether it is an undetectable fault before the test sequence generation. Processing to do. 108 Processing for performing a fault propagation process on the selected target fault. 109, 110 State initialization processing, processing for performing failure simulation. 111 A process of determining whether or not the failure propagation process of test sequence generation processed in step 107 is successful. 112 A process of registering a D frontier selected in a time frame that propagates the influence of a target failure to an arbitrary external output pin in a set of prohibited D frontiers of the target failure. 113 A process in which undetected faults other than redundant faults are set as unprocessed faults in the fault table. 114 A process of counting up the number of test sequence generation processes for an undetected fault by one. 115 Processing indicating the end of the processing of the test sequence generation method. 1402 Processing for determining whether a path including a target failure is activated. 1403 Processing for determining whether the time frame to be processed is the k-th time frame. 1404 Other than the prohibited D frontier,
Alternatively, a process of selecting one of the outputs of the FF (that is, the input of the combinational circuit portion) as one D frontier. 1405 Processing for temporarily storing the selected D frontier. 1406 Target failure location or 1 out of FF output
The process of selecting one D frontier. 1407 Processing for activating a fault propagation path in a target time frame. 1408 The state value assigned to the external input pin for activating the fault propagation path is stored as a part of the test sequence,
The process of setting the frontier input as a new target PPO. 1409 Processing indicating the end of the failure propagation processing. 203 so as not to belong to the prohibited state set,
A process of justifying the current state by assigning values to external input pins and flip-flops 204 A process of adding a state that justifies the current state to the history of state transition 205 A process of justifying the current state during the history of state transition Processing for determining whether or not two states exist 206 Processing for deleting the state and registering it in the prohibited state set when two identical states exist in the history of state transition 208 Processing for deleting the prohibited state set 302: Processing for determining whether or not a target failure is activated. 303 As the D frontier, any one of the target fault and the output of the flip-flop is selected, and an arbitrary external output pin or the input (target PP) of the flip-flop selected as the D frontier in the previous time frame is selected.
O) a process of generating a test input for transmitting a fault signal to
However, a process in which a combination of the D frontier and the target PPO belonging to the prohibited combination set is not selected. 304 Processing for temporarily storing a pair of a target PPO and a D frontier. 305 Processing to set the input side of the flip-flop whose output side is the D frontier as the target PPO. 306 Processing for adding the stored combination of the D frontier and the target PPO to the prohibited combination set. 307 Processing for clearing all test sequences generated halfway. 308 Processing to clear the prohibited combination set and end the fault propagation processing.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁶ , DB name) G01R 31/3183 G06F 11/22 310 G06F 11/263

Claims (19)

(57) [Claims] 1. A fault propagation for expanding a sequential circuit, which is a circuit under test, into a time frame and attempting to activate a propagation path of a fault signal of the fault for each assumed time of a stuck-at fault in the sequential circuit. A test sequence generation method for performing a process and generating a sequence for testing the fault, comprising selecting a path through which a fault signal is to be transmitted in one time frame, and inputting a value in the time frame such that the path is activated. And a failure propagation processing step in which this processing is performed retroactively in the time frame from the output pin that is the ultimate failure propagation destination to the failure location, and when activation failure is detected in any of the time frames , Allocation failure detection in which at least a part of routes from the first time frame to the failed time frame is prohibited information And a re-failure propagation processing step for newly executing a failure propagation processing step so as not to select a path set as prohibition information when activation fails. . 2. The method according to claim 1, wherein the prohibition information is a D frontier representing a signal line to be a failure propagation destination from a time frame of a previous time selected in a predetermined time frame. Item 2. The test sequence generation method according to Item 1. 3. The test sequence generation method according to claim 2, wherein the predetermined time frame is a time frame for activating a fault propagation path first. 4. The prohibition information includes a D frontier and a target PPO representing a propagation path in a predetermined time frame.
2. The test sequence generation method according to claim 1, wherein 5. The prohibition information is a set of a D frontier and a target PPO representing a propagation path in a time frame processed immediately before a time frame in which failure propagation has failed. The described test sequence generation method. 6. A fault propagation which expands a sequential circuit, which is a circuit under test, into a time frame and tries to activate a propagation path of a fault signal of the fault with respect to an assumed stuck-at fault in the sequential circuit for each time frame. A test sequence generating method for performing a process and generating a sequence for testing the fault, wherein a first step of counting the number of times the fault propagation process has been performed on all of the target faults, and the count value is: A second step of determining whether a predetermined number of times has been exceeded and, if so, terminating the generation of the test sequence; A first sub-step of selecting one of the target faults for which the test sequence has not been generated and for which a test sequence has not yet been generated; and a time-lag for transmitting the target fault to the external output pin with respect to the selected target fault. In the case where the D frontier indicating the input side of the path to be activated is registered as a prohibited D frontier, the second sub-step of selecting a D frontier from the other than the prohibited D frontier and performing a fault propagation process A third sub-step for determining whether the failure propagation processing has succeeded or failed in the second sub-step; and a time frame for transmitting the influence of the target failure to an external output pin when it is determined that the failure has failed. A fourth sub-step of registering the D frontier selected in the above as the target front-end prohibition D frontier, and a fault that fails in the fault propagation process when the first to fourth sub-steps are executed for all target faults. A fifth sub-step of simulating the failure propagation processing as unprocessed and counting the count value. Test sequence generation how to. 7. A fault propagation which expands a sequential circuit, which is a circuit under test, into a time frame and tries to activate a propagation path of a fault signal of the fault with respect to an assumed stuck-at fault in the sequential circuit for each time frame. A test sequence generation method for performing a process and generating a sequence for testing the fault, comprising: a first step of performing a fault propagation process on one time frame for a certain target fault; The propagation path selected in the time frame immediately before the time frame to be processed is stored as a pair of a signal line (hereinafter a target PPO) indicating the exit side of the path and a D frontier indicating the entrance side. It is determined whether or not the failure propagation processing in the second step and the first step has succeeded. If the failure propagation processing has succeeded, the first step is executed for the next time frame. In this case, the third step of registering the combination of the target PPO and the D frontier stored in the second step as a forbidden route, and the failure propagation processing in the first step, which has already been generated, A fourth step of clearing a portion of the test sequence generated at least one time frame before the failed time frame, and a D frontier and a target P registered as the prohibited route.
A fifth step of executing the first step from a time frame corresponding to the cleared portion so as not to select a combination of POs. 8. An input signal to be time-sequentially applied to an input pin of a sequential circuit as a circuit under test in order to make a transition from an initial state to a state at the time of completion of a fault propagation process for a certain stuck-at fault. Is a test sequence generation method for performing a status initialization process to obtain a sequence for testing the fault, and in the sequential circuit, the state of the storage element of the sequential circuit and the state of the storage element of the sequential circuit so as to justify the state at that time. An input signal to be applied to an external input pin, a justification step of executing the processing to obtain an initial state of the sequential circuit from a state of the sequential circuit when the fault propagation processing ends, and A match detection step of determining whether the state matches the state at the time of the failure propagation processing end, or the state already assigned once; If it is determined that they match, the assignment of the matching state and the input signal given to the external input pin is canceled,
A test sequence generation method, comprising: an assignment control step of newly executing a justification step while avoiding the state. 9. The test sequence generation method according to claim 8, wherein the allocation control step newly executes a justification step from a state at the time when the failure propagation processing is completed. 10. The test sequence generation method according to claim 8, wherein the assignment control step newly executes a justification step from a state immediately before the matched state. 11. A sequential circuit which is a circuit under test,
In order to transition the state from the initial state to the state at the end of the fault propagation processing for a certain stuck-at fault, a state initialization processing for obtaining an input signal to be given in time series to the input pin of the sequential circuit is performed, and the fault is inspected. A test sequence generation method for a test sequence for generating a sequence, wherein it is determined whether a current state matches an initial state,
A first step of ending if they match, a second step of allocating a state value justifying the current state and an input signal given to an external input pin if they do not match, and a justified state As a state transition history, a fourth step of determining whether or not the state newly stored in the third step already exists in the state transition history, a fourth step If it is determined that the information does not exist, the state is registered as prohibition information, the fifth step is deleted from the history of state transition and returns to the second step, and if it is determined that the information does not exist in the fourth step, A test sequence generation method, comprising: setting the justified state as the current state and returning to the first state. 12. A fault propagation which expands a sequential circuit which is a circuit under test into a time frame and attempts to activate a propagation path of a fault signal of the fault with respect to an assumed stuck-at fault in the sequential circuit for each time frame. What is claimed is: 1. A test sequence generation device for performing a process and generating a sequence for testing said fault, comprising: selecting a path through which a fault signal is to be transmitted in one time frame; and inputting values in said time frame such that said path is activated. Failure propagation processing means that performs this processing by going back in time frame from the output pin that is the ultimate failure propagation destination to the failure location, and when activation failure is detected in any of the time frames Failure detection means for setting at least a part of routes from the first time frame to the failed time frame as prohibition information. A prohibition information storage unit for storing the prohibition information in association with the failure; and, when activation fails, prohibiting the selection of the path designated as the prohibition information, and providing a new failure for the failure. A test sequence generation device comprising: a prohibition unit that activates a propagation processing unit. 13. The apparatus according to claim 12, wherein the prohibition information is a D frontier representing a signal line to be a failure propagation destination from an adjacent time frame selected in a predetermined time frame. Test sequence generator. 14. The test sequence generating apparatus according to claim 13, wherein the predetermined time frame is a first time frame. 15. The prohibition information includes a D frontier representing a propagation path in a predetermined time frame and a target PPO.
13. The test sequence generation apparatus according to claim 12, wherein 16. The method according to claim 12, wherein the prohibition information is a set of a D frontier representing a propagation path in a time frame processed immediately before a time frame in which failure propagation has failed, and a target PPO. Test sequence generator. 17. A sequential circuit which is a circuit under test,
In order to transition the state from the initial state to the state at the end of the fault propagation processing for a certain stuck-at fault, a state initialization processing for obtaining an input signal to be given in time series to the input pin of the sequential circuit is performed, and the fault is inspected. A test sequence generation apparatus for generating a test sequence for generating a sequence, in a sequential circuit, allocating a state of a storage element of the sequential circuit and an input signal given to an external input pin so as to justify a state at that time, and Justification means for executing to obtain the initial state of the sequential circuit from the state of the sequential circuit at the time when the fault propagation processing is completed, and the state of the sequential circuit assigned by the means is the state at the time of the failure propagation processing end, or already once A match detecting means for determining whether or not the state matches the assigned state; and Cancel the assignment with the input signal
A test sequence generation device comprising: an assignment control unit that newly executes a justification unit while avoiding the state. 18. The test sequence generation apparatus according to claim 17, wherein said assignment control means newly executes the justification means from the state at the time when the failure propagation processing is completed. 19. The test sequence generation apparatus according to claim 17, wherein said assignment control means newly executes the justification means from a state immediately before the matched state.