JPH0611543A - Method and device for generating inspection sequence - Google Patents

Abstract

PURPOSE:To obtain a method for generating a sequence to inspect a sequential circuit for obtaining a highly fault detection rate. CONSTITUTION:In a step 104, it is judged whether the inspection sequence generation processing count for a non-detected fault exceeds the maximum inspection sequence generation processing count for the non-detected fault which is set in a step 102 or not. In a step 108, the fault propagation processing for an inspection sequence generation is performed so that a signal line existing inside a prohibition D frontier aggregate of a target fault which is registered in a step 112 is not selected as the D frontier within a time frame for propagating the target fault to an external output pin. When the fault propagation processing of the inspection sequence generation fails, the D frontier which is selected within a specific time frame is registered to the prohibition D frontier aggregate of the target fault in the step 112, thus modifying a fault propagation path dynamically, increasing probability for succeeding in the inspection sequence generation, and generating the inspection sequence for obtaining a high fault detection rate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test sequence generation method and a test sequence generation device for generating a test sequence used for fault inspection of a digital circuit.

[0002]

2. Description of the Related Art In recent years, digital circuits have been greatly developed into LSIs, and have come to be used in all fields.
Since the LSI cannot directly observe the internal signal, the LS
Along with the increase in the scale of I, the technology related to the failure inspection at the inspection stage has become important.

Regarding the fault inspection of digital circuits, various methods have been proposed for automatically generating a test sequence for detecting a fault in advance. In general, the presence or absence of a failure is determined by adding an appropriate input sequence to the input terminal of the circuit under test and comparing the result obtained from the output terminal with the expected result. The input sequence used for this is the test sequence. This inspection sequence is generated so that it can be inspected for each fault assumed in advance.

The conventional test sequence generation method is the PRENTI
CE-HALL, Anglewood Cliff, N
"FAULT TOLERAN" issued by ew Jersey
T COMPUTING Theory and Tech
1.4.2 "Stack at Fault Testi" of Chapter 1 of "niques Volume I"
ng "and materials from the 1991 European Design Automation Conference [T. Nier
mann and J.M. H. Patel, "HITEC:
A TEST GENERATION PACKAGE
FOR SEQUENTIAL CIRCUIT
S, “1991], etc. The above-mentioned conventional test sequence generation method will be described below.

As a premise of generation of a test sequence, a fault to be inspected is a fault assumed on the basis of a circuit to be inspected and is a modeled one. Specifically, it is a stuck-at fault. That is, it is a fault in which the signal line of the circuit has a value fixed to logic 0 or 1, and there are a stuck-at-0 fault and a stuck-at-1 fault. These stuck-at faults are listed in advance for each signal line based on the netlist of the LSI to be tested and registered in the fault table. An example of this failure table is shown in FIG.
Shown in 1. In the figure, “signal line” indicates each signal line existing in the circuit under test, “fault” indicates 0 stuck-at fault (sa-0) or 1 stuck-at fault (sa-1), and “detection” indicates “1”. “Processed” has been processed with “1”, that is, that the test sequence has been successfully generated for the fault, or that the fault can be detected by a test sequence that detects another fault. That is, the fact that the generation process (regardless of whether the process is successful or unsuccessful) is executed as a target of the inspection sequence generation process is executed and the "redundant fault" is "1" and the fault is a redundant fault, that is, Each indicates an undetectable failure. For example, for the sa-0 fault of the signal line a in the same figure, the test sequence generation processing is executed, and as a result, it is found that it is not a redundant fault, and it further indicates that the test sequence has been successfully generated. Further, the sa-1 fault of the signal line c indicates that the inspection sequence generation processing has been executed, and that it is not a redundant fault, indicating that the inspection sequence generation has failed. FIG. 12 is a diagram showing a conventional test sequence generation method for a sequential circuit.

In the figure, step 401 shows the start of the test sequence generation process of the sequential circuit. In step 402,
Referring to the failure table, a test sequence other than the redundant fault has not been generated (“Detection” column is 0, hereinafter referred to as undetected fault), and the process of generating the test sequence is still being executed. It is determined whether or not there is a failure (the “processing” column is 0, which will be referred to as an unprocessed failure hereinafter). If there is, the procedure proceeds to step 403.

In step 403, one fault (hereinafter, referred to as a target fault) to be the target of test sequence generation is selected from the undetected and unprocessed fault group. At this time, the "processing" column of the failure table corresponding to this target failure is set to "1". In step 404, as a pre-stage of generating a test sequence of a sequential circuit, first, only the combinational circuit portion is targeted,
By generating a test input for the target fault, it is determined whether or not the fault is a logically undetectable fault (hereinafter, redundant fault). As a result, when the target failure is a redundant failure, the corresponding “redundant failure” in the failure table is set to “1” and the process proceeds to step 402. By this step, undetectable faults can be filtered out in advance before generation of the inspection sequence.

In step 405, with respect to the target fault selected in step 403, a process for generating a sequence for propagating the effect of the target fault from the fault location to an arbitrary external output pin (hereinafter, fault propagation process) is performed. If the failure propagation process succeeds, the process proceeds to step 406, and if the failure propagation process fails, the process proceeds to step 40.
Proceed to 2 to process the next target failure. Step 406
Then, the process of generating a sequence that transitions from the initial state of the circuit to the state of the circuit at the time when the failure propagation processing ends (hereinafter,
State initialization processing). If the generation of the series is successful, the process proceeds to step 407, and if it fails, the process proceeds to step 402 to process the next target failure. Here, the initial state may be an arbitrary state, but generally, all FFs of the circuit under test are don't care or unknowm.
With such a state, it is possible to obtain a test series capable of executing a failure test regardless of the state of the sequential circuit. In practice, if the state of the circuit at the time of completion of the previous failure inspection at the time of execution of the failure inspection is set, the inspection time for continuously executing the failure inspection can be shortened.

In step 407, a fault simulation is executed with the target fault inspection sequence selected in step 403, and the fault detected at any external output pin is
Set the "Detection" column to "1". The failure detected by this is not limited to one target failure. This is because, along with the simulation of the target failure, other failures such as a failure on the same route as the target failure will be simulated.

Step 408 shows the end of the test sequence generation process of the sequential circuit. FIG. 13 is a flow chart showing the failure propagation processing in step 405. This flow is
The fault propagation processing based on RTP (Reverse Time Processing) method is shown. In the RTP method, a sequential circuit is logically divided into a combinational circuit portion and a flip-flop circuit (hereinafter referred to as FF circuit) portion, and is treated as a circuit developed as a temporal repetition of the combinational circuit portion. In the expanded circuit, the fault propagation processing heuristically sets a route from the external output that should be the final destination of the target fault to the fault location, and inputs the route for the fault signal to propagate. Find the series. At this time, this is a method of obtaining an input for propagating a fault signal of a target fault, that is, activating the path for each circuit unit (hereinafter, time frame).

Specifically, in the expanded sequential circuit, the following steps are executed for each time frame.
Step 601 indicates the start of failure propagation processing. In step 602, it is determined whether the route including the target failure is activated. If the route including the target fault is activated, it is determined that the fault propagation processing has succeeded and step 605 is performed.
Go to step 603. If not activated, go to step 603.

In step 603, one D frontier is selected from the target failure location or the output of the FF (that is, the input to the combinational circuit portion) in the target time frame. Further, a failure signal is assigned to the D frontier, and the failure signal is propagated to any external output pin or the input of the selected D frontier (hereinafter referred to as a target PPO) in the previously processed time frame (that is, the failure signal is transmitted). In order to activate the propagation path), a state value is assigned to the external input pin and the output of the FF, and if the failure propagation is successful, the process proceeds to step 604.
Go to.

In step 604, the state value assigned to the external input pin for activating the fault propagation path in step 603 is stored as a test sequence, the input of the D frontier is newly set as the target PPO, and the process proceeds to step 602. In step 605, the end of the failure propagation processing is shown. 14
FIG. 8 is a diagram showing a state initialization process in step 406.

Contrary to the state transition in the actual fault inspection, the state initialization process causes a state transition from the state of the circuit at the time of completion of the fault propagation process (hereinafter, fault excited state) toward the initial state. In this process, state values are assigned, state transitions are traced back to the initial state, and an input sequence is obtained based on the state values. Step 5 in the figure
01 indicates the start of the state initialization process for generating the check sequence of the sequential circuit.

In step 502, it is judged whether or not the current state and the initial state of the circuit match. If the current state and the initial state match, it is determined that the state initialization has succeeded, and the process proceeds to step 505, where they match. If not, step 503
Go to. In step 503, a state value is assigned to the external input pin of the circuit and the output of the flip-flop to justify the current state. If the current state is successfully justified, the process proceeds to step 504, and if it fails, the state is initialized. Since the conversion has failed, the process proceeds to step 505.

In step 504, the state value assigned to the external input pin in order to justify the current state in step 503 is stored as a check sequence, and the state value assigned to the output of the flip-flop, that is, the current state is justified. The set state value is set as the current state, and the process proceeds to step 502. Step 505 shows the end of the state initialization process of the test sequence generation of the sequential circuit. The operation of the conventional test sequence generation method of the sequential circuit configured as described above will be described.

First, in the failure table shown in FIG. 11, one target failure to be the target of test sequence generation is selected from undetected and unprocessed failure groups (step 40 in FIG. 12).
1-403). Next, since the selected target fault may be a redundant fault or a fault that takes a long time to generate the test input, in order to check it, the test input generation is executed for the combinational circuit portion of the circuit under test. An explanatory view of the circuit under test is shown in FIG. An example of the circuit is shown in FIG. The circuit to be inspected, which is a sequential circuit, can be logically divided into a combinational circuit portion and an FF portion as shown in FIG. Then, the input to the combinational circuit part is the external input pin (hereinafter,
Abbreviated as PI. ) And a pseudo input (hereinafter, PPI) output from the FF, and the output of the combinational circuit is an external output pin (hereinafter, PO) which is the original output and a pseudo output (hereinafter, PIO) input to the FF. Hereinafter, it is considered to consist of PPO).

By paying attention to the inputs (PI and PPI) and outputs (PO and PPO) of this combinational circuit part, by assigning appropriate input values so that the fault signal of the target fault is propagated to either of the outputs. , A test input for the combinational circuit portion is generated (step 404).
As a result, if the inspection input generation is successful, step 40
If the target failure is a redundant failure, the process proceeds to step 5, and "1" is set in the "redundant failure" column of the failure table, and the process proceeds to step 402 to select the next target failure. If the test input generation is successful, a fault propagation process is performed to generate a test sequence for the target fault (step 405). An explanatory diagram of this fault propagation is shown in FIG.

In the figure, 701 is a time frame of a sequential circuit to be processed first, 702 is a time frame of a sequential circuit to be processed second, and 703 is a time frame to be processed third. These timeframes are
The sequential circuit is divided into a combinational circuit part and an FF part,
It corresponds to the combinational circuit portion when the time expansion is performed according to the state transition of the FF. (For reference, the time-expanded result in the case of the circuit example shown in FIG. 15B is shown in FIG. 17.) In FIG. 16, only three time frames are shown for convenience of explanation, but an actual LSI is shown. In, it is usually necessary to fault propagate a considerable number of time frames. A point to be noted in failure propagation is that the actual operation of the circuit operates in the order of 703 to 701, but in the propagation processing, it is performed for each time frame by tracing back time from 701 to 703. 704
Is an external output pin of the sequential circuit. Reference numeral 705 is a failure signal propagation path in the time frame 701, and 706 is a failure propagation path in the time frame 702. 707
˜709 are flip-flops used in the processing of the time frame 701. 710 to 712 are time frames 7
This is a flip-flop used in the processing of 02. Reference numeral 713 is a failure point of the target failure a. This will be described with reference to FIG. 16 according to the flow of the failure propagation processing of FIG.

At the first time frame 701, the route including the target fault 713 cannot be activated yet (step 602 in FIG. 13), and therefore FF as the D frontier.
3 (709) output is heuristically selected. This FF3
Assign the fault signal to (709) and activate fault propagation path 705 to propagate it to external output pin 704. That is, from the FF3 (709) to the external output pin 70
The state values of the external input pin and FF are assigned so as to activate the path up to 4 (step 603). The state value that has been successfully assigned is stored as a test sequence, and the input of FF3, which is the D frontier, is set as a new target PPO,
The process returns to step 602 (step 604). At this point, the route including the target failure has not been activated yet, so the process proceeds to step 603 (step 602).

Upon the processing of the time frame 702, the FF3 (709) selected as the D frontier in the processing of the time frame 701 is set as the target PPO and the FF is heuristically detected.
2 (711) is selected as D frontier, and FF2
In order to allocate the failure signal to (711) and propagate it to the FF3 (709) which is the target PPO, the failure propagation path 706 is activated (step 603), and the state value that has been successfully allocated is stored as a test sequence, FF2 is set as a new target PPO (step 604).

In the processing of the time frame 703, the F selected as the D frontier in the time frame 702
F2 (711) is the target PPO, but here, the target PPO is FF regardless of which D frontier is selected.
It is assumed that the failure signal could not be propagated to 2 (711) (step 603). Then, since the failure propagation processing of the failure 713 has failed, the failure propagation processing ends (step 604).

If the failure propagation processing fails, the process proceeds to step 402 in FIG. 12 (step 405), the next new target failure is selected, and the same processing is executed (steps 402 to 405). The above operation example is an example of a case where the failure propagation processing has failed, but when the failure signal is successfully propagated to the target failure 713 in step 405 in the time frame 703, the following is performed.

In this case, the state value assigned to the external input pin is generated as a test sequence in each time frame. However, the state of each FF is the state of the circuit at the time when the fault propagation processing ends (hereinafter, the fault excited state), and in the above example, the state value that was successfully allocated in the time frame 703, so the fault propagation The test sequence generated by the process is a test sequence that is valid only in the state at the end of the propagation process. Therefore, it is necessary to obtain a sequence for changing the state of the circuit from the initial state to the fault excited state so that the fault inspection can be executed in the desired initial state. This process is the state initialization process. The operation of the state initialization process will be described using an example of the state transition of the circuit under test shown in FIG.

In the figure, reference numerals 801 to 804 denote circuit states, particularly state 801 is a circuit state at the time when the fault propagation processing is completed, that is, a fault excited state, and state 804 is an initial state. 805 is a branch indicating that the state 802 can be transited to the state 801, 806 is a branch indicating that the state 803 can be transited to the state 802, and 807 is a branch indicating that the state 801 can be transited to the state 803. , 808 are branches indicating that the state 804 can transit to the state 803.

At the end of the failure propagation processing, the current state is the state 801 (S1) and does not match the initial state (step 502 in FIG. 14). Therefore, the current state is justified, that is, the state is changed to the current state. The external input and FF states are assigned to. Here, the state 802 is set to FF.
When the state of (S2) is assigned, it is assumed that it has been justified (step 503). The justified state is newly set as the current state (S2) (step 504).

Similarly, the current state is justified and the current state is newly set to S3 (steps 502 to 504).
Further, similarly, the current state S3 is justified, but in the case of FIG. 18, the state transition to the current state S3 is S1.
There may be two cases, that is, a transition from S4 and a transition from S4. If the justified state is S4, the state initialization will be successful. In this case, the failure check series can be obtained by combining the input series obtained in the previous failure propagation processing and the input series selected in the state initialization processing.

On the other hand, if the justified state is S1, the same process as described above is repeated again, and the process fails and falls into a state transition loop, so that the initial state cannot be obtained. After the state initialization process, using the test sequence obtained, execute a fault simulation for the target fault, confirm that it is detected at the external output pin, and check the corresponding "Detection" column in the fault table. It is set to "1" (step 407 in FIG. 12) and the process proceeds to step 402. Further, the above operation is repeated, and the inspection sequence generation processing is performed for each target failure. Finally, the test sequence generation processing in the case of the circuit example of FIG. 17 will be described. The target failure is the signal line marked with X.

(First time frame of propagation processing) Since the activation of the path including the target failure (marked by X) is not completed (step 602 in FIG. 16), the F frontier is F.
It is assumed that the output Y2 of F2 is selected (first half of step 603). In the combinational circuit portion, a state value that activates the path from the input signal y2 to the external output pin Z is assigned as follows. That is, in order for the failure signal D to be output to the external output pin Z, the two inputs of the AND gate G2 must be (I, y2) = (1, D). At this time, the input y1 may be don't care. Therefore, the state value (I, y1, y2) = (1, X, D) is assigned (the latter half of step 603).

This state value (1, X, D) is stored as a part of the test sequence, and a new target PPO is input to the FF2 at the input Y2.
(Step 604). (Second time frame of propagation processing) Assume that the target failure (marked with X) is selected as the D frontier (step 6).
02, the first half of 603).

In the combinational circuit portion, the state value for activating the path from the target failure to the target PPO Y2 is assigned as follows. That is, the failure signal D is applied to Y2.
Must be input to the OR gate G3 (output of G1, y1) = (D, 0). In addition, 2 inputs of the AND gate G1 (I, target failure) =
Must be (1, D). Therefore, the state value (I,
y1, y2) = (1, 0, 0) is assigned (the latter half of step 603).

This state value (1, 0, 0) is stored as a part of the test sequence, and a new target PPO is input to the FF1 input Y1.
However, since the route including the target failure is activated (step 602), the propagation process ends (step 605). (State Initialization Processing) Subsequently, state initialization processing is performed. If the initial state is (FF1, FF2) = (0, 0), the state initialization process ends immediately (step 5 in FIG. 14).
02, 505).

Here, the initial state is (FF1, FF2)
= (X, X) That is, the case of don't care will be described. Since the initial state (X, X) and the current state (0, 0) do not match (step 502), a state value that justifies the current state is assigned. That is, in order to justify FF1 (Y1 = 0), the two inputs (I,
y2) = (0, X). At this time, y2 may be X. Therefore, if I = 0 is assigned as the input value, the state (0, 0) can be justified (step 503).

This input value I = 0 is stored as a part of the check sequence, and the justified state (0, X) is set as the current state (step 504), which does not match the initial state (step 502). ), Justify the current state. That is, in order to justify FF1 (Y1 = 0), AND
2 inputs of the gate G1 (I, y1) = (0, X) may be used,
In order to justify FF2 (Y2 = X), the two inputs of the OR gate G3 (output of G1, y1) = (0, X) may be set. At this time, y1 may be X. Therefore, by assigning I = 0 as an input value, the state (0, X) can be justified (step 503).

This input value I = 0 is stored as a part of the test sequence, and the justified state (X, X) is set as the current state (step 504), but since it is known as coincident with the initial state (step 502). ), The justification process ends (step 505). As a result, {0011} is obtained as the test sequence to be input to the input signal I.

[0036]

However, according to the above-described test sequence generation method in the prior art, there is a problem that the failure propagation process or the state initialization process often fails, and the test sequence cannot be generated in many cases. there were. That is, if the failure propagation processing or the state initialization processing fails, the generation of the test series for the target failure is abandoned and the next target failure is proceeded to. Therefore, the success rate of test sequence generation, that is, the failure detection rate has not been improved.

In view of the above problems, it is an object of the present invention to provide a fault test sequence generation method and a test sequence generation device which can obtain a high fault coverage.

[0038]

In order to achieve the above-mentioned object, the test sequence generation method of the present invention develops a sequential circuit, which is a circuit to be tested, in a time frame to detect an assumed stuck-at fault in the sequential circuit. , A test sequence generation method that performs a fault propagation process that attempts to activate a propagation path of a fault signal of the fault for each time frame and generates a sequence for testing the fault, in which the fault signal is transmitted in one time frame. Select a power path, assign an input value in the relevant time frame so that the path is activated, and perform this process retroactively through the time frame from the output pin, which is the final failure propagation destination, to the failure location. When the activation failure is detected in the propagation processing step and in any of the time frames, the failed time frame from the first time frame In the allocation failure detection step in which at least a part of the routes in step 1 is set as prohibition information, and in the case of failure in activation, a new fault propagation processing step is added so as not to select the path set as prohibition information. And a re-fault propagation processing step to be executed.

Here, the prohibition information information may be a D frontier representing a signal line selected as a failure propagation destination from the time frame of the immediately preceding time frame selected in a predetermined time frame. The predetermined time frame may be a time frame that first activates the failure propagation path.

The prohibition information may be a set of a D frontier and a target PPO, which represents a propagation path in a predetermined time frame. The prohibition information is a D frontier and a target PPO indicating a propagation path in a time frame processed one time before a time frame in which failure propagation has failed.
It may be a pair with. The test sequence generation method according to claim 1, wherein:

Further, the sequential circuit which is the circuit to be inspected is developed in the time frame, and for the assumed stuck-at fault in the sequential circuit, the fault propagation which attempts to activate the propagation path of the fault signal of the fault for each time frame is propagated. An inspection sequence generation method for performing processing to generate a sequence for inspecting the fault,
A first step of counting the number of times the failure propagation processing has been performed for all of the target failures, and determining whether or not the count value exceeds a predetermined number of times, and if it exceeds, a test sequence generation And a second step to end
The first step is selected as a first sub-step of selecting one of target faults whose fault propagation process is untreated or quasi-untreated and whose test sequence is ungenerated. Regarding the target fault, when the D frontier indicating the input side of the path to be activated is registered as the prohibited D frontier in the time frame for propagating the target fault to the external output pin, the D frontier is selected from other than the prohibited D frontier. A second sub-step in which the failure propagation processing is performed by selecting, a third sub-step that determines whether the failure propagation processing succeeded or failed in the second sub-step, and if it is determined that the failure propagation processing has failed, Registering the D frontier selected in the time frame for propagating the influence of the target failure to the external output pin as the prohibited D frontier of the target failure; And the first to fourth sub-steps are executed for all target faults, the fault which has failed the fault propagation process is assumed to be unprocessed by the fault propagation process, and the count value is counted. 5
Sub-steps of.

In addition, the sequential circuit which is the circuit to be inspected is developed in a time frame, and for the assumed stuck-at fault in the sequential circuit, the fault propagation which attempts to activate the propagation path of the fault signal of the fault for each time frame is propagated. An inspection sequence generation method for performing processing to generate a sequence for inspecting the fault,
A first step in which a failure propagation process is performed for one target frame with respect to a certain target failure, and a propagation path selected in a time frame immediately before the time frame that is the processing target of the first step. Is stored as a pair of a signal line indicating the exit side of the path (hereinafter, target PPO) and a D frontier indicating the entrance side, and whether or not the failure propagation processing in the first step is successful. If the determination is successful, the first step is executed for the next time frame, and if the determination is unsuccessful, the combination of the target PPO and the D frontier stored in the second step is registered as the prohibited route. When the step and the failure propagation processing in the first step fail, at least one time frame before the failed time frame in the already generated test sequence. A fourth step of clearing the generated partial after chromatography beam, D registered as the prohibited path
It may consist of a fifth step of executing the first step from the corresponding time frame of the cleared part so as not to select the combination of frontier and target PPO.

Further, in the sequential circuit which is the circuit to be inspected, in order to transit the state from the initial state to the state at the end of the fault propagation processing for a certain stuck-at fault, an input signal to be applied to the input pin of the sequential circuit in time series. Is a test sequence generating method for generating a test sequence for inspecting the fault, and in the sequential circuit, the state of the memory element of the sequential circuit is set so as to justify the state at that time. An input signal to be given to an external input pin is allocated, and a justification step for executing the processing to obtain the initial state of the sequential circuit from the state of the sequential circuit when the fault propagation processing is finished; A match detection step that determines whether the state matches the state at the end of the fault propagation process or the state that has already been assigned once. And, when it is determined that they match, the assignment control step of canceling the assignment of the matched state and the signal to be given to the external input pin and avoiding the state and newly executing the justification step. Is characterized by.

Here, in the allocation control step, the justification step may be newly executed from the state at the time when the failure propagation processing is completed. In the allocation control step, the justification step may be newly executed from a state before the coincident state. Further, in the sequential circuit that is the circuit under test, in order to change the state from the initial state to the state at the end of the fault propagation processing for a certain stuck-at fault, the state in which the input signal to be applied to the input pin of the sequential circuit in time series is obtained. A first step of determining whether or not the current state is the same as the initial state by a method of generating an inspection sequence for performing an initialization process and generating a sequence for inspecting the fault. The second step of assigning a state value that justifies the state, the third step of storing the justified state as a history of state transitions, and the state newly stored in the third step is already in the history of state transitions. If it exists in the fourth step, the state is registered as prohibition information, and the state is deleted from the history of state transitions. It may be configured to include a fifth step of returning to the first step and a sixth step of returning to the first state with the justified state as the current state when it is determined not to exist in the fourth step. .

Further, the test sequence generation device of the present invention expands the sequential circuit which is the circuit to be tested in the time frame, and regarding the assumed stuck-at fault in the sequential circuit, the fault signal of the fault is output for each time frame. A test sequence generation device that performs a fault propagation process that attempts to activate a propagation route and generates a sequence that tests the fault, selects a route through which a fault signal should be transmitted in one time frame, and activates the route. The fault propagation processing means that assigns an input value in the relevant time frame so as to trace back the time frame from the output pin, which is the final fault propagation destination, to the fault location, and in any time frame ,
When the activation failure is detected, a failure detection unit that makes at least a part of the routes from the first time frame to the failed time frame the prohibition information, and the prohibition information is associated with the failure. Providing prohibition information storage means for storing, and prohibition means for prohibiting the selection of the path for which the prohibition information is set when activation fails and newly activating the failure propagation processing means for the failure It is characterized by that.

Here, the prohibition information may be a D frontier representing a signal line selected in a predetermined time frame and to be a fault propagation destination from an adjacent time frame. The predetermined time frame may be the first time frame. The prohibition information may be a set of a D frontier representing a propagation route in a predetermined time frame and a target PPO.

The prohibition information may be a set of a D frontier and a target PPO indicating a propagation path in a time frame processed one time before a time frame in which failure propagation has failed. Further, in the sequential circuit that is the circuit under test, in order to change the state from the initial state to the state at the end of the fault propagation processing for a certain stuck-at fault, the state in which the input signal to be applied to the input pin of the sequential circuit in time series is obtained. An inspection sequence generating device for performing an initialization process and generating a sequence for inspecting the fault is a test sequence generation device, and in a sequential circuit, a state of a storage element of a sequential circuit and an external input pin are set so as to justify the state at that time. Input signal given to the, and the justification means for executing the processing to obtain the initial state of the sequential circuit from the state of the sequential circuit when the fault propagation processing is finished, and the state of the sequential circuit assigned by the means, Match detection means that determines whether the state at the end of the fault propagation process or the state that has already been assigned matches, and determines that they match. If it and cancel the assignment of the input signal applied to the matched state and the external input pins, and wherein the providing the allocation control means for executing a new justification means to avoid the condition.

Here, the allocation control means may newly execute the justification means from the state at the time when the failure propagation processing is completed. The allocation control means may newly execute the justification means from the state immediately before the matched state.

[0049]

In the test sequence generation method (apparatus) of the present invention having the above-described configuration, when the failure propagation processing of the target failure fails in the failure propagation processing step (means), the allocation failure detection step (means) detects the target failure. At least a part of the route for propagating the influence is prohibited information. The re-fault propagation processing step (prohibition means) does not select the prohibition information for the target fault as a route, and newly performs the fault propagation process of test sequence generation for the same target fault.

In the state initialization process, the coincidence detection step (means) determines whether or not the state transition falls into a loop in the justification step (means).
If there is one). The allocation control step (means) is
The state that caused the formation of the loop is prohibited,
Please try again.

[0051]

【Example】

(Embodiment 1) FIG. 1 is an overall flow chart of a method for generating a test sequence of a sequential circuit in an embodiment of the present invention. The faults to be inspected by the inspection series are the same as those explained in the section of the prior art, and are listed up in advance for each signal line on the basis of the netlist of the LSI to be inspected circuit, and are listed in the fault table. It has been registered (see the example of the failure table in FIG. 11).

In FIG. 1, step 101 shows the start of processing of the test sequence generation method. In step 102, the maximum number of test sequence generation processes to be executed for undetected failures in the failure table is set. The number of times should be determined in consideration of the complexity of the circuit to be inspected, the circuit scale, the time allowed for the inspection sequence generation processing, etc., but in most cases, about 5 times is appropriate.

In step 103, the number of test sequence generation processes is initialized to zero. In step 104, it is judged whether or not the number of inspection sequence generation processes exceeds the maximum number of inspection sequence generation processes for the undetected fault set in step 102. If it does not exceed the maximum number, the process proceeds to step 105, If it exceeds, the process proceeds to step 115.

In step 105, it is judged whether or not there is any undetected and unprocessed fault other than the redundant fault in the fault table. If it exists, the process proceeds to step 106, and if it does not exist, the process proceeds to step 113. In steps 106 and 107, one target fault is selected from the undetected and unprocessed fault groups, and as a pre-stage of the test sequence generation, it is checked whether or not it is an undetectable fault. Therefore, only the combinational circuit portion is inspected. Generate input. This is the step 403, 404 in FIG. 12 described in the prior art.
Is the same as.

In step 108, fault propagation processing is performed for the selected target fault. Steps 109 and 11
At 0, state initialization processing and failure simulation are performed. This is the same as steps 406 and 407 in FIG. 12 described in the description of the prior art. In step 111, it is judged whether or not the fault propagation processing of test sequence generation processed in step 107 is successful. If it is successful, the processing proceeds to step 105, and if it fails, the processing proceeds to step 112.

In step 112, the D frontier selected in the time frame for propagating the influence of the target failure to any external output pin is registered in the prohibited D frontier set of the target failure. FIG. 2 shows an example of registration of the prohibited D frontier set. In the figure, "signal line" indicates the target failure location, "failure" indicates the type of failure, and "D frontier" indicates the D frontier that is prohibited to be selected. As shown in the figure, in the present embodiment, the prohibited D frontier is registered for each failure.

In step 113, undetected faults other than redundant faults in the fault table are treated as unprocessed faults. That is,
The "processing" column of a fault in which the "detection" column is 0 and the "redundant fault" is not 1 is set to 0. As a result, the failure for which the test sequence generation has failed is selected again in step 106. In step 114, the number of inspection sequence generation processes for undetected faults is incremented by one.

Step 115 shows the end of the processing of the test sequence generation method. FIG. 3 is a diagram showing a more detailed flow of the failure propagation processing in step 108 of FIG. The figure is different only in that steps 1403 to 1405 are added to the flow of the failure propagation processing of FIG. 13 described in the related art. That is, when selecting the D frontier in the k-th time frame, those registered in the prohibited D frontier set are not selected. As a result, in the k-th time frame of the failure propagation processing from the second time onward, a D-frontier other than the previously failed one is selected.

In the figure, in step 1402, it is judged whether or not the route including the target failure is activated. If it has been activated, it is determined that the failure propagation processing has succeeded, and the process proceeds to step 1409. If it has not been activated, the process proceeds to step 1403. In step 1403, it is determined whether or not the time frame to be processed is the k-th time frame. If it is the k-th time frame, the process proceeds to step 1404, and if not, the process proceeds to step 1406. However, in this embodiment, k = 1.

At step 1404, the target failure point or the output of the FF (that is, the input of the combinational circuit portion).
Select one from among as D frontier. that time,
The forbidden D frontier set is referred to, and one not registered as the forbidden D frontier for the failure is selected. In step 1405, the selected D frontier is temporarily stored.

In step 1406, one D frontier is selected from the target failure location or the output of the FF. This selection method is a conventional technique (step 603 in FIG. 13).
The first half) is the same. Step 1407 assigns a fault signal to the selected D frontier in the time frame of interest, up to any external output pin or input of the selected D frontier (target PPO) in the previously processed time frame. In order to propagate the fault signal (that is, activate the fault propagation path), state values are assigned to the external input pin and the output of the FF. If the fault propagation is successful, the process proceeds to step 1408, and if it fails, the fault propagation process is performed. Since it has failed, the process proceeds to step 1409. This pathway activation is performed by the conventional technique (step 6 in FIG. 13).
The latter half of 02).

In step 1408, step 1407
In step 1402, the input value assigned to the external input pin for activation of the fault propagation path is stored as a part of the inspection sequence, and the input of D frontier is newly set as the target PPO.
Go to. In step 1409, the end of the failure propagation processing is shown. The operation of the test sequence generating method according to the first embodiment of the present invention configured as above will be described.
An explanatory diagram of an operation example of this fault propagation is shown in FIG.

In FIG. 4, the same reference numerals as those in FIG. 16 used in the description of the prior art are the same as those in FIG.
Reference numeral 1001 denotes a prohibited D frontier set of the target failure 713. Reference numerals 1002 to 1004 denote failure propagation paths of the time frames 701, 702, and 703 in the second propagation processing, respectively. First, in the present embodiment, the maximum number of times to be repeated when the propagation process fails is set to 5 times (step 102 in FIG. 1), and the variable i for controlling the number is set to the initial value 0 (step). 103). Next, it is determined whether or not the variable i has reached the maximum number of times. If it has reached the maximum number, the process proceeds to step 112, and if not, the step 10
5 (step 104).

Since the following steps 105 to 107 are the same as the steps 402 to 404 in FIG. 12 in the prior art, description thereof will be omitted. If the test input generation is successful in step 107, a fault propagation process is performed to generate a test sequence for the target fault (step 10).
8). In the first-time (when i = 0) failure propagation processing, it is assumed that the failure propagation processing for the target failure 713 is performed as described with reference to FIG. 16 in the section of the related art. Since the operation of the propagation process itself is almost the same as that of the conventional technique, only different points will be described. That is, in the first time frame (step 1403), when selecting the D frontier, the ones other than those registered as the prohibited D frontier are selected. However, since nothing is registered as the prohibited D frontier in the first failure propagation processing, as a result, FF3 is D
It will be selected as the frontier (step 1404 in FIG. 3). Further, the selected D frontier is temporarily stored (step 1405).

Go to the second and third time frames,
It is assumed that the activation of the propagation path has failed in the third time frame as in the conventional technique. Furthermore, the success or failure of the failure propagation processing is judged (step 111), and when the failure propagation processing fails, the D frontier 709 temporarily stored in step 1405 of FIG.
It is registered in the prohibited D frontier set 1001 of No. 3 (step 112).

After that, the above-mentioned processing is executed for each unprocessed failure in the failure table (repeat from step 105 to 111 or 112). At this time, the failure for which the failure propagation processing has failed is the k-th (implemented). In the example, the D frontier in the time frame of k = 1) is registered as the prohibited D frontier for the failure. When the inspection sequence generation processing is completed for each unprocessed failure, it is determined that there is no unprocessed failure (step 105),
In the failure table, the "detection" column is 0, and the "redundancy failure" is not 1, the "processing" column is set to 0 (step 113). This causes the failed fault to be selected again. The variable i indicating the number of repetitions of the test sequence generation process is incremented by 1 (step 114), and the process proceeds to step 105.

In the second failure propagation process (when i = 2), the failure 713 that failed when i = 1 is selected again as a target failure (step 106), and the test input generation of the combinational circuit (step 107). ), The fault propagation processing is performed as follows. Time frame 701 of FIG.
Since it is the first time frame in the processing of (1) (step 1403), the prohibited FF3 (709) is not selected as the D frontier by referring to the prohibited D frontier set 1001. As a result, FF1 (707) is the D frontier. Heuristically selected as (step 14
04), which is temporarily stored (step 1405), activates the fault propagation path 1002 to the external output pin 704 (step 1407), and sets FF1 (707) to the target PPO.
(Step 1408).

In the second time frame 702,
FF3 (712) is selected as the D frontier (steps 1403 and 1406), and the influence of the failure is FF3 (71).
In order to propagate from 2) to FF1 (707) which is the target PPO, the fault propagation path 1003 is activated (step 1407) and FF3 (712) is set as the target PPO (step 1408).

In the third time frame 703,
The failure point 713 is selected as the D frontier (steps 1403 and 1406), and the influence of the failure is determined as the failure point 713.
Fault propagation path 1004 in order to propagate it from the target PPO to FF3 (712) (step 1
407). Since the target fault has been activated here (step 1402), the process proceeds to the state initialization process in which the propagation process has succeeded.

Since the subsequent state initialization processing is the same as that described in the prior art, the description thereof will be omitted. As mentioned above,
According to the present embodiment, when the fault propagation process fails as a result of the test sequence generation of a certain target fault, the k-th time frame (in the embodiment, k = 1, that is, the influence of the target fault is output to the external output pin). Register the D frontier selected in (Propagation time frame) to the prohibited D frontier set,
By generating the test sequence of the failed target fault again, when the test sequence of the target fault is generated again, the target fault is prohibited in the time frame for propagating the influence of the target fault to the external output pin. By not selecting a signal line belonging to the D frontier as the D frontier and dynamically changing the fault propagation path,
Since the probability of successful generation of the test sequence for the target fault is high, it is possible to generate a test sequence capable of obtaining a high fault coverage. (Embodiment 2) FIG. 5 is a diagram showing a fault propagation process of a test sequence generation method for a sequential circuit according to a second embodiment of the present invention. The overall flow of the test sequence generation method is almost the same as that of FIG. 12 used in the description of the conventional technique, except that the fault propagation processing 405 of FIG. 12 is the flow of FIG.
Hereinafter, only the fault propagation process will be described.

In FIG. 5, step 301 shows the start of the fault propagation processing according to the present invention. In step 302, it is determined whether or not the target fault is activated. If the target fault is activated, the process proceeds to step 308, and if it is not activated, the process proceeds to step 303. In step 303, one of the target failure and the output of the flip-flop is selected as the D frontier, and any external output pin or the input of the flip-flop selected as the D frontier in the immediately preceding time frame (target PPO). Generate a test input that propagates the fault signal to. If this process fails, the process proceeds to step 306, and if it succeeds, the process proceeds to step 304. However, the combination of the D frontier and the target PPO belonging to the prohibited combination set is not selected.

At step 304, the pair of the target PPO and the D frontier is temporarily stored. In step 305, if the D frontier selected in step 303 is a flip-flop, its input is set as the target PPO. In step 306, the combination of the D frontier and the target PPO stored in step 304 is added to the prohibited combination set. An example of the prohibited combination set is shown in FIG. In the figure, "signal line" indicates the target failure location, "failure" indicates the failure type, "D frontier" and "target PP".
The set of "O" indicates a prohibited route.

At step 307, all the inspection sequences generated halfway are cleared, and the routine proceeds to step 302. In step 308, the prohibited combination set is cleared, and the failure propagation processing ends. The operation of the fault propagation processing of the test sequence generation method of the sequential circuit according to the third embodiment of the present invention configured as above will be described.

FIG. 7 is a diagram used for explaining the operation of the fault propagation processing. 16 that are the same as those in FIG. 16 used in the description of the conventional technique have the same reference numerals. 1
201 is the prohibited combination set shown in FIG. 1202
Is a failure propagation path of the time frame 702, and 1203 is a failure propagation path of the time frame 703. Target failure 7
In the test sequence generation of No. 13, the test sequence generation is assumed to have failed because the failure propagation of the time frame 703 has failed as described with reference to FIG. 16 in the description of the prior art (step 303 of FIG. 5). . Here, as shown in FIG. 7, when failure propagation processing fails, the output of FF2 (711), which is the D frontier of the time frame 702 immediately before the failed time frame 703, and the target PP.
The combination with the input of FF3 (709) which is O is registered in the prohibited combination set 1201 (step 306).

Next, to clear all the sequences generated for the target fault 713 and return to the first time frame 701 to perform fault propagation processing again (step 307), the D frontier 709 is selected in the time frame 701. ,
In order to propagate the influence of the target fault b (713) to the external output pin, the fault propagation path 705 is activated (step 30
2, 303), the combination of the D frontier 709 and the external output pin PO representing the failure propagation path 705 is temporarily stored (step 304), and the input of the D frontier is set as the next target PPO (step 305).

At time frame 702, the elements of the prohibited combination set 1201 (D frontier 711, target PPO 7
09), the target PPO is now 709, so F
As a result of not selecting F2 (711) as the D frontier, FF1 (710) is selected as the D frontier, and the fault propagation path 1202 up to FF3 (709) which is the target PPO is activated (steps 302 to 3).
05).

Next, the processing of the time frame 703 is performed, the failure location 713 is selected as the D frontier, and the effect of the failure is changed from 713 to the target PPO FF1 (71).
The fault propagation path 1203 is activated to propagate it to 0) (steps 302 to 305). Since the target fault is activated here, the fault propagation process succeeds and the process proceeds to the state initialization process (step 302).

In step 307, all the test sequences generated up to that point are cleared and the propagation process is executed again from the first time frame. However, the present invention is not limited to this. Since the path of the time frame processed immediately before is prohibited, the processing may be performed again from the processing of the time frame processed immediately before the failed time frame.

As described above, according to the present embodiment, when the failure propagation processing fails as a result of the test sequence generation of a certain target failure, the D frontier of the time frame immediately before the failed time frame is set. By registering the combination of the target PPOs into the prohibited combination set, clearing all or part of the generated sequence, and performing the fault propagation processing again, it belongs to the prohibited combination set in the processing of a certain time frame. By not selecting the combination and dynamically changing the fault propagation path, the probability of successful test sequence generation of the target fault increases, so it is possible to generate a test sequence that can obtain a high fault coverage. it can. (Third Embodiment) FIG. 8 is a diagram showing a state initialization process of a check sequence generating method for a sequential circuit according to a third embodiment of the present invention. The overall flow of the test sequence generation method is almost the same as that of FIG. 12 shown in the related art, but only the state initialization processing part is different. Only the state initialization process will be described below.

In FIG. 8, step 201 shows the start of the state initialization process according to the present invention. In step 202, it is determined whether or not the current state and the initial state of the circuit match. If the current state and the initial state match, the process proceeds to step 208, and if they do not match, the process proceeds to step 203.

In step 203, the current state is justified by assigning values to the external input pin and the flip-flop so that the state does not belong to the prohibited state set registered in step 206. In step 204, the state justified in step 203 is added to the history of state transitions in the history of state transitions. The history of state transition is, for example, as shown in the history table shown in FIG. As shown in the figure, each state can be represented by a state name for identifying the state and a state value of each FF forming the state.

At step 205, it is judged whether or not there are two states justified at step 203 in the history of state transition. If there are two states, the routine proceeds to step 206,
If it does not exist, the process proceeds to step 207. Step 20
In step 6, the state justified in step 203 is deleted from the state transition history, and the state is registered in the prohibited state set.
If there are two same states in the history of state transitions,
Since the state transition loop is formed, the state initialization process can be prevented from falling into a loop by making the justified state a prohibited state later.

In step 207, the state justified in step 203 is newly set as the current state. Step 208
Now, delete the prohibited state set. Step 209 indicates the end of the state initialization process according to the present invention. The operation of the state initialization process of the test sequence generation method for the sequential circuit according to the third embodiment of the present invention configured as above will be described.

FIG. 10 is a diagram used for explaining the operation of the state initialization process of the test sequence generation of the sequential circuit in the second embodiment of the present invention. In the figure, reference numeral 1101 in FIG. 10A represents a history of state transitions when two identical states exist during the state initialization process of the circuit under test having the state transitions shown in FIG. 1102 in FIG. 5B is 1101.
2 shows the history of state transitions when the state assigned later is deleted from the existing two states.

Reference numeral 1103 in FIG. 5C represents a history of state transitions when the state initialization process of the circuit under test having the state transitions shown in FIG. 18 is completed successfully. In FIG. 18, which illustrates the operation of the state initialization process in the conventional technique, a sequence of transition from the initial state 804 to the fault excited state 801 is generated as follows.

First, the fault excited state 801 is registered in the history of state transition (step 201). Next, the fault excited state 80
As a result of justifying 1, the state 802 is obtained (step 20
3) Register in the history of state transition (step 204).
Since the state 802 is not the initial state and two identical states do not exist in the state transition history (step 205), the justified state is set as the current state (step 207), and the state 8
02 is justified (steps 202 and 203). Similarly, the states 803 and 801 are justified and registered in the state transition history.

Since there are two states 801 in the state transition history 1101 at this time (step 205, FIG. 1).
0 (a)), the state 801 is deleted from the state transition history 1101, and the state 801 is registered in the prohibited state set (step 206, FIG. 10B). As a result of justifying the state 803 so as not to become the prohibited state 801 again (step 203), the state 804 is obtained and registered in the history of state transition (step 204, FIG. 5C). Here, two identical states do not exist in the state transition history 1103 (step 205). Further, since the state 804 is equal to the initial state (step 202), the state initialization is successful and the process ends. As described above, according to the present embodiment, the history of state transitions is stored when performing the state initialization process of generating a test sequence of a certain target fault, and two or more identical states exist in the history of state transitions. In that case, by deleting the state from the history of state transition, registering it as a prohibited state, and executing the state initialization process so that it will not become the prohibited state again,
Since the probability of successful state initialization increases and the test sequence generation can succeed, it is possible to generate a test sequence that can obtain a high fault coverage.

[0088]

As described above, according to the test sequence generation method (apparatus) of the present invention, when the failure propagation processing of the target failure fails, at least a part of the route for propagating the influence of the target failure. Is stored as prohibition information. Newly, the prohibition information for the target fault is not selected as a route, and the fault propagation process of the test sequence generation for the same target fault is performed. This has the effect of improving the probability of successful failure propagation processing, and thus the failure detection rate.

Further, in the state initialization processing, it is detected whether or not the state transition has fallen into a loop (whether there are two same states), and the state that caused the formation of the loop is set as the prohibited state and the processing is performed again. This has the effect of improving the probability of successful state initialization, and thus the failure detection rate.

[Brief description of drawings]

FIG. 1 is a flow chart of a test sequence generation method for a sequential circuit according to a first embodiment of the present invention.

FIG. 2 is a table showing a prohibited D frontier set in the first embodiment of the present invention.

FIG. 3 is a flowchart of a fault propagation processing part of the test sequence generation method according to the first embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of the fault propagation processing portion of the test sequence generation method in the first example of the present invention.

FIG. 5 is a flow chart of a fault propagation processing portion of a test sequence generation method for a sequential circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a prohibited combination set according to the second embodiment of the present invention.

FIG. 7 is an operation explanatory diagram of a fault propagation processing portion of the test sequence generation method according to the second embodiment of the present invention.

FIG. 8 is a flowchart of a state initialization part of a check sequence generation method for a sequential circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a history of state transitions in the third example of the present invention.

FIG. 10 is an operation explanatory diagram of the state initialization part of the check sequence generation method for the sequential circuit in the third embodiment of the present invention.

FIG. 11 is a failure table of an example of a circuit under test.

FIG. 12 is a flowchart of a conventional test sequence generation method for a sequential circuit.

FIG. 13 is a flowchart of a fault propagation part of a conventional test sequence generation method for a sequential circuit based on the RTP (Reverse Time Processing) method.

FIG. 14 is a flowchart of a state initialization part of a conventional test sequence generation method for a sequential circuit.

15A is an explanatory diagram of a combinational circuit portion and a flip-flop portion in a sequential circuit. FIG. 15B is a simple circuit example in FIG.

FIG. 16 is an operation explanatory diagram of a fault propagation portion of a conventional sequential circuit check sequence generation method.

FIG. 17 is an example of test sequence generation in the circuit example of FIG.

FIG. 18 is an explanatory diagram of an example of state transition in the state initialization process.

[Explanation of symbols]

102 Process for setting the maximum number of test sequence generation processes to be executed for undetected failures in the failure table. 103 Process for initializing the number of test sequence generation processes to 0. 104 A process of determining whether or not the number of test sequence generation processes has exceeded the maximum number. 105 A process of determining whether or not there is an undetected and unprocessed fault in the fault table. 106, 107 A target fault is selected from a fault group that has not been detected and has not yet been processed, and a check input is generated only for the combinational circuit part in order to check whether it is an undetectable fault as a pre-stage of generating a check sequence. Processing. 108 A process of performing a fault propagation process for the selected target fault. 109, 110 State initialization processing, failure simulation processing. 111 Processing for determining whether or not the failure propagation processing of test sequence generation processed in step 107 is successful. 112 A process of registering the D frontier selected in the time frame for propagating the influence of the target failure to any external output pin, in the prohibited D frontier set of the target failure. 113 Processing of undetected failures other than redundant failures in the failure table as unprocessed failures. 114 A process of incrementing the number of inspection sequence generation processes for undetected faults by one. 115 Process indicating the end of the process of the test sequence generation method. 1402 Processing for determining whether or not a path including a target failure is activated. 1403 Processing for determining whether the time frame to be processed is the k-th time frame. 1404 Other than the prohibited D frontier, the target failure location,
Alternatively, a process of selecting one as a D frontier from the output of the FF (that is, the input of the combinational circuit portion). 1405 A process of temporarily storing the selected D frontier. 1406 1 out of target failure location or FF output
The process of selecting one D frontier. 1407 A process of activating a failure propagation path in a target time frame. 1408 stores the state value assigned to the external input pin for activation of the fault propagation path as a part of the inspection sequence, and D
A process of newly inputting the frontier as a target PPO. 1409 Processing indicating the end of the failure propagation processing. 203 Do not become a state that belongs to the prohibited state set
A process for justifying the current state by assigning values to external input pins and flip-flops 204 A process for adding a state justifying the current state to the history of state transitions 205 A current state justified in the history of state transitions Process 206 for determining whether or not there are two states 206 Process for deleting the same state and registering it in the prohibited state set when there are two same states in the history of state transitions 208 Process for deleting the prohibited state set 302 A process of determining whether or not the target failure is activated. 303 As the D frontier, either one of the target failure and the output of the flip-flop is selected, and any external output pin or the input of the flip-flop selected as the D frontier in the previous time frame (target PP
The process of generating a test input that propagates a fault signal to O).
However, the process of not selecting the combination of the D frontier and the target PPO belonging to the prohibited combination set. 304 A process of temporarily storing a pair of a target PPO and a D frontier. 305 Processing for setting the input side of the flip-flop whose output side is the D frontier as the target PPO. 306 A process of adding the stored combination of the D frontier and the target PPO to the prohibited combination set. 307 A process of clearing all the inspection sequences generated halfway. 308 A process of clearing the prohibited combination set and ending the failure propagation process.

Claims (19)

[Claims] 1. A fault propagation method in which a sequential circuit, which is a circuit to be tested, is developed in a time frame, and an assumed stuck-at fault in the sequential circuit is attempted to activate a propagation path of a fault signal of the fault for each time frame. An inspection sequence generation method for performing processing to generate a sequence for inspecting the fault, wherein a route through which a fault signal should be transmitted is selected in one time frame, and an input value in the time frame is activated so that the route is activated. And a failure propagation processing step in which this processing is performed by tracing back the time frame from the output pin that is the final failure propagation destination to the failure location, and when activation failure is detected in any of the time frames. , Allocation failure detection with prohibition information of at least some of the routes from the first time frame to the failed time frame And a re-fault propagation processing step for newly executing a failure propagation processing step so as not to select a path that is prohibited information when activation fails, and a new test sequence generation method. . 2. The prohibition information information is a D frontier that represents a signal line selected as a fault propagation destination from a time frame of a time immediately before, which is selected in a predetermined time frame. Item 1. The inspection sequence generation method according to Item 1. 3. The test sequence generation method according to claim 2, wherein the predetermined time frame is a time frame which first activates a failure propagation path. 4. The prohibition information is a D frontier and a target PPO indicating a propagation path in a predetermined time frame.
2. The test sequence generation method according to claim 1, wherein 5. The prohibition information is a set of a D frontier and a target PPO, which represents a propagation path in a time frame processed immediately before a time frame in which failure propagation has failed. The inspection sequence generation method described. 6. A fault propagation method in which a sequential circuit, which is a circuit to be inspected, is developed in a time frame, and an assumed stuck-at fault in the sequential circuit attempts activation of a propagation path of a fault signal of the fault for each time frame. A test sequence generation method for performing a process to generate a sequence for inspecting the fault, the first step of counting the number of times the fault propagation process is performed through all target faults, and the count value is It comprises a second step of judging whether or not a predetermined number of times is exceeded, and ending the test sequence generation if the number of times is exceeded, wherein the first step is to assume that the fault propagation processing is unprocessed or unprocessed. A selected sub-step of selecting one of the selected faults for which a test sequence has not been generated, and a time step for propagating the target fault to an external output pin for the selected target fault. In the system, if the D frontier indicating the input side of the route to be activated is registered as the prohibited D frontier, the second substep of selecting the D frontier from other than the prohibited D frontier and performing the failure propagation processing And a third sub-step of judging whether the failure propagation processing succeeded or failed in the second sub-step, and a time frame for propagating the influence of the target failure to the external output pin when it is judged as failure. A fourth substep of registering the D frontier selected in step 1 as a prohibited D frontier for the target failure, and a failure for which failure propagation processing fails when the first to fourth substeps are executed for all the target failures. And a fifth sub-step of counting the count value by assuming that the failure propagation processing is unprocessed. Test sequence generation how to. 7. A fault propagation in which a sequential circuit which is a circuit under test is developed in a time frame and an assumed stuck-at fault in the sequential circuit is attempted to activate a propagation path of a fault signal of the fault for each time frame. A test sequence generation method for performing a process to generate a sequence for inspecting the fault, comprising: a first step of performing a fault propagation process for one target time frame for a certain target fault; The propagation path selected in the time frame immediately before the time frame to be processed is stored as a pair of a signal line (hereinafter, target PPO) indicating the exit side of the path and a D frontier indicating the entrance side. 2) and whether or not the failure propagation processing in the first step is successful, and if successful, execute the first step for the next time frame and fail. In this case, when the failure propagation processing in the third step of registering the combination of the target PPO and the D frontier stored in the second step as the forbidden path and the first step fails, it is already generated. A fourth step of clearing a portion of the inspection sequence generated at least one time frame before the failed time frame, a D frontier registered as the prohibited route, and a target P.
And a fifth step of executing the first step from the corresponding time frame of the cleared portion so as not to select the combination of POs. 8. An input signal to be applied to an input pin of a sequential circuit in time series in order to make a transition from an initial state to a state at the end of fault propagation processing for a certain stuck-at fault in a sequential circuit which is a circuit under test. Is a method for generating a test sequence for generating a sequence for inspecting the fault by performing a state initialization process to obtain a state of a memory element of the sequential circuit so as to justify the state at that time. An input signal to be given to an external input pin is assigned, and a justification step for executing the processing to obtain the initial state of the sequential circuit from the state of the sequential circuit when the fault propagation processing is finished; A match detection step of determining whether the state matches the state at the end of the fault propagation processing or the state already assigned once. , If it is determined that they match, cancel the assignment of the matched state and the input signal given to the external input pin,
A test sequence generation method, comprising: an allocation control step for avoiding the state and newly executing a justification step. 9. The test sequence generation method according to claim 8, wherein the allocation control step newly executes the justification step from a state at the time when the failure propagation processing ends. 10. The method for generating a test sequence according to claim 8, wherein the allocation control step newly executes the justification step from a state immediately before the coincident state. 11. A sequential circuit which is a circuit under test,
In order to transition the state from the initial state to the state at the end of the fault propagation process for a certain stuck-at fault, the state initialization process is performed to find the input signal to be applied to the input pins of the sequential circuit in time series, and the fault is inspected. The test sequence generating method is a test sequence generation method, and it is determined whether or not the current state matches the initial state,
The first step that ends if they match, the second step that, if they do not match, assigns the state value that justifies the current state and the input signal that is given to the external input pin, and the justified state Is stored as a history of state transitions, a fourth step of determining whether or not the state newly stored in the third step already exists in the history of state transitions, and a fourth step When it is determined that the state does not exist, the state is registered as prohibition information, the state transition history is deleted and the process returns to the second step, and the fourth step determines that the state does not exist. And a sixth step of returning to the first state with the justified state as the current state. 12. A fault propagation method in which a sequential circuit, which is a circuit to be inspected, is developed in a time frame, and for an assumed stuck-at fault in the sequential circuit, an attempt is made to activate a propagation path of a fault signal of the fault for each time frame. An inspection sequence generation device that performs processing and generates a sequence for inspecting the fault, selecting a route through which a fault signal should be transmitted in one time frame, and inputting value in the time frame so that the route is activated. And the failure propagation processing means that performs this processing by tracing back the time frame from the output pin which is the final destination of the failure propagation to the failure location, and when the activation failure is detected in any of the time frames. , Failure detection means that uses at least some of the routes from the first time frame to the failed time frame as prohibition information, , A prohibition information storage unit that stores the prohibition information in association with the failure, and prohibits the selection of the path designated as the prohibition information when activation fails, and newly fails the failure. A test sequence generation apparatus comprising: a prohibition unit that activates a propagation processing unit. 13. The prohibition information information is a D frontier that represents a signal line selected in a predetermined time frame and to be a fault propagation destination from an adjacent time frame. Inspection sequence generator. 14. The test sequence generation device according to claim 13, wherein the predetermined time frame is a first time frame. 15. The prohibition information is a D frontier indicating a propagation path in a predetermined time frame and a target PPO.
13. The test sequence generation device according to claim 12, which is a set of 16. The method according to claim 12, wherein the prohibition information is a set of a D frontier and a target PPO which represent a propagation path in a time frame processed one time before a time frame in which failure propagation has failed. Inspection sequence generator. 17. A sequential circuit which is a circuit under test,
In order to transition the state from the initial state to the state at the end of the fault propagation process for a certain stuck-at fault, the state initialization process is performed to find the input signal to be applied to the input pins of the sequential circuit in time series, and the fault is checked. A test sequence generating device generates a test sequence, and in a sequential circuit, allocates a state of a memory element of the sequential circuit and an input signal given to an external input pin so as to justify the state at that time, and performs the processing. The justification means for executing the initial state of the sequential circuit from the state of the sequential circuit when the fault propagation processing is finished, and the state of the sequential circuit assigned by the means are the state at the end of the fault propagation processing, or already once. A match detection means for determining whether or not it matches the assigned state, and a match state and an external input pin when it is determined to match. Cancel the assignment of the input signal to the
A test sequence generation device comprising: an allocation control unit that newly executes a justification unit while avoiding the state. 18. The test sequence generation device according to claim 17, wherein the allocation control means newly executes the justification means from a state at the time when the failure propagation processing is completed. 19. The test sequence generation device according to claim 17, wherein the allocation control means newly executes the justification means from a state immediately before the matched state.