JP2642265B2 - Inspection method of test pattern of logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test pattern of a logic circuit input to an input terminal of a logic circuit while observing an output state of an output terminal of the logic circuit in order to detect a failure of a predetermined logic circuit. In particular, the present invention relates to a method for inspecting a test pattern of a logic circuit for more effective evaluation of a fault detection capability of a test pattern.

[0002]

2. Description of the Related Art In a method of detecting a failure of a logic circuit such as an integrated circuit or the like consisting of predetermined logic gates, a test pattern prepared in advance is sequentially input to an input terminal of the logic circuit. There is a method of observing the output state of.

In this method, for example, a test pattern to be input to an input terminal and an expected output pattern corresponding to the test pattern are created in advance, and the test pattern is input to an input terminal of a predetermined logic circuit to be inspected. Then, the output state of the output terminal at this time is compared with the expected output pattern, thereby detecting a failure of the logic circuit.

According to such a logic circuit failure detection method, it is possible to detect a failure of an already completed logic circuit, for example, an integrated circuit sealed in a package, from outside the integrated circuit.

Further, as a test method of a test pattern used for detecting a failure of a predetermined logic circuit, there is a toggle check method or a toggle check tool for automatically performing the toggle check method.

In detecting a fault in a logic circuit using a test pattern, when the number of input terminals of the logic circuit to be tested increases, the number of test patterns for testing the logic circuit increases.

Therefore, it is difficult to use a test pattern including all patterns for input terminals in a fault test of a logic circuit using a test pattern.

Further, even if the test pattern covers all the patterns for the input terminals, it may not be possible to detect all the faults of the logic circuit.

Therefore, a test pattern itself used for detecting a failure of such a logic circuit is also inspected.

The above-described toggle check is one of the test methods of a test pattern used for a fault test of a logic circuit.

This toggle check is performed by simulating a logic circuit which is a failure detection target of a test pattern by using a logic simulator capable of simulating a logic circuit which is a failure detection target of the test pattern to be inspected. Inspect itself. At this time, a change in the logic state of each net in the logic circuit is detected, and the number of changes in the logic state, that is, the number of toggles is counted for each net.

According to such a toggle check, it is possible to evaluate the fault detection capability of a test pattern to be inspected in accordance with a test result report which is the number of toggles of each net obtained as an inspection result.

[0013]

However, in the test pattern inspection by the toggle check described above,
The inventor has found that even if a change in the logical state of each net is detected, a fault relating to this net portion cannot always be detected from outside the logic circuit.

That is, in the test pattern inspection by the toggle check, even if a change in the logic state of each net is counted, the change in the logic state may not be observed at the output terminal of the logic circuit. Is found.

In the case where the failure cannot be observed at such an output terminal, there is a problem that even if there is a fault related to the net portion, the fault cannot be found by a fault test using this test pattern.

The present invention has been made to solve the above-mentioned conventional problem. In order to detect a failure of a predetermined logic circuit, the present invention observes the output state of an output terminal of the logic circuit while observing the output state of the logic circuit.
In the method for testing a test pattern of a logic circuit input to an input terminal of the logic circuit, a method for testing a test pattern of a logic circuit capable of reporting information for more effective evaluation of the fault detection capability of the test pattern is described. The purpose is to provide.

[0017]

SUMMARY OF THE INVENTION In order to detect a failure in a predetermined logic circuit, the present invention observes the output state of the output terminal of the logic circuit while monitoring the output state of the logic circuit. In the test pattern inspection method, the test pattern is executed step by step by logic simulation, and when the logic state of the net inside the logic circuit changes,
It is determined whether or not the change in the logic state is unobservable at the output terminal of the logic circuit. If it is determined that the change is not observable, the invalid toggle number of the net is counted up,
The above object has been achieved by obtaining the number of valid toggles from the number of invalid toggles and the total number of toggles and evaluating the fault detection capability of the test pattern.

Further, the determination that the observation is impossible is performed by:
The above-described object is also achieved by performing the determination according to the presence or absence of a change in the logic state of the output terminal in the corresponding step during the logic simulation.

[0019]

According to the present invention, in a method for inspecting a test pattern of a logic circuit, the logic state of each net of the logic circuit to be inspected must be changed in accordance with the execution of the test pattern. Is focused on a first point that the change of the data must be observable from outside the logic circuit.

That is, a change in the logic state of the net inside the logic circuit must be observable as a change in the logic state of the output terminal of the logic circuit.

In addition to the first point of interest, the present invention, when a change in the logical state is detected, determines that the change in the logical state is observable at the output terminal of the logic circuit.
A second point of interest has been found that it is easy to determine that this change in logic state is not observable at the output terminal of the logic circuit.

This is because, when a test pattern is executed for each step in the logic simulation, the logic state of the net inside the logic circuit changes (toggles), and for example, the logic state of the output terminal of the logic circuit changes. This is because it cannot be determined that the change in the logic state of the output terminal is a change in the logic state of the net. Because,
For example, when the logic states of a plurality of nets inside the logic circuit change and the logic state of the output terminal of the logic circuit changes, the change of the logic state of the output terminal changes the logic state of the plurality of nets. This is because it is not immediately possible to determine which net is due to a change in the logical state.

On the other hand, when the test pattern is similarly executed for each step in the logic simulation, for example, even if the logic state of the net inside the logic circuit changes, for example, the change of the logic state of the output terminal of the logic circuit changes. This is because, if there is no, it is possible to determine that a change in the logic state of the net cannot be observed at the output terminal of the logic circuit.

Further, the number of invalid toggles of each net counted up each time it is determined that such a test pattern cannot be observed is used as the number of valid toggles by using the total number of toggles, so that the failure of the test pattern can be determined. The detection ability can be evaluated more effectively.

Therefore, according to the present invention, when a test pattern is executed for each step in a logic simulation, when the logic state of a net in a logic circuit changes, it is not determined whether or not the net can be observed, but the logic state is determined. Is determined at the output terminal of the logic circuit as to whether or not it is not observable, and when it is determined that the change is not observable, the invalid toggle number of the net is counted up. At a predetermined time, such as after all test patterns have been completed, the number of valid toggles is calculated from the number of invalid toggles and the total number of toggles of each of the counted up nets. The test results are mainly evaluated based on the number of effective toggles of the net, and the failure detection capability of the test pattern is evaluated.

Note that the logical state of the present invention is a state of a logical value "0" or "1". Alternatively, the state may include a state of a logical value “0” or “1” and a state including a high impedance state. The total number of toggles is the number of times the logic state of each net changes when a test pattern is executed for each step in a logic simulation. The number of invalid toggles means the number of times the test pattern is executed for each step in the logic simulation.
The logic state of a certain net inside the logic circuit changes (toggle)
Nevertheless, this is the number of times that a change in the logic state cannot be observed at the output terminal of the logic circuit. Therefore, the sum of the number of invalid toggles and the number of valid toggles is the total number of toggles.

The toggle according to the present invention refers to a mutual change between these logic states. Also, the number of toggles of the present invention,
The number of invalid toggles and the number of valid toggles need only correspond to the number of such changes. Note that a net is each wiring in a logic circuit.

FIG. 1 is a flowchart showing the gist of the present invention.

The processing shown in the flowchart of FIG. 1 is a logic capable of performing a logic simulation of a logic circuit in which a failure is detected using a test pattern to be inspected by the test method of a test pattern of a logic circuit of the present invention. This is performed mainly using a simulator. This logic simulator observes the output state of the output terminal of the logic circuit and a change in the output state when the test pattern to be inspected is input to the input terminal of the logic circuit to be tested in each step. In addition to the above, it is possible to grasp the logical state or the change of the logical state of each net in the logic circuit.

In FIG. 1, in step 104,
Using the logic simulator, a simulation of a logic circuit as a test target of the test pattern targeted by the processing of this flowchart is performed, and one step of the corresponding step of the test pattern is executed.

In step 106, step 104
, The change of the logic state of each net in the logic circuit is detected. In step 106, the number of times of the change of the logical state of the net for which the change of the logical state is detected is counted, and the number is set as the total number of toggles of each net.

In step 108, the above-mentioned step 106
It is determined whether or not the change in the logic state is not observable at the output terminal of the logic circuit for the net in which the change in the logic state is detected.

In step 110, if it is determined that the change in the logic state is not observable at the output terminal of the logic circuit despite the change in the logic state of a certain net, The number of invalid toggles of the net that has changed is counted up.

In step 114, it is determined whether or not the execution of the test patterns performed one by one has all been completed. Note that this step 114 is the same as step 1
It is needless to say that the determination is made as to whether a series of processes from 04 to 110 is completed, and the determination is not limited to the determination of completion of all executions of the target test pattern.

If all test patterns have been completed in step 114, the process proceeds to step 116. on the other hand,
If there is a test pattern that has not been executed, the process branches before step 104, and the series of processes from steps 104 to 114 is executed again.

In step 116, step 106
The number of valid toggles of each net is obtained using the total number of toggles of each net counted up in the step and the number of invalid toggles of each net counted up in step 110.

As described above, the number of effective toggles of each net obtained by such a series of processing corresponds to the number of changes in the logic state of each net which can be observed at the output terminal of the logic circuit. This also corresponds to the fault detection ability of the test pattern in the logic circuit to be tested. Therefore, according to such a test method of a test pattern of a logic circuit, it is possible to obtain information for performing a more effective evaluation of the fault detection capability of the test pattern.

In FIG. 1, in step 116, the number of valid toggles is calculated from the number of invalid toggles and the total number of toggles. However, this may be performed in step 110. However, step 10
In the loop from 4 to 114, obtaining the number of valid toggles according to the number of invalid toggles and the total number of toggles that are not determined increases the overall processing time.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

The embodiment of the present invention is in accordance with the flow chart of FIG. 1, and the determination that the observation is impossible at the step 108 is made by the change of the logic state of the output terminal at the corresponding step during the logic simulation. Go according to the presence or absence. That is, when a test pattern is executed for each step in a logic simulation, if the logic state of a net inside the logic circuit changes and if the logic state of the output terminal of the logic circuit does not change, the logic This is to count up the number of invalid toggles of the net whose state has changed.

FIG. 2 is a logic circuit diagram of an example of a logic circuit as a failure detection target of a test pattern to be tested in the above embodiment.

The logic circuit 10 shown in FIG. 2 is provided with a total of seven input terminals A to F and H and a total of two output terminals X and Y. The logic circuit 10 is provided with a total of five logic gates G1 to G5.

The logic gates G1, G2 are connected to the inputs a, b
Is a two-input AND gate. The logic gate G
3, G5 is a two-input OR gate having inputs a and b. The logic gate G4 is a D-type flip-flop.

These input terminals AF, H, output terminal X,
Y, and between each of the logic gates G1 to G5,
They are connected by n1 to n13. Hereinafter, the numeral portions of the signs of the nets n1 to n13 are referred to as net numbers.

The logic circuit 10 has a logic circuit 1
0 after the manufacture of each of the nets n 1 inside the logic circuit 10.
The change in the logic state of .about.n13 cannot be observed from outside the logic circuit 10. Therefore, each of these nets n 1 to n 1
3 changes in the logic circuit 1
It must be observed from the change in the logic state of the output terminals X and Y of 0.

On the other hand, during the simulation by the logic circuit simulator, the output terminals X, Y
Of the nets n1 to n13 inside the logic circuit 10 can be observed.

The symbols D and C of the logic gate G4
K and CL are input terminals, and symbols Q and QN are output terminals.

The test pattern to be inspected in this embodiment is a pattern of an input signal inputted to each of the inputs A to F and H of the logic circuit 10 in FIG.

FIG. 3 is a diagram showing a table for the number of toggles per net according to the present embodiment.

The toggle number per net table in FIG.
5 is a table in which the total number of toggles, the number of invalid toggles, and the number of valid toggles are written for each net in a logic circuit which is a failure detection target of a test pattern to be inspected in this embodiment.

The values of the total number of toggles, the number of invalid toggles, and the number of valid toggles for each net number in the toggle number table for each net are determined at the start of the test pattern test of this embodiment, that is, the processing of the flowchart of FIG. All 0 at the start of
Is reset to

In the total number of toggles of each net number in the above-mentioned toggle number table for each net, step 106 in FIG.
In each of the nets, the net determined to have a change in the logical state is counted up.

In the number of invalid toggles for each net number, the number of invalid toggles of the net determined to be unobservable in step 110 of FIG. 1 is counted up.

The number of effective toggles of each net number is shown in FIG.
In step 116, the total number of toggles of each net and the number of invalid toggles of each net are obtained from the following equation.

(Number of valid toggles) = (total number of toggles) − (number of invalid toggles) (1)

The numerical values of the toggle number table for each net written in FIG. 3 correspond to the test results of the test performed by the logic circuit 10 of FIG. It is.

FIG. 4 is a diagram showing a test pattern inspection report printed out in this embodiment.

In FIG. 4, the underlined print portion of each item is a portion on which the obtained numerical value or character string of the name is printed.

In FIG. 4, in item 1, the name of the test pattern inspected in the present embodiment is printed.

In item 2, the total number of steps of the test pattern having the test pattern name of item 1 is printed.

Items 3 to 7 respectively include the total number of logic gates, the total number of inputs, the total number of outputs, the total number of paths, and the number of logic circuits whose failure is detected by the test pattern having the test pattern name of item 1 described above. The total number of nets is printed.

Item 8 and Item 9 include the number of nets of the toggle number “0” after execution of all the steps of this test pattern, and the number of nets of the toggle number “0” with respect to the total number of nets of the item 7. , The number of nets with the effective toggle number “0”, and the ratio of the number of nets with the effective toggle number “0” to the total number of nets in item 7 are printed.

In item 10, the names (net numbers) of nets having the number of valid toggles “0” are printed in order.

As described above, according to the embodiment of the present invention, the test pattern inspection report as shown in FIG. 4 including the information according to the data of the effective toggle number of each net in the logic circuit is obtained. Therefore, a more effective evaluation of the fault detection capability of the test pattern can be performed.

The above-described toggle number per net table in FIG. 3 is stored in a memory in the computer system in which the processing shown in the flowchart in FIG. 1 is executed. Write update and read are performed. The logic circuit shown in FIG. 2 is also stored in the computer system by a predetermined means.

[0066]

As described above, according to the present invention, in order to detect a failure of a predetermined logic circuit, the input is input to the input terminal of the logic circuit while observing the output state of the output terminal of the logic circuit. In the test method of the test pattern of the logic circuit, an excellent effect of being able to provide the test method of the test pattern of the logic circuit capable of reporting information for more effective evaluation of the fault detection capability of the test pattern is provided. Have.

[Brief description of the drawings]

FIG. 1 is a flowchart showing the gist of the present invention.

FIG. 2 is a logic circuit diagram of an example of a logic circuit as a failure detection target of a test pattern to be inspected in the embodiment.

FIG. 3 is a diagram showing a toggle number per net table used in the embodiment.

FIG. 4 is a diagram showing a test pattern inspection report printed out from the embodiment.

[Explanation of symbols]

 10: logic circuit, A to F, H: logic circuit input, X, Y: logic circuit output, G1 to G5: logic gate, a, b, D, CK, CL: logic gate input, y, Q, QN Logic gate output, n1 to n13 ... net.

Claims (2)

(57) [Claims] 1. A method for inspecting a test pattern of a logic circuit input to an input terminal of a logic circuit while observing an output state of an output terminal of the logic circuit for detecting a failure of the logic circuit. The test pattern is executed for each step in the simulation, and when the logic state of the net inside the logic circuit changes, it is determined whether or not the change in the logic state cannot be observed at the output terminal of the logic circuit. If it is determined that it is impossible, the number of invalid toggles of the net is counted up, and the number of valid toggles is obtained from the number of invalid toggles and the total number of toggles. An inspection method of a test pattern of a logic circuit, characterized by evaluating. 2. The method according to claim 1, wherein the determination that the observation is not possible is a determination in accordance with the presence or absence of a change in the logic state of the output terminal at a corresponding step in the logic simulation. An inspection method for a test pattern of a logic circuit.