JP2008026074A - Ic test method and ic - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which can diagnose especially the AC characteristics of an I/O section in an IC, for which diagnoses/tests have been conventionally impossible and not performed, in order to reduce percent defective in IC products constituting a storage device, thereby allowing to detect defective components and improve quality. <P>SOLUTION: In an LSI 100, the I/O section 110, which is an object to be diagnosed/tested, is provided outside a local clock section 101. In the configuration where an input buffer section 111 and an output buffer section 121 of interest are sandwiched by FFs 133, 143 of testing common circuit sections 131, 141 and FFs 103, 104 of the local clock section 101, diagnoses/tests are performed using an RAGR 161 and an MISR 162. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique such as LSI (IC: semiconductor integrated circuit device) diagnosis / test, and more particularly to an I / O unit (input / output circuit unit) in an IC constituting a processing circuit of a storage device (disk array device). About diagnosis and testing.

  For example, a gate array IC (or ASIC, custom LSI, etc.) is included as an IC constituting a processing circuit of a conventional storage apparatus. In order to detect a defective product, the IC is subjected to a predetermined diagnosis / test or the like at the stage of manufacture or before shipment. An automatic diagnosis method (BIST method) is used as a means for diagnosing the IC. In the BIST system, an automatic diagnosis / test or the like can be performed by incorporating a diagnosis / test circuit in the target IC.

  For example, in the circuit configuration of the gate array IC, for the gate portion disposed between the flip-flop circuits provided as the diagnosis / test circuit, the delay (propagation delay) contrast, that is, the diagnosis of AC characteristics is performed by the BIST method.・ Testing was possible.

  There are the following problems with the conventional means and method for diagnosis and testing of ICs. In the conventional gate array IC automatic diagnosis method (BIST method), the I / O unit (input / output circuit), particularly its AC characteristics, cannot be automatically diagnosed and is excluded from diagnosis and testing. For this reason, a defect in the I / O portion cannot be detected, which is insufficient as an IC inspection.

  In more detail, the above is as follows. In the circuit configuration of the gate array IC, in the case of the conventional automatic diagnosis method (BIST method), a flip-flop circuit (first test circuit) is provided on the input / output (front / rear) side of the gate portion, and the gate portion is automatically diagnosed. Is possible. However, the I / O part of the IC, that is, the gate part and the circuit such as the input / output buffer outside the first test circuit are automatically diagnosed by the diagnosis / test method and the test circuit arrangement. could not. Particularly, since the I / O unit is not sandwiched between test circuits, it is impossible to perform delay comparison, that is, diagnosis / test of AC characteristics.

  The present invention has been made in view of the above problems, and its purpose is to reduce the defect rate of an IC product used in a storage device or the like in the past by conventional diagnosis / testing (automatic diagnosis) in an IC. In particular, it is possible to diagnose the AC characteristics of I / O units that are not feasible and out of scope, thereby providing a technique capable of detecting defects and improving quality.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. In order to achieve the above object, the present invention provides a method for diagnosing / testing an IC circuit and an IC technology including a diagnostic / test circuit, comprising the following means: . The target IC includes, for example, a gate unit or a logic circuit, and an I / O unit (input / output buffer or the like).

  (1) In this test method and IC, in order to enable diagnosis / test including AC characteristics for the I / O part of the IC, a test circuit (flip of the first (A)) provided outside the gate part, etc. In addition to the first (A) test circuit including a second circuit), a new test circuit (second (B) test circuit including a second (B) flip-flop circuit) is included in the target I / O unit. In addition, the target I / O unit is sandwiched between the first (A) and second (B) test circuits. In this configuration, using test circuits such as a test signal generator and a test signal determiner built in the IC, the AC characteristics (delay contrast) of the target I / O unit are included at the stage of manufacture and before shipment. Carry out diagnosis and test.

  Further, the second test circuit is configured to be shared by a plurality of input / output lines using a switching circuit or the like.

  Further, the second test circuit is configured to be connected to the input / output line using means capable of cutting / cutting off the fuse portion or the like so that it can be disconnected or not used.

  (2) In this test method and IC, in order to enable diagnosis / test including AC characteristics for the I / O part of the IC, a test circuit (first (A The first (A) test circuit including the flip-flop circuit (1) is used, and the target I / O section is defined by the parallel first (A) test circuit and its wiring on one input / output side. The configuration is sandwiched between test circuits of type 1 (A1) and type 2 (A2). In this configuration, a diagnosis / test including AC characteristics for the target I / O unit is performed using a test circuit such as a test signal generator and a test signal determiner built in the IC.

  In addition, a wiring switching circuit is provided for the target I / O unit. By using this switching circuit, the target I / O unit is inserted into the first (A) test circuit for the test execution, and the target I / O unit is disconnected for non-use. The wiring state that is not sandwiched between the test circuits 1 (A) is switched.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. According to the present invention, in order to reduce the defective rate of an IC product used for a storage device or the like, an I / O unit in which diagnosis / testing or the like (automatic diagnosis) in the past has been impossible and excluded from the target. In particular, the AC characteristics can be diagnosed, thereby enabling the detection of defects and improving the quality.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
A first embodiment of the present invention will be described with reference to FIG. In the LSI and the diagnosis / test method of the first embodiment, as features, (1) automatic diagnosis including AC characteristics and the like as a configuration in which the I / O unit is newly sandwiched between test flip-flop circuits (abbreviated as FF)・ A test unit can be implemented, (2) The test FF is configured as a common circuit between a plurality of input / output lines, and (3) The test FF can be separated from the fuse unit. It is a configuration.

  With reference to FIG. 1, the configuration of the LSI 100 according to the first embodiment will be described. The LSI 100 is a gate array IC that constitutes a processing circuit or the like of the storage apparatus. The LSI 100 includes a local clock unit 101, an I / O unit (input / output circuit) 110, test common circuit units 131 and 141, fuse units 151 to 154, RAGR (test signal generator) 161, MISR (test signal determiner). 162 or the like.

<Overall configuration>
(1) First, as a basic configuration, the I / O unit 110 to be diagnosed / tested in the present embodiment includes a first (A) FF (103, 104) and a second circuit which are diagnostic / test circuits. It is the structure inserted | pinched by FF (133,143) of (B). As a result, the I / O unit 110 can perform input / output delay comparison, that is, the AC characteristics can be diagnosed and tested.

  (2) Further, in a configuration in which a test circuit such as the second (B) FF (133, 143) is added to each I / O unit 110 in the basic configuration, a huge number of circuits must be provided. This is a disadvantageous factor such as an increase in the chip size of the LSI 100 more than necessary. Therefore, in this embodiment, in order to minimize the number and size of test circuits such as the second (B) FFs (133, 143), in addition to the basic configuration, the multiplexer 132, the selector 142, etc. In addition, the test circuit including the second (B) FFs 133 and 143 is shared and integrated. That is, for example, in two adjacent input / output lines (L1, L2), a test circuit including a plurality of second (B) FFs 133, 143 and the like are collectively configured as test common circuit units 131, 141. It is. As a result, the number and size of test circuits such as FFs to be added are reduced as compared with the basic configuration due to the common use.

  (3) In addition, the second (B) FFs 133 and 143 and the like (test common circuit units 131 and 141) newly added for testing are unnecessary loads during the actual operation of the LSI 100. For example, the I / O unit 110 in the storage apparatus is a circuit that requires high-speed operation, and it is not desirable to have an unnecessary load. For this reason, since it is necessary or desirable to disconnect the test common circuit portions 131 and 141, in this configuration, as the means for disconnection, the test common circuit portions 131 and 141 having the fuse portions 151 to 154 are provided. A configuration that can be separated is adopted. By cutting the fuse portions 151 to 154 after the test is performed, the test common circuit portions 131 and 141 are disconnected from the main body portion, and an unnecessary load is not generated.

<Configuration of each part>
Each part will be described below. The local clock unit 101 includes a gate unit (logic unit) 102 and FFs (first (A) FF: FF-A) 103 and 104. On the input / output lines (L1, L2, etc.), the input / output of the LSI 100, the I / O unit 110 (the input buffer unit 111 and the output buffer unit 121) are positioned before and after (input / output) outside the local clock unit 101. FFs 103 and 104 are provided at the front and rear (input / output) positions of the gate unit 102 inside the local clock unit 101. Although not shown in the drawings, the same circuit configuration is used for a plurality of input / output lines.

  The gate unit 102 is an array of a plurality of gate elements 10 and is a part where a certain logic circuit (specific application processing circuit) is formed according to a custom wiring design. The FFs 103 and 104 are first (A) test circuits. The FF 103 is arranged in parallel on the input side, and the FF 104 is arranged in parallel on the output side. For example, the first input / output line (L1) includes the FF-A (# 1) 103 on the input side and the FF-A (# 1) 104 on the output side. The second input / output line (L2) includes an FF-A (# 2) 103 on the input side and an FF-A (# 2) 104 on the output side.

  A group of gate elements 10 of the gate unit 102 is sandwiched between the FF 103 and the FF 104 before and after the gate unit 102. The local clock unit 101 operates by inputting a clock (“CLK”) to each of the FFs 103 and 104. Each of the FFs 103 and 104 is connected to a wiring with RAGR 161 and MISR 162 which are test circuits. In the local clock unit 101, automatic diagnosis is possible for the gate unit 102 between the FF 103 and the FF 104 on both input and output sides using the RAGR 161 and the MISR 162 as in the conventional case.

  The I / O unit 110 is divided into an input buffer unit 111 and an output buffer unit 121. On each input / output line, the input buffer unit 111 includes one or more buffers (buffer circuits) 11. Similarly, the output buffer unit 121 includes one or more buffers (buffer circuits) 12.

  On the input / output side of the LSI 100, test common circuit units 131 and 141 are connected between adjacent two input / output lines (for example, L 1 and L 2) through fuse units 151 to 154. The test common circuit units 131 and 141 are configured by sharing a second (B) test circuit between two input / output lines using a switching circuit or the like. The test common circuit units 131 and 141 are arranged at an extra position such as an end of the LSI 100. The fuse portions 151 to 154 are cut by, for example, a laser beam. The disconnecting means is not limited to the fuse portions 151 to 154, and a disconnectable wiring element can be used.

  The first (input side) test common circuit unit 131 includes an FF 133 (FF of the second (B): FF-B) and a multiplexer (output selection circuit) 132. The FF 133 constitutes a second (B) test circuit. The FF 133 has an input from the RAGR 161 and a CLK input, and a multiplexer 132 is connected to the output. Two outputs of the multiplexer 132 are connected to fuse units 151 and 152 connected to input points of the input buffer unit 111 of two adjacent input / output lines (L1 and L2). The multiplexer 132 selects and outputs to two adjacent input / output lines (L1, L2) based on the output of the FF 133.

  The second (output side) test common circuit unit 141 includes an FF 143 (second (B) FF: FF-B) and a selector (input selection circuit) 142. The selector 142 selects two inputs from the fuse units 153 and 154 connected to the output points of the output buffer unit 121 of the adjacent two input / output lines (L 1 and L 2), and outputs them to the FF 143. The FF 143 has an input from the selector 142, a CLK input, and an output to the MISR 162. The selector 142 makes a selection based on the inputs from the two input / output lines (L 1, L 2) and outputs it to the FF 143.

  In each input / output line, the input buffer unit 111 is sandwiched between the second (B) FF 133 in the first test common circuit unit 131 and the first (A) FF 103 on the input side of the local clock unit 101. It is a configuration. Further, the output buffer unit 121 is sandwiched between the first (A) FF 104 on the output side of the local clock unit 101 and the second (B) FF 143 in the second test common circuit unit 141. .

  The RAGR 161 built in the LSI 100 generates and outputs a test signal to the target part, that is, the input terminals such as the FFs 133 and 104, at the time of diagnosis / test execution. The MISR 162 built in the LSI 100 inputs and processes a test signal from the target portion, that is, the output terminals of the FFs 103, 143, etc., at the time of diagnosis / test execution. The result of diagnosis / test is determined by MISR 162.

  The LSI 100 has a plurality of units of the input / output lines L1 in the vertical direction of FIG. 1 (only two lines are shown in this example for simplicity). In the input / output line L1, s11 to s16 and the like represent signal lines and terminals. s11 is an input terminal of the input / output line L1 of the LSI 100 and an input point of the input buffer unit 111. s12 is an output point of the input buffer unit 111 and an input point of the local clock unit 101. s13 is an input point of the gate unit 102. s14 is an output point of the gate unit 102. s15 is an output point of the local clock unit 101 and an input point of the output buffer unit 121. s16 is an output point of the output buffer unit 121 and an output terminal in the input / output line L1 of the LSI 100.

  The I / O unit 110 (the input buffer unit 111 and the output buffer unit 121) arranged at the input / output (front and rear stages) of the local clock unit 101 is a target of diagnosis / test in the present embodiment. In the input buffer unit 111, a portion between the input point (s11) and the output point (s12) is a target of diagnosis / test including AC characteristics. Similarly, in the output buffer unit 121, a portion sandwiched between the input point (s15) and the output point (s16) is a target of diagnosis / test including AC characteristics. Diagnosis and testing can be similarly performed on the input buffer unit 111 side and the output buffer unit 121 side.

<Diagnosis and test method>
A diagnosis / test method in the configuration of the LSI 100 of FIG. 1 will be described. In the present embodiment, automatic diagnosis of the I / O unit 110 can be performed using the BIST method, that is, the RAGR 161 and the MISR 162 which are test circuits mounted on the LSI 100. BIST (Built In Self Test), which is a well-known technology, performs self-diagnosis by LSI by incorporating a random number generator: RAGR (RAndom pattern Generation Register) and a response compressor: MISR (Multiple Input Signature Register) in the LSI. Is. In the BIST method, various combinations of the logical values of the signal lines can be generated in the random number pattern, so high test accuracy is expected even for physical defects other than stuck-at faults. The diagnosis / test is typically performed as a pre-shipment inspection.

  In FIG. 1, an I / O unit 110 (input buffer unit 111, output buffer unit 121) to be diagnosed / tested is replaced with existing first (A) FFs 103, 104 which are test circuits. 2 (B) FFs 133 and 143. In this configuration, the following diagnosis / test is performed. In a stage before shipment of the LSI 100, a predetermined diagnosis / test including diagnosis of AC characteristics of the I / O unit 110 is performed, and if it is determined that there is a problem as a result, it is detected as a defective LSI 100. . A diagnostic pattern (input test signal: e.g., c1) is generated and input from the RAGR 161 to the target portion, for example, the input buffer unit 111 on the first input / output line L1 and the FFs (133, 103) on both sides thereof. A response signal (output test signal: for example, c2) is input and determined in the MISR 162. For example, in the diagnosis of AC characteristics, the propagation delay of the output test signal with respect to the input test signal is diagnosed. In addition, after the predetermined diagnosis / test is completed, the fuse units 151 to 154 are disconnected, so that the test common circuit unit (131, 141) including the second (B) FFs (133, 143) is removed from the main body unit. Separate.

  As described above, according to the first embodiment, in the LSI 100, (1) diagnosis / testing of the AC characteristics and the like of the I / O unit 110 as well as the gate unit 102 can be performed. The circuit size and the like can be suppressed by using a common circuit (second (B) test circuit) or using an existing test circuit (first (A) test circuit). (3) After the test The performance of the actual operation can be ensured by disconnecting the test circuit portion (test common circuit portions 131 and 141) which becomes an unnecessary load.

(Embodiment 2)
Next, a second embodiment of the present invention will be described with reference to FIGS. Unlike the first embodiment, the LSI and the diagnosis / test method of the second embodiment are characterized in that the test circuit FF (corresponding to the second (B) FF 133, 143 in the first embodiment) is replaced with a local clock unit. The test circuit is configured using FFs (corresponding to FFs 103 and 104 of the first (A)) that exist in the local clock unit 101 without being added outside of the local clock unit 101. The wiring at the time of test execution is different from that of the first embodiment.

  With reference to FIG. 2, the configuration of the LSI 100 according to the second embodiment will be described. The LSI 100 includes a gate unit 102 inside the local clock unit 101, an external I / O unit 110, a RAGR 161, a MISR 162, and the like as parts similar to those in the first embodiment. In addition, the LSI 100 includes switching circuits 171 and 172 corresponding to the I / O units 110 outside the local clock unit 101.

<Overall configuration>
As described in the first embodiment, each of the first (A) test circuits FF (106 to 109) sandwiches the gate unit 102 so that the diagnosis and test of the gate unit 102 can be performed. It is a configuration. In the second embodiment, these first (A) FFs (106 to 109) are used for diagnosis / test of the I / O unit 110 by means of wiring or the like.

  As a basic configuration, diagnosis / test is performed by wiring of the first type FF (FF-A1) and the second type FF (FF-A2) and the switching circuits 171 and 172 in the first (A) FFs 106 to 109. It is the structure which inserts | pinches the I / O part 110 used as object of this. For example, the first type FF (FF-A1 # 2) 108, the second type FF (FF-A2 # 1) 106, and the first switching circuit 171 on the input side of the first input / output line L1. In this configuration, the input buffer unit 111 is sandwiched using wiring. Similarly, for example, the first type FF (FF-A1 # 1) 107, the second type FF (FF-A2 # 2) 109, and the second switching circuit on the output side of the first input / output line L1. In this configuration, the output buffer unit 121 is sandwiched by using the wiring 172.

  Under the control of the switching circuits 171 and 172, the I / O unit 110 is diagnosed and tested in a state where it is connected to the terminal on the A side. In the switching circuits 171, 172, the terminal on the A side is a side that is in a wiring state sandwiching the front and rear of the I / O unit 110 by the first (A) FF, and the terminal on the B side is the terminal of the I / O unit 110. This is the side that is in a wiring state where the front and rear are not sandwiched.

  Similarly to the first embodiment, when the LSI 100 is actually used, the state sandwiched by the first (A) FF (first type FF 108 or the like) that is a test circuit is an unnecessary load. Separation / non-use is necessary or desirable. As a means for this, after the test is completed, the wiring is switched to the terminal on the B side under the control of the switching circuits 171 and 172 so that the I / O unit 110 is not caught and the load is reduced.

<Configuration of each part>
In FIG. 2, the local clock unit 101 includes FFs 106, 107, 108, and 109, which are first (A) test circuits, before and after (input / output) the gate unit 102. When these are distinguished according to roles, for example, FF (# 1) 106, FF (# 2) 108, etc. arranged in parallel on the input side of the gate unit 102, in parallel on the output side of the gate unit 102, for example. The FF (# 1) 107, the FF (# 2) 109, and the like are arranged. Further, the first type FFs (FF-A1) 108 and 107 which are upstream of the I / O unit 110 and the second type FFs (FF-A2) 106 and 109 which are subsequent to the I / O unit 110 are included. Each input / output line (L1, L2, etc.) has the same configuration.

  On the input side of the local clock unit 101, for example, in the first input / output line L1, the first type FF (FF-A1 # 2) at the second position in the column of the first (A) FFs (106, 108). ) 108 is connected to the input of the first switching circuit 171. The two switching outputs (A, B) of the first switching circuit 171 are connected to the input / output (s31, s32) of the input buffer unit 111. The output (s32) of the input buffer unit 111 is connected to the input of the second type FF (FF-A2 # 1) 106 at the first position. Similarly, on the output side of the local clock unit 101, the output of the first type FF (FF-A1 # 1) 107 at the first position is connected to the input (s35) of the output buffer unit 121. The input / output (s35, s36) of the output buffer unit 121 is connected to the two switching inputs (A, B) of the second switching circuit 172. The output of the second switching circuit 172 is connected to the input of the second type test FF (FF-A2 # 2) 109 at the second position.

  Each of the first (A) test circuits FFs (106 to 109) has a CLK input and is connected to the RAGR 161 and the MISR 162. “R” represents an input from the RAGR 161, and “M” represents an output to the MISR 162. Although not shown for simplicity, an input / output line by the gate unit 102 is also provided between the first type FF (FF-A1) 108 and the second type FF (FF-A2) 109 in FIG. Exists.

  FIG. 3 shows a configuration example in the switching circuits 171 and 172. In the switching circuit 171, the input “Dat” connected to the first type FF (FF-A1) is connected to the respective outputs “Out” of (A, B) through the two transistors 31 and 32. . Further, the switching circuit 171 has the test control pin 33, and (A, B) is switched based on a control input ("CON") by controlling the test control pin 33 from the outside.

<Diagnosis and test method>
A diagnosis / test method in the configuration of the LSI 100 of FIG. 2 will be described. At the stage before shipment or the like, the terminals of the switching circuits 171 and 172 are set to the A side, and the RAGR 161 and the MISR 162 are set in a state where each I / O unit 110 is sandwiched between the first (A) FFs (106 to 109). Use it to carry out predetermined diagnoses and tests. At the time of implementation, a diagnostic pattern (input test signal) is input from the RAGR 161 to the target site, that is, the first type FF (FF-A1) 108, 107, and the response signal (output test signal) is input to the MISR 162 and judge. After completion of the diagnosis / test, the terminals of the switching circuits 171 and 172 are set to the B side.

  As described above, according to the second embodiment, as in the first embodiment, (1) it is possible to perform diagnosis / test on the AC characteristics and the like of not only the gate unit 102 but also the I / O unit 110 ( 2) The circuit size can be reduced by using the existing test circuit (first (A) test circuit). (3) Also, after the test, the test circuit part that becomes an unnecessary load is separated. The performance of the operation can be ensured.

  For example, the following is possible as other embodiments. In the above-described embodiment, the I / O unit 110 on both sides of the input / output (front and rear) of the local clock unit 101 and all of the plurality of input / output lines can be similarly diagnosed and tested. However, a configuration in which feasible characteristic portions are provided only on one side or only a part of the input / output lines is also possible.

  In addition, the commonization and aggregation of the test circuits in the first embodiment may be configured not only between adjacent input / output lines but also as a group by a plurality of input / output lines.

  Further, the test circuit may be disconnected without leaving the load if the load has no problem with LSI performance.

  Further, the test circuit is not limited to the FF, and other sequential circuit elements may be used.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used for an IC such as a gate array IC having an I / O section.

It is a figure which shows the structure of LSI in Embodiment 1 of this invention. It is a figure which shows the structure of LSI in Embodiment 2 of this invention. It is a figure which shows the structural example of the switching circuit in LSI of Embodiment 2 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Gate element, 11, 12 ... Buffer, 100 ... LSI, 101 ... Local clock part, 102 ... Gate part, 103, 104 ... 1st (A) FF (flip-flop circuit), 106-109 ... 1st ( A) FF (flip-flop circuit), 110... I / O section (input / output circuit), 111... Input buffer section, 121... Output buffer section, 131. ... 2nd (B) FF (flip flop circuit), 141 ... 2nd common circuit for test, 142 ... selector, 143 ... 2nd (B) FF (flip flop circuit), 151 to 154 ... fuse part , 161... RAGR (test signal generator), 162... MISR (test signal determiner), 171, 172.

Claims (7)

An IC test method comprising a gate portion and an input / output circuit portion outside the gate portion,
The IC has a flip-flop circuit serving as a first test circuit outside the gate portion and inside the input / output circuit portion, and a second test circuit outside the input / output circuit portion. In a configuration in which the front and rear of the input / output circuit section are sandwiched between the first and second test circuits,
A test signal is input to the first or second test circuit in the previous stage of the input / output circuit section, and the first or second of the subsequent stage of the input / output circuit section is passed through the input / output circuit section. An IC test method, comprising: testing an AC characteristic of the input / output circuit unit by determining the test signal output from a test circuit. The IC test method according to claim 1, wherein
As the input / output circuit unit, a plurality of input buffer units are arranged in parallel on the input side of the gate unit according to a plurality of input / output lines, and a plurality of output buffer units are arranged in parallel on the output side of the gate unit. Placed in
The first test circuit is disposed on the output side of each of the input buffer units, and the first test circuit is disposed on the input side of each of the output buffer units,
In the plurality of adjacent groups of the input / output lines, the second test circuit is provided on the input side of the input buffer unit using a first switching circuit connected to the group of input / output lines. A first common test circuit including the second test circuit using a second switching circuit connected to the input / output line group on the output side of the output buffer unit. 2 common test circuits are configured,
The input buffer unit and the output buffer unit in the group of input / output lines are tested under the control of the first and second switching circuits of the first and second common test circuits. IC test method. The IC test method according to claim 2, wherein
The switching circuit of the first and second test common circuits is configured to be connected to a point outside the input / output circuit unit on the predetermined plurality of adjacent input / output lines through a fuse unit,
An IC test method, comprising: cutting the fuse portion of the IC determined to have no problem after the test. An IC test method comprising a gate portion and an input / output circuit portion outside the gate portion,
The IC has a flip-flop circuit serving as a first test circuit outside the gate unit and inside the input / output circuit unit, and the first test circuit is connected to the input / output circuit unit. A first type circuit wired to the input side and a second type circuit wired to the output side of the input / output circuit unit; and the first test circuit outside the gate unit And a switching circuit between the input / output circuit unit,
By switching to the first terminal side in the switching circuit, the front and rear of the input / output circuit section are sandwiched between the first type and second type circuits of the first test circuit,
A test signal is input to the first type circuit before the input / output circuit unit, and is output from the second type circuit after the input / output circuit unit via the input / output circuit unit. An IC test method for performing an AC characteristic test of the input / output circuit section by determining a test signal. The IC test method according to claim 4, wherein
By switching to the second terminal side in the switching circuit, the front and rear of the input / output circuit portion are not sandwiched between the first type and second type circuits of the first test circuit,
An IC test method for switching the switching circuit from the first terminal side to the second terminal side for the IC for which it is determined that there is no problem after the test. An IC including a gate portion and an input / output circuit portion outside the gate portion;
A flip-flop circuit serving as a first test circuit outside the gate portion and inside the input / output circuit portion;
A flip-flop circuit serving as a second test circuit outside the input / output circuit section;
A test signal generator for outputting a test signal to the first or second test circuit before the input / output circuit section outside the gate section, and the first or second after the input / output circuit section. A test signal determiner for inputting the test signal from the test circuit of 2;
In a configuration in which the front and rear of the input / output circuit section are sandwiched between the first and second test circuits,
A test signal is input from the test signal generator to the first or second test circuit before the input / output circuit unit, and the input signal after the input / output circuit unit. An IC characterized in that an AC characteristic test of the input / output circuit section is performed by determining the test signal output from the first or second test circuit with the test signal determination unit. An IC including a gate portion and an input / output circuit portion outside the gate portion;
A flip-flop circuit serving as a first test circuit outside the gate portion and inside the input / output circuit portion;
The first test circuit includes a first type circuit wired to the input side of the input / output circuit, and a second type circuit wired to the output side of the input / output circuit,
Outside the gate portion, a switching circuit is provided between the first test circuit and the input / output circuit,
A test signal generator for outputting a test signal to the first type circuit preceding the input / output circuit unit outside the gate unit, and the test from the second type circuit following the input / output circuit unit A test signal determiner for inputting a signal,
By switching to the first terminal side in the switching circuit, the front and rear of the input / output circuit section are sandwiched between the first type and second type circuits of the first test circuit,
A test signal is input from the test signal generator to the first type circuit before the input / output circuit unit, and the second type of the second stage after the input / output circuit unit is passed through the input / output circuit unit. An IC characterized in that an AC characteristic test of the input / output circuit unit is performed by determining the test signal output from a circuit with the test signal determiner.

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