JP2525078B2 - Logic circuit test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] With respect to a logic circuit test apparatus, it is possible to visualize (for example, a print list) the quality results of terminals in net units, and to improve the determination accuracy and the determination efficiency without being influenced by the skill of the determiner. For the purpose of improvement, first storage means for storing the identification information of each terminal of a plurality of logic circuits and the quality judgment result of each terminal in association with each other, and the identification information of all terminals connected to each of the terminals. A second storage unit that stores the data classified by each terminal, and identification information of all the terminals connected to the terminal whose result is “No” among the determination results in the first storage unit is the second storage unit. First extracting means for extracting from the storing means, second extracting means for extracting the determination result of each terminal in the first storing means corresponding to the extracted identification information, and the second extracting means. Judgment extracted by extraction means It is characterized in that it is provided with a third storage means for storing the result and the identification information of the terminal and a visualization means for visualizing the contents of the third storage means.

[Industrial applications]

 The present invention relates to a logic circuit test device.

Generally, the pass / fail judgment test for a single logic circuit is performed by applying a predetermined test pattern to the input terminal of the logic circuit and comparing the pattern appearing at the output terminal with the expected pattern. An output terminal in which a logic different from the expected logic appears is a defective terminal.

On the other hand, in a test for a circuit network composed of a plurality of logic circuits, a pass / fail judgment is made for each terminal of each logic circuit,
Pass / fail judgment is also performed for the wiring network that connects terminals (hereinafter referred to as net). However, since the number of nets is enormous, especially for large-scale integrated circuits, efficient net pass / fail judgment is required. To be done.

[Conventional technology]

As a conventional logic circuit test device of this type, for example,
A circuit network consisting of a plurality of logic circuits is tested (hereinafter referred to as UU
Then, there is a method in which a predetermined test pattern is given to this UUT and the output pattern from the circuit network is compared with the expected pattern to judge the quality of each terminal of the logic circuit.

The quality of the net in such a conventional device is determined artificially by outputting a list of defective terminals and viewing the print list. FIG. 7 is an example of a print list. From the left, the logic circuit number (LOC.), The defective terminal number (PIN), and the input / output of that terminal (IN / OUT) are arranged. The judge compares the printed list with the wiring diagram to find the defective portion of the net connected to the defective terminal.

For example, if one net is as shown in FIG.
If only one terminal "UB01-10" in the net is defective, it is determined that the defective portion (disconnected portion in this case) of the net is the mark X in FIG.

[Problems to be Solved by the Invention]

However, in such a conventional logic circuit test device, since the net defect location is artificially determined, it is easy to overlook when collating the print list with the wiring diagram, and the determination accuracy is poor. There were various problems such as being easily influenced by the skill of the judge and having a poor judgment efficiency.

The present invention has been made in view of such a problem, and can visualize the result of quality of a terminal for each net (for example, a print list), and the determination accuracy and the determination efficiency can be obtained without being influenced by the skill of the determiner. Is intended to improve.

[Means for solving the problem]

In order to achieve the above object, the present invention relates to a principle configuration diagram thereof, as shown in FIG. 1, in which identification information of each terminal of a plurality of logic circuits and a pass / fail judgment result of each terminal are stored in association with each other.
The storage means, the second storage means for storing the identification information of all the terminals connected to each of the terminals classified by the terminal, and the result of the determination results in the first storage means is " Regarding the first extracting means for extracting the identification information of all the terminals connected to the terminal which is "No" from the second storing means, and each terminal in the first storing means corresponding to the extracted identification information. A second extraction means for extracting the determination result, a third storage means for storing the determination result extracted by the second extraction means and the identification information of the terminal, and the contents of the third storage means And a visualizing means for visualizing [Operation] In the present invention, based on the identification information of the terminal of the determination result is "no", identification information of all the terminals connected to the terminal Corresponding to the extracted identification information The determination result of the terminal is visualized (e.g. printing list).

Therefore, all terminals connected to one terminal, that is, the determination results for each net are visually recognized collectively.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

2 to 6 are views showing an embodiment of the logic circuit test apparatus according to the present invention.

First, the system configuration will be described. In FIG. 2, 1
0 and 11 are storage devices. One of the storage devices 10 stores a "parts / pin table (abbreviation, PT)", and the other storage device 11 stores a "net connection table (abbreviation, NT)". FIG. 3 is a conceptual diagram of PT and NT.

PT is each logic circuit (also called parts) that makes up the UUT
The terminal (also referred to as a pin) number of each logic circuit is stored. It is composed of a parts table and a pin table, and one pin table stores all terminal information (physical pin numbers) of one logic circuit. The pin table is referenced by the table address pointer in the parts table. That is, the terminal information of the logic circuit can be searched by checking the pointer for each logic circuit in the parts table.

On the other hand, NT stores all the net connection information in the UUT. One net connection information contains the number of terminals connected to the net, the pointer number of the parts table corresponding to each terminal (each logic circuit). Information), a pin table serial number on the part (indicates each terminal), and the like.

Here, NT is referenced by a pointer in PT. For example, the content of the pointer adjacent to the physical pin number (10) in the pin table is "# 1500", which points to the address 1500 of NT. That is, the net information connected to the terminal (for example, No. 10) of any logic circuit (for example, UB01) is stored in the area starting from the address “# 1500” in NT.

For example, when performing a table search for the terminal (10) of the logic circuit (UB01), UB01 → pointer on the parts table (# 100) → pointer on the pin table (# 1500) → on the net connection table The address 1500 is searched, and in this case, the net information connected to "UB01-10" is referred to.

Therefore, storage devices 10, 11 for storing PT and NT
Together constitute the second storage means 12.

14 is a control computer, which controls each part of the system and extracts the input test pattern and the expected pattern for each UUT from the storage devices 10 and 11 (or another storage device) in response to a request from the tester 15. Tester 15
Processing for receiving the fail information (described later) from the tester 15 and generating a list in a predetermined net unit. Therefore, the control computer 14 has a bus 16
Through CPU memory 17, output device for printers and display devices 1
8 and tester 15 are connected.

Here, the control computer 14 functions as a first extraction means and a second extraction means, the CPU memory 17 functions as a third storage means, and the output device 18 functions as a visualization means.

The tester 15 has an interface device 19 for exchanging various data with the control computer 14, an input pattern memory 20 for holding an input pattern, an expected pattern memory 21 for holding an expected pattern, an output pattern from the UUT and an expected pattern. A pass / fail judgment circuit 22 for comparing and judging whether a terminal is good or bad for each logic circuit constituting the UUT, and a fail pattern memory 23 as a first storage means for storing the good / bad judgment result and terminal identification information in association with each other .

The data (fail information) structure in the fail pattern memory 23 is shown in FIG. One bit of information corresponds to one terminal, and a plurality of consecutive bits correspond to one logic circuit. Here, it is assumed that when the bit content is “0”, the determination result is “good”, and when the bit content is “1”, it is “no”.

In the example of FIG. 4, the terminal "1" of the logic circuit "UB01" is
The determination result of the terminal "5" (bit 8) of "0" (bit 5) and "UC03" is "no".

Each bit of fail information is associated with table information in the second storage unit 12. That is, a plurality of consecutive bits corresponding to one logic circuit correspond to a pin table address pointer on the parts table, and each bit corresponds to a physical pin number on the pin table. Therefore, the table information of each terminal can be extracted based on the bit number of the fail information.

 Next, the operation will be described.

In the pass / fail judgment test for the UUT, first, the input pattern and the expected pattern are written in the memories 20 and 21, and the input pattern in the memory 20 is given to the UUT. The output pattern from the UUT is compared with the expected pattern by the pass / fail judgment circuit 22, and the comparison result is written in the fail pattern memory 23.

When the test for the UUT is completed, the output process of the net connection is executed next. FIG. 5 is a flowchart of the processing.

First, in step S ₁ , if the fail information is checked and there is no “failure”, that is, if there is no defect detection terminal, the process ends, or if even one “failure” is detected, Reads the fail information from the tester 15 and develops it in the CPU memory 17 in step S ₂ . Then, sequentially inspect each bit of fail information in step S _3, the determination result is to find the bit number of "unnecessary".

Then, the intra-net terminal information extraction process (step S ₄ ) is executed based on the retrieved bit number. This extraction process first refers to the parts table according to the bit number of the underlying terminal, then refers to the pin table with the pin table address pointer in the parts table as a clue, and then the pin table within the pin table. Net connection table Use the address pointer as a clue to refer to the net connection table. That is, based on the bit number of "fail" in the fail information, a hierarchical search is performed to the parts table, pin table, and net connection table, and from the net connection table of the lowest layer to the "no" terminal. Identification information (pin numbers) of all terminals to be connected is sequentially extracted.

Next, it is determined the completion of net information extraction for all "No" terminal in the fail information at step S _5, if not completed, the process proceeds to step S _6, the extracted terminal information and the CPU
The fail information in the memory 17 is collated. Then, the determination result is "good" path marks (e.g., blank) to the terminals of subjecting (step S ₇₎ on the other hand, terminals fail mark "unnecessary" (e.g., * asterisk) subjected (step S _8), after transferred to the terminal information with these marks to another area in the CPU memory 17 to erase the fail mark subjected to fail information at step S _9.

In this way, when the above processing is completed for the terminals connected to all the “NO” terminals of the fail information, the determination result of step S ₅ becomes YES, and the determination result of step S ₁₀ becomes NO. proceeds to step S _11, CPU memory
Transfer the data stored in another area in 17 to the output device 18,
For example, a print list is output.

FIG. 6 is an example of the printed list that has been launched and shows the xxxxth net connection list. In this example, the fail mark (*) is added to the terminal “10” having the logical number “UB01”.

That is, in this net, the terminal "2" of the logic circuit "UA01" is connected to the terminal "10" of the logic circuit "UB01" and the terminal "50" of the logic circuit "UB02", and the terminal "UB01" is connected. Since only "10" is defective, it is determined that the wiring connected to the terminal 10 of this "UB01" has a cut point (eighth).
See the fault circuit model in the figure).

As described above, according to the present embodiment, based on the fail information of the UUT, it is possible to output the terminal information in net units as a print list, and refer to this print list to make a pass / fail judgment for each net. You can Therefore, it is possible to minimize the matching work with the wiring diagram,
The determination accuracy and the determination efficiency can be improved without being influenced by the skill of the determiner.

Although the print list is output in the above embodiment, the print list is not limited to this, and may be displayed on the display, for example. The point is to visualize it so that it can be visually confirmed.

〔The invention's effect〕

According to the present invention, the quality result of terminals can be visualized for each net (for example, a print list), and the determination accuracy and the determination efficiency can be improved without being influenced by the skill of the determiner.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a principle configuration diagram of the present invention, FIGS. 2 to 6 are diagrams showing an embodiment of a logic circuit test apparatus according to the present invention, and FIG. 2 is a system configuration diagram thereof. 3 is a conceptual diagram of the table, FIG. 4 is a structural diagram of the fail information, FIG. 5 is a flowchart of the net information output processing, and FIG. 6 is a print list thereof. 7 and 8 are diagrams showing a conventional example, FIG. 7 is a print list thereof, and FIG. 8 is a model diagram of the faulty circuit. 12 ... Second storage means, 14 ... Control computer (first extraction means, second extraction means), 17 ... CPU memory (third storage means), 18 ... Output device (visualization means) ), 23 ... Fail pattern memory (first storage means).

Claims (1)

(57) [Claims] 1. A first storage means for storing identification information of each terminal of a plurality of logic circuits and a quality judgment result of each terminal in association with each other, and identification information of all terminals connected to each of the terminals. Second storage means for classifying and storing for each terminal, and identification information of all the terminals connected to the terminal whose result is “No” among the determination results in the first storage means, the second storage First extracting means for extracting from the means, second extracting means for extracting the determination result of each terminal in the first storing means corresponding to the extracted identification information, and the second extracting means. A logic circuit test comprising: a third storage means for storing the determination result extracted by the above and the terminal identification information; and a visualization means for visualizing the contents of the third storage means. apparatus.