CN115293084A - Gate-level netlist clock domain crossing automatic analysis method and system - Google Patents
Gate-level netlist clock domain crossing automatic analysis method and system Download PDFInfo
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- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G06F30/32—Circuit design at the digital level
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- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
Abstract
A cross-clock domain automatic analysis method and a system of a gate-level netlist are disclosed, which comprises a simulation library automatic abstraction module, a Verilog program analysis module, a gate-level netlist clock tree and reset tree inference module, a cross-clock domain feature recognition module and an illegal display module, wherein the steps of Verilog language analysis, simulation library automatic abstraction, gate-level netlist clock tree inference, gate-level netlist reset tree inference, cross-clock domain feature circuit recognition and illegal display are performed, the cross-clock domain risk of the gate-level netlist of a programmable logic design can be analyzed by a static analysis method, the design defect is accurately positioned, and the reliability of the programmable logic design is improved.
Description
Technical Field
The invention relates to a cross-clock-domain automatic analysis method and a cross-clock-domain automatic analysis system for a gate-level netlist, and belongs to the field of cross-clock-domain analysis in the field of FPGA (field programmable gate array) or integrated circuit design.
Background
The current digital circuit design usually includes a plurality of clock domains (average 4-7 clock domains), and these clocks are either directly introduced from external pins, or the master clock is frequency-divided and frequency-multiplied by RTL code inside the digital circuit chip such as FPGA, or the PLL/DLL/DCM/CMT/MMCM inside the FPGA chip is directly used for frequency-dividing, frequency-multiplying and phase-shifting. These different clocks will act on different functional areas inside the chip, and there will be more control signals and data signals transmitted between different functional areas, so how to ensure that the signal of the high frequency clock domain is transmitted to the low frequency clock domain completely, correctly and timely, which requires the designer to correctly add a synchronization circuit at each signal intersection. If the added synchronous circuit is incorrect or no synchronous circuit is added, the problem of signal metastable state can be caused, the metastable state problem is difficult to expose in the process of normal functional simulation and static time sequence simulation, the metastable state problem is remained in the design until being loaded into an FPGA device, and the device has frequent and difficult-to-understand abnormal function phenomena during running, so that a designer has to spend a great deal of time for problem positioning and repairing. The structure of the RTL code can be rapidly, automatically and comprehensively checked by using the CDC checking and repairing suggestion technology, the clock domain crossing signal transmission problem is analyzed, a designer can locate, verify and repair CDC defects in the design earlier, project progress is accelerated, and the reliability of the product is really improved.
The gate-level logic circuit is the final working form of the digital integrated circuit design, contains all information of the whole design, expands the object of CDC analysis to the gate-level logic circuit, and can confirm the design correctness aiming at the final design result.
Large-scale digital integrated circuit designs are classified by the degree of abstraction, from high to low, into functional designs, algorithm-level/micro-architecture designs, register transfer-level designs, gate-level designs, and physical-level designs. The gate level design is the main design level of the traditional digital device, the product is large-scale digital integrated circuit gate level logic, all the design function information is contained, and the final expression form of the logic design carried by the programmable logic device (FPGA, CPLD) is also provided.
At present, the cross-clock domain automatic analysis method for the programmable logic design gate-level netlist does not have patents and articles in the same direction at home and abroad, but related patents and articles exist.
The Langchao electronics information industry Co., ltd CN201510015597.1 discloses a cross-clock domain logic ASIC verification system and method based on metastable state injection, which is characterized in that the structure comprises: clock domain crossing logic of a single modular design on a system on chip; the parameterization configuration unit realizes flexible configuration of parameters of a metastable state signal and synchronous logic, wherein the parameters comprise: triggering clock period and phase shift of cross-clock signals, error threshold and randomization of metastable state signals, establishing and maintaining time and initializing parameters of a synchronous register; meanwhile, the logic structure integrated by the parameterization configuration unit adjusts effective asynchronous signals and logic factors of the cross-clock domain logic according to set parameter values; the ASIC logic analysis unit is used for determining network nodes which are easy to generate logic errors by analyzing the propagation of clock domain crossing signals in the ASIC logic, and the network nodes are listed as key nodes for functional verification, so that the logic tracking of the clock domain crossing logic signals is realized; the key node verification unit is used for verifying elements including modularized excitation data, verification results, signal attributes and assertions, and realizing data monitoring and result recording of cross-clock-domain signals; and verifying a matching file, associating the parameterized configuration unit and the key node verification unit with the cross-clock-domain logic of the system on chip, and performing embedded verification on the cross-clock-domain logic.
The traditional model checking method facing the cross-clock domain design does not fully consider the integrity problem of circuit characteristic description, however, the complete circuit characteristic is the basis of the model checking effectiveness, and the incomplete circuit characteristic description can possibly hide the design error; the results of experiments on two typical cross-clock domain designs show that the method not only can achieve 100% of circuit characteristic coverage rate, but also can find functional errors hidden by the traditional method.
In summary, on one hand, it can be determined whether the design has a clock domain crossing problem only by performing clock domain crossing analysis on the final gate-level circuit; on the other hand, a cross-clock domain automated analysis method for programmable logic design gate-level netlists is still blank.
Disclosure of Invention
The invention solves the technical problems that: aiming at the clock domain crossing problem which is difficult to find in the code design stage, product delivery test and test links in the prior art, a method and a system for automatically analyzing a gate-level netlist and the clock domain crossing are provided.
The technical problem to be solved by the invention is realized by the following technical scheme:
a method for automatically analyzing a gate-level netlist across clock domains comprises the following steps:
abstract processing is carried out on the simulation library file;
acquiring a gate-level netlist design structure according to the abstract processing result;
extracting a clock tree and a reset tree of the gate-level netlist in the gate-level netlist design structure;
performing cross-clock domain behavior analysis according to the extraction result;
and matching the analysis result with the common cross-clock domain fault mode and synchronization mode information to obtain the designed violation information, and displaying the violation information.
The concrete steps of the abstraction processing are as follows:
loading simulation library files of devices designed by the programmable logic design gate-level netlist, performing language analysis on Verilog and VHDL simulation libraries respectively, and storing corresponding analysis results into a symbol table for subsequent clock domain crossing automatic analysis;
extracting corresponding module attributes in the simulation library file according to the description of the simulation library file, confirming the register driving clock, the reset signal, the enable signal and the output input port according to logic combination, and abstracting and processing basic component pins in the simulation library;
classifying according to the functions of basic elements, storing information of the basic elements, identifying design ports of the basic elements through statement characteristics, storing input ports and output ports into an input and output port list, identifying the basic elements according to a hierarchical structure, identifying the types of the elements through the identification names of the basic elements, extracting, registering and storing the types of the elements into a register list, extracting logic combination elements in the basic elements and storing the logic combination elements into a logic connection list, identifying the register list and the elements outside the logic connection list, identifying the types of other elements and storing identification results into a corresponding list according to the ports, the registers and the logic classification.
The specific steps of obtaining the gate-level netlist design structure are as follows:
screening the Verilog design files to prevent error file input, performing syntactic analysis on the Verilog design files, establishing a module mapping model, confirming the expression of the connection mode in the Verilog design files, and establishing a module connection model according to the analysis result of the Verilog design files for expressing the connection relation between a port and a device and between the device and the device.
The specific steps of inferring the clock tree of the gate-level netlist through the gate-level netlist clock tree and the reset tree inference module are as follows:
according to data results output by a Verilog program analysis module and a simulation library automatic abstraction module, deducing a clock tree through a gate-level netlist clock tree and a reset tree deduction module, traversing clock pins of all registers and latches, applying a stored logical connection relation, tracing the tail end of any pin which can be connected, inputting the clock pin of any register, and acquiring a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port;
judging the property of the terminal signal of any pin, if the terminal of the pin is an external interface, the interface is the input of a clock domain; if the terminal is the output end of the register, tracing the input clock of the register; if the terminal is a half latch, discarding the clock path;
and forming a list by the clock domain of the terminal according to the port name index.
The specific steps of inferring the reset tree of the gate-level netlist through the gate-level netlist clock tree and the reset tree inference module are as follows:
traversing all reset pins of the registers and the latches, tracing the tail end to which any pin can be connected through a stored logic connection relation list, and acquiring a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port;
judging the property of a terminal signal, and if the terminal is an external interface, considering the interface as an input controlled by a reset signal; if the terminal is the output end of the register, tracing the input reset of the register; if the terminal is a half latch, abandoning the reset path;
and forming a list by indexing the reset signal influence domain of the terminal according to the port name.
The specific method for analyzing the clock domain crossing behavior by using the clock domain crossing feature recognition module comprises the following steps:
analyzing the clock domain crossing behavior by using data output by a clock tree and reset tree inference module and a clock domain crossing characteristic identification module, analyzing the clock domain signal crossing, inferring out a register of which the clock domain is different from the clock domain of the input signal, and taking the input of the register as a preliminary pre-judged clock domain crossing path;
identifying a characteristic circuit in which a combinational logic exists in a clock-crossing domain path, the combinational logic exists behind a first-stage synchronizer, and the clock-crossing path is correctly optimized;
and recording and searching the characteristic circuit path, and storing the illegal path.
The characteristic circuit is specifically as follows:
the circuit comprises a two-stage synchronization circuit, a clock domain crossing circuit path and a clock domain crossing synchronization inter-register path combinational logic circuit, wherein:
the two-stage synchronization circuit comprises 3 registers, a Clk1 clock domain register inputs a clock domain signal, the clock domain signal passes through a 2-stage register to eliminate metastable state influence, the clock domain signal is obtained by a last-stage clock domain register and has no logic combination, the clock domain signal is used after the Clk2 clock domain signal is subjected to two-stage register synchronization processing, and the clock domain signal is a single-bit signal after the first-stage synchronization.
The clock domain crossing circuit path specifically comprises:
the logic gate has logic combination after the clock domain signal is generated and is acquired by another clock domain register, and the logic gate outputs the clock domain signal after the clock domain signal passes through at least one stage of logic gate and is subjected to synchronization processing of at least two stages of clock domain registers in the Clk2 clock domain.
The cross-clock domain synchronization inter-register path combinational logic circuit comprises:
after clock domain signals are generated, the signals are acquired by another clock domain register and then output to another clock domain register, logic combination exists in the logic gates after passing through at least one stage of logic gates, and the signals are output after being subjected to synchronization processing of at least two stages of clock domain registers in a Clk2 clock domain.
The utility model provides a gate-level netlist clock domain automation analysis system across, includes simulation library automatic abstraction module, verilog program analysis module, gate-level netlist clock tree and reset tree inference module, clock domain feature identification module across, violation display module, wherein:
loading a simulation library file of a device designed by the programmable logic design gate-level netlist by the simulation library automatic abstraction module, performing language analysis on the Verilog simulation library and the VHDL simulation library respectively, and storing a corresponding analysis result into a symbol table for subsequent clock domain crossing automatic analysis; extracting corresponding module attributes in the simulation library file according to the description of the simulation library file, confirming a register driving clock, a reset signal, an enable signal and an output input port according to logic combination, and abstracting and processing basic component pins in the simulation library; classifying according to functions of basic components, storing information of the basic components, identifying design ports of the basic components through statement characteristics, storing input ports and output ports into an input and output port list, identifying the basic components according to a hierarchical structure, identifying device types through identification names of the basic components, extracting, registering and storing into a register list, extracting logic combination devices in the basic components and storing into a logic connection list, identifying devices outside the register list and the logic connection list, identifying other device types and storing identification results into a corresponding list according to the ports, the registers and the logic classification;
screening the Verilog design files by a Verilog program analysis module, preventing error file input, carrying out syntactic analysis on the Verilog design files, establishing a module mapping model, confirming the expression of a connection mode in the Verilog design files, and establishing a module connection model according to the analysis result of the Verilog design files for expressing the connection relationship between a port and a device and between the device and the device;
according to data results output by the Verilog program analysis module and the simulation library automatic abstraction module, the gate-level netlist clock tree and reset tree inference module infers the clock tree through the gate-level netlist clock tree and reset tree inference module, traverses clock pins of all registers and latches, applies stored logic connection relation, traces back the tail end of any pin which can be connected, inputs the clock pin of any register, and acquires a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port; judging the property of the terminal signal of any pin, if the terminal of the pin is an external interface, the interface is the input of a clock domain; if the terminal is the output end of the register, tracing the input clock of the register; if the terminal is a half latch, discarding the clock path; forming a list by indexing the clock domain of the terminal according to the port name; simultaneously traversing all the reset pins of the registers and the latches, tracing the tail end to which any pin can be connected through a stored logic connection relation list, and acquiring a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port; judging the property of the terminal signal, and if the terminal is an external interface, considering the interface as an input controlled by a reset signal; if the terminal is the output end of the register, tracing the input reset of the register; if the terminal is a half latch, abandoning the reset path; forming a list by indexing the reset signal influence domain of the terminal according to the port name;
the cross-clock domain feature recognition module analyzes the cross-clock domain behavior by using the data output by the clock tree and reset tree inference module, analyzes the clock domain signal intersection, infers a register with a clock domain in which the register is located and a clock domain of an input signal, and takes the input of the register as a preliminarily pre-judged cross-clock domain path; identifying a characteristic circuit which has combinational logic in a clock-crossing domain path, combinational logic in the first-stage synchronizer and correct optimization processing in the clock-crossing path; recording and retrieving a characteristic circuit path, and storing the illegal path;
and the violation display module displays the violation path.
Compared with the prior art, the invention has the advantages that:
(1) The cross-clock-domain automatic analysis method and the cross-clock-domain automatic analysis system for the gate-level netlist can check the problem that cross-clock risks cannot be found only by CDC (sequence control library) check aiming at RTL (real time language) codes by using a traditional cross-clock-domain check tool. Because the problems are not easy to find in the code design stage and the product delivery test and test links, the invention can avoid the severe consequences caused by the abnormal operation of the equipment due to the metastable state transmission of the product during the application;
(2) According to the invention, through a gate-level netlist clock domain-crossing secondary synchronization circuit automatic analysis method, the problem that register copying is carried out on a synchronizer after comprehensive layout and wiring of RTL design clock domain-crossing synchronization design in the prior art so as to cause metastable state sampling window expansion can be checked, and validity check of the synchronizer designed in RTL codes after layout and wiring is realized;
(3) Through the automatic analysis method of the clock domain-crossing and clock domain-crossing circuit paths of the gate-level netlist, the problem that the clock domain-crossing circuit paths have combinational logic problems due to the fact that a certain bit in a state machine register in the RTL code is set as an output to be processed in a clock domain-crossing mode in the prior art and the coding mode is changed into a gray mode after synthesis can be detected, and the clock domain-crossing circuit paths designed in the RTL code after layout and wiring are judged;
(4) By the automatic analysis method of the path combinational logic circuit between the cross-clock domain and cross-clock domain synchronization registers of the gate-level netlist, the problem that in the prior art, the optimization setting of the synthesizer cannot be judged to be timing, the problem of cross-clock error processing error is caused by moving the edge judgment logic from the synchronizer to the front of the synchronizer, and the detection of cross-clock domain failure caused by optimization options of the synthesizer is realized.
Drawings
FIG. 1 is a schematic flow chart of a cross-clock-domain automated analysis method for a programmable logic design gate-level netlist provided by the present invention;
FIG. 2 is a flow diagram of the principles of automatic abstraction of a simulation library provided by the present invention;
FIG. 3 is a schematic flowchart of a clock tree inference principle for a gate level netlist provided by the present invention;
FIG. 4 is a schematic diagram of a two-stage synchronization circuit provided in the present invention;
FIG. 5 is a schematic diagram of a clock domain crossing circuit provided by the present invention;
FIG. 6 is a schematic diagram of a cross-clock domain synchronous inter-register path combinational logic circuit provided in the present invention;
Detailed Description
A clock domain crossing automatic analysis method and system of the gate-level netlist, analyze the clock domain crossing risk of the design gate-level netlist of programmable logic and carry on the accurate positioning to the design defect through the method of the static state analysis, have improved the design reliability of programmable logic, the system makes up and includes the automatic abstraction module of simulation library, verilog program analysis module, gate-level netlist clock tree and reset tree inference module, clock domain characteristic identification module, violation display module of crossing, specifically:
loading a simulation library file of a device designed by the programmable logic design gate-level netlist by the simulation library automatic abstraction module, performing language analysis on the Verilog simulation library and the VHDL simulation library respectively, and storing a corresponding analysis result into a symbol table for subsequent clock domain crossing automatic analysis; extracting corresponding module attributes in the simulation library file according to the description of the simulation library file, confirming the register driving clock, the reset signal, the enable signal and the output input port according to logic combination, and abstracting and processing basic component pins in the simulation library; classifying according to the functions of basic components, storing information of the basic components, identifying design ports of the basic components through statement characteristics, storing input ports and output ports into an input and output port list, identifying the basic components according to a hierarchical structure, identifying the types of the components through the identification names of the basic components, extracting, registering and storing the types of the components into a register list, extracting logic combination devices in the basic components and storing the logic combination devices into a logic connection list, identifying the register list and devices outside the logic connection list, identifying the types of other devices and storing identification results into a corresponding list according to the ports, the registers and the logic classification;
screening the Verilog design files by a Verilog program analysis module, preventing error file input, carrying out syntactic analysis on the Verilog design files, establishing a module mapping model, confirming the expression of a connection mode in the Verilog design files, and establishing a module connection model according to the analysis result of the Verilog design files for expressing the connection relationship between a port and a device and between the device and the device;
according to data results output by the Verilog program analysis module and the simulation library automatic abstraction module, the gate-level netlist clock tree and reset tree inference module infers the clock tree through the gate-level netlist clock tree and reset tree inference module, traverses clock pins of all registers and latches, applies stored logic connection relation, traces back the tail end of any pin which can be connected, inputs the clock pin of any register, and acquires a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port; judging the property of the terminal signal of any pin, wherein if the terminal of the pin is an external interface, the interface is the input of a clock domain; if the terminal is the output end of the register, tracing the input clock of the register; if the terminal is a half latch, abandoning the clock path; forming a list by the clock domain of the terminal according to the port name index; simultaneously traversing all the reset pins of the registers and the latches, tracing the tail end to which any pin can be connected through a stored logic connection relation list, and acquiring a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port; judging the property of the terminal signal, and if the terminal is an external interface, considering the interface as an input controlled by a reset signal; if the terminal is the output end of the register, tracing the input reset of the register; if the terminal is a half latch, abandoning the reset path; forming a list by indexing the reset signal influence domain of the terminal according to the port name;
the cross-clock domain feature recognition module analyzes the cross-clock domain behavior by using the data output by the clock tree and reset tree inference module, analyzes the clock domain signal intersection, infers a register of which the clock domain is different from the clock domain of the input signal, and takes the input of the register as a preliminarily pre-judged cross-clock domain path; identifying a characteristic circuit in which a combinational logic exists in a clock-crossing domain path, the combinational logic exists behind a first-stage synchronizer, and the clock-crossing path is correctly optimized; recording and retrieving a characteristic circuit path, and storing the illegal path;
and the violation display module displays the violation path.
According to the gate-level netlist clock domain crossing automatic analysis system, the analysis steps are as follows:
(1) Carrying out abstract processing on the simulation library file through a simulation library automatic abstract module aiming at the simulation library file;
the concrete steps of the abstraction processing are as follows:
loading simulation library files of devices designed by the programmable logic design gate-level netlist, performing language analysis on Verilog and VHDL simulation libraries respectively, and storing corresponding analysis results into a symbol table for subsequent cross-clock-domain automatic analysis;
extracting corresponding module attributes in the simulation library file according to the description of the simulation library file, confirming a register driving clock, a reset signal, an enable signal and an output input port according to logic combination, and abstracting and processing basic component pins in the simulation library;
classifying according to functions of basic components, storing information of the basic components, identifying design ports of the basic components through statement characteristics, storing input ports and output ports into an input and output port list, identifying the basic components according to a hierarchical structure, identifying device types through identification names of the basic components, extracting, registering and storing into a register list, extracting logic combination devices in the basic components and storing into a logic connection list, identifying devices outside the register list and the logic connection list, identifying other device types and storing identification results into a corresponding list according to the ports, the registers and the logic classification;
(2) Acquiring a gate-level netlist design structure by a Verilog program analysis module aiming at the gate-level netlist file;
the specific steps for obtaining the gate-level netlist design structure are as follows:
screening the Verilog design files to prevent error file input, performing syntactic analysis on the Verilog design files, establishing a module mapping model, confirming the expression of a connection mode in the Verilog design files, and establishing a module connection model according to the analysis result of the Verilog design files for expressing the connection relation between a port and a device and between the device and the device;
(3) Extracting clock trees and reset trees of the gate-level netlist through a gate-level netlist clock tree and reset tree inference module for output results of the Verilog program analysis module and the simulation library automatic abstraction module;
the specific steps of inferring the clock tree of the gate-level netlist through the gate-level netlist clock tree and the reset tree inference module are as follows:
according to data results output by a Verilog program analysis module and a simulation library automatic abstraction module, deducing a clock tree through a gate-level netlist clock tree and a reset tree deduction module, traversing clock pins of all registers and latches, applying a stored logical connection relation, tracing the tail end of any pin which can be connected, inputting the clock pin of any register, and acquiring a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port;
judging the property of the terminal signal of any pin, if the terminal of the pin is an external interface, the interface is the input of a clock domain; if the terminal is the output end of the register, tracing the input clock of the register; if the terminal is a half latch, abandoning the clock path;
forming a list by the clock domain of the terminal according to the port name index;
the specific steps of inferring the reset tree of the gate-level netlist through the gate-level netlist clock tree and the reset tree inference module are as follows:
traversing all reset pins of the registers and the latches, tracing the tail end to which any pin can be connected through a stored logic connection relation list, and acquiring a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port;
judging the property of a terminal signal, and if the terminal is an external interface, considering the interface as an input controlled by a reset signal; if the terminal is the output end of the register, tracing the input reset of the register; if the terminal is a half latch, abandoning the reset path;
forming a list by indexing the reset signal influence domain of the terminal according to the port name;
(4) Analyzing the cross-clock domain behavior by using a cross-clock domain feature recognition module according to the extraction result obtained in the step (3);
the specific method for analyzing the cross-clock domain behavior by using the cross-clock domain feature recognition module comprises the following steps:
analyzing the clock domain crossing behavior by using data output by a clock tree and reset tree inference module and a clock domain crossing characteristic identification module, analyzing the clock domain signal crossing, inferring out a register of which the clock domain is different from the clock domain of the input signal, and taking the input of the register as a preliminary pre-judged clock domain crossing path;
identifying a characteristic circuit in which a combinational logic exists in a clock-crossing domain path, the combinational logic exists behind a first-stage synchronizer, and the clock-crossing path is correctly optimized;
recording and retrieving a characteristic circuit path, and storing the illegal path;
the characteristic circuit specifically comprises:
the circuit comprises a secondary synchronization circuit, a clock domain crossing circuit path and a clock domain crossing synchronization inter-register path combinational logic circuit, wherein:
the second-stage synchronizing circuit comprises 3 registers, a Clk1 clock domain register inputs a clock domain signal, the clock domain signal is subjected to metastable state elimination through a 2-stage register and is acquired by a last-stage clock domain register without logic combination, the clock domain signal is used after being subjected to two-stage register synchronization processing in a Clk2 clock domain, and the clock domain signal is a single-bit signal after being subjected to first-stage synchronization;
the clock domain crossing circuit path is specifically as follows:
the logic gate has logic combination after passing through at least one stage of logic gate, and is output after the clock domain signal is generated and is subjected to synchronization processing by at least two stages of clock domain registers in a Clk2 clock domain;
the cross-clock domain synchronization inter-register path combinational logic circuit comprises:
after the clock domain signals are generated, the clock domain signals are acquired by another clock domain register and then output to another clock domain register, the logic gates have logic combination through at least one stage of logic gate, and the logic gates are output after the Clk2 clock domain is subjected to synchronization processing of at least two stages of clock domain registers;
(5) And matching the analysis result with a fault mode and a synchronization mode of a common cross-clock domain to obtain designed violation information, and displaying the violation information by a violation display module.
The following is further illustrated according to specific examples:
in the current embodiment, the gate-level netlist cross-clock-domain automated analysis system mainly comprises a Verilog language parsing module, a simulation library automatic abstraction module, a gate-level netlist clock tree and reset tree inference module, a cross-clock-domain feature circuit identification module and an illegal display module. As shown in FIG. 1, prior to cross-clock domain analysis, the simulation library auto-abstraction module provides a list of basic module cases for structural analysis. In the cross-clock domain analysis, firstly, a Verilog program analysis module analyzes language in a connection mode aiming at a gate-level netlist file (including but not limited to Verilog language description), and a language analysis result is stored in a symbol table; secondly, the clock tree and reset tree inference module of the gate-level netlist extracts the clock tree and reset tree of the gate-level netlist by using the symbol table and the basic module condition list; thirdly, matching the extraction result with a common cross-clock domain fault mode and a synchronization mode to obtain designed violation information; and finally, displaying the violation design information by the violation display module.
Specifically, the simulation library file is abstracted by the automatic abstraction module of the simulation library aiming at the simulation library file, as shown in fig. 2, specifically:
firstly, loading simulation library files of devices designed by the programmable logic design gate-level netlist, respectively carrying out language analysis on Verilog and VHDL libraries, and storing corresponding analysis results into a symbol table for subsequent cross-clock domain automatic analysis;
secondly, extracting the attributes of each module of the library file according to the description of the library file, confirming the income output port aiming at the register driving clock, the reset signal, the enable signal and the output input port and aiming at the logic combination, and finally abstracting the base component pins in the simulation library;
finally, the component functions are classified according to the basic element functions as follows: logic combinations, registers and other basic devices, store device information into an information list. Recognizing the designed port through the characteristics of the sentence, storing the input port and the output port into an input/output port list, and marking the naming rule from the top layer to the bottom layer by the device according to the hierarchical structure as each module for use': "symbol separated, module and register name separated by". - ". The device type is identified through the device name, the register in the device type is extracted and stored in a register list, and the logic combination device in the device type is extracted and stored in a logic connection list. And identifying a device table outside the register and the logic, identifying other device types, classifying the other device types such as DCM, PLL, DDR IP core and the like, and storing identification results into respective lists according to port, register and logic classification.
Aiming at a gate-level netlist file represented by Verilog, a gate-level netlist design structure is obtained by using a Verilog program analysis module, and the method specifically comprises the following steps:
firstly, screening a Verilog design file to prevent program crash caused by wrong file input; secondly, carrying out syntactic analysis on the Verilog design file, establishing a module mapping model, mainly focusing on the expression of the design aiming at the connection mode, and analyzing and ignoring other characteristics of the language; finally, according to the analysis result, a module connection model is established, namely connection relations between ports and devices and between devices;
and synthesizing data results of the Verilog program analysis module and the simulation library automatic abstraction module, and using a gate-level netlist clock tree and a reset tree inference module. As shown in fig. 3, the clock tree inference specifically includes:
firstly, clock pins of all registers and latches are traversed, and stored logical connection relations are applied to trace back the tail end to which the pin can be connected, for example, for a certain register input clock pin, a clock input relevant path is obtained by means of inquiring a connection table until a relevant input port or a relevant register output port is reached.
Secondly, judging the property of the terminal signal, and if the terminal is an external interface, considering the interface as the input of a clock domain; if the signal is the output end of the register, continuously tracing the input clock of the register; if the signal is a half latch, the clock path is discarded.
And finally, forming a list by the clock domain according to the port name index for subsequent analysis and query.
The inference procedure for the reset tree is similar to the inference of the clock tree, and specifically comprises the following steps:
firstly, all the reset pins of the registers and the latches are traversed, and the stored logical connection relation is applied to trace back the tail end to which the reset pin can be connected, for example, for a certain register input reset pin, a clock input related path is obtained by inquiring a connection table until reaching a related input port or a register output port.
Secondly, judging the property of a terminal signal, and if the terminal is an external interface, considering the interface as an input controlled by a reset signal; if the signal is the output end of the register, continuously tracing the input reset of the register; if the signal is a half latch, the reset path is discarded.
Finally, the reset signal influence domain is indexed to form a list according to the port name for subsequent analysis and query;
deducing data by using a clock tree and a reset tree, and analyzing the clock domain crossing behavior by using a clock domain crossing feature recognition module, wherein the method specifically comprises the following steps:
firstly, analyzing clock domain signal crossing, deducing a register with a clock domain different from an input signal clock domain, wherein the input of the register is a preliminarily pre-judged clock domain crossing path.
Secondly, identifying characteristic circuits such as the existence of combinational logic in a clock domain crossing path, the existence of combinational logic behind a first-stage synchronizer, and the accurate processing of the clock crossing path. The method is characterized in that:
as shown in FIG. 4, a typical two-stage synchronization circuit consists of 3 registers, starting with the Clk1 clock domain register, and signals crossing the CLK1 and CLK2 clock domains are passed through at least two successive stages of registers to effectively eliminate the meta-stable effect. The circuit is characterized by three points, firstly, one path of clock domain crossing signal exists, is generated by one clock domain and is obtained by the other clock domain register; secondly, the signal is transmitted by a single wire, and no logic combination exists; finally, the signal is used after at least two-stage synchronization processing in a target clock domain (Clk 2 clock domain), and the signal is a single-bit signal after the first stage of synchronization.
As shown in FIG. 5, a typical combinational logic circuit existing across clock domain paths consists of three registers and a combinational logic gate, and signals crossing asynchronous clock domains CLk1 and CLk2 pass through the combinational logic, increasing the risk of metastability. The circuit is characterized by the following three points: firstly, a path spanning two clock domains exists, is generated by one clock domain and is acquired by a register of the other clock domain; secondly, the signal passes through at least one stage of logic gate, and logic combination exists; finally, the signal is used after the target clock domain (Clk 2 clock domain) has undergone at least two stages of synchronization.
As shown in fig. 6, a typical combinational logic circuit for synchronizing paths between registers across clock domains consists of three registers and a combinational logic gate, and signals crossing asynchronous clock domains CLk1 and CLk2 pass through the combinational logic, which increases the risk of metastability. The circuit is characterized by the following three points: firstly, a path crossing two clock domains exists, is generated by one clock domain and is acquired by a register of the other clock domain; secondly, a logic combination exists between the first-stage synchronization path and the second-stage synchronization path; finally, both stages of synchronizers are in the target clock domain (Clk 2 clock domain).
Finally, recording and searching the characteristic circuit path, and storing the illegal path.
And displaying the violation path and the violation mode through a violation display module.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Those skilled in the art will appreciate that the details of the invention not described in detail in this specification are well within the skill of those in the art.
Claims (10)
1. A gate-level netlist clock domain crossing automated analysis method is characterized by comprising the following steps:
abstract processing is carried out on the simulation library file;
acquiring a gate-level netlist design structure according to the abstract processing result;
extracting a clock tree and a reset tree of the gate-level netlist in the gate-level netlist design structure;
performing cross-clock domain behavior analysis according to the extraction result;
and matching the analysis result with the common cross-clock domain fault mode and synchronization mode information to obtain the designed violation information, and displaying the violation information.
2. The method for cross-clock-domain automated analysis of a gate-level netlist as claimed in claim 1, wherein:
the concrete steps of the abstraction processing are as follows:
loading simulation library files of devices designed by the programmable logic design gate-level netlist, performing language analysis on Verilog and VHDL simulation libraries respectively, and storing corresponding analysis results into a symbol table for subsequent clock domain crossing automatic analysis;
extracting corresponding module attributes in the simulation library file according to the description of the simulation library file, confirming the register driving clock, the reset signal, the enable signal and the output input port according to logic combination, and abstracting and processing basic component pins in the simulation library;
classifying according to the functions of basic components, storing information of the basic components, identifying design ports of the basic components through statement characteristics, storing input ports and output ports into an input and output port list, identifying the basic components according to a hierarchical structure, identifying the types of the components through the identification names of the basic components, extracting, registering and storing into a register list, extracting logic combination devices in the basic components and storing into a logic connection list, identifying the register list and devices outside the logic connection list, identifying other device types and storing identification results into a corresponding list according to the ports, the registers and the logic classification.
3. The method for cross-clock-domain automated analysis of a gate-level netlist as claimed in claim 2, wherein:
the specific steps for obtaining the gate-level netlist design structure are as follows:
screening the Verilog design files to prevent error file input, performing syntactic analysis on the Verilog design files, establishing a module mapping model, confirming the expression of the connection mode in the Verilog design files, and establishing a module connection model according to the analysis result of the Verilog design files for expressing the connection relation between a port and a device and between the device and the device.
4. The method for cross-clock-domain automated analysis of a gate-level netlist as claimed in claim 3, wherein:
the specific steps of inferring the clock tree of the gate-level netlist through the clock tree of the gate-level netlist and the reset tree inference module are as follows:
according to data results output by a Verilog program analysis module and a simulation library automatic abstraction module, deducing a clock tree through a gate-level netlist clock tree and a reset tree deduction module, traversing clock pins of all registers and latches, applying a stored logical connection relation, tracing the tail end of any pin which can be connected, inputting the clock pin of any register, and acquiring a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port;
judging the property of the terminal signal of any pin, if the terminal of the pin is an external interface, the interface is the input of a clock domain; if the terminal is the output end of the register, tracing the input clock of the register; if the terminal is a half latch, abandoning the clock path;
and forming a list by the clock domain of the terminal according to the port name index.
5. The method for cross-clock-domain automated analysis of a gate-level netlist as claimed in claim 4, wherein:
the specific steps of inferring the reset tree of the gate-level netlist through the gate-level netlist clock tree and reset tree inference module are as follows:
traversing all reset pins of the registers and the latches, tracing the tail end to which any pin can be connected through a stored logic connection relation list, and acquiring a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port;
judging the property of the terminal signal, and if the terminal is an external interface, considering the interface as an input controlled by a reset signal; if the terminal is the output end of the register, tracing the input reset of the register; if the terminal is a half latch, abandoning the reset path;
and forming a list by indexing the reset signal influence domain of the terminal according to the port name.
6. The method for cross-clock-domain automated analysis of a gate-level netlist as claimed in claim 5, wherein:
the specific method for analyzing the clock domain crossing behavior by using the clock domain crossing feature recognition module comprises the following steps:
analyzing the clock domain crossing behavior by using data output by a clock tree and reset tree inference module and a clock domain crossing characteristic identification module, analyzing the clock domain signal crossing, inferring out a register of which the clock domain is different from the clock domain of the input signal, and taking the input of the register as a preliminary pre-judged clock domain crossing path;
identifying a characteristic circuit which has combinational logic in a clock-crossing domain path, combinational logic in the first-stage synchronizer and correct optimization processing in the clock-crossing path;
and recording and searching the characteristic circuit path, and storing the illegal path.
7. The method for cross-clock-domain automated analysis of a gate-level netlist as claimed in claim 6, wherein:
the characteristic circuit is specifically as follows:
the circuit comprises a two-stage synchronization circuit, a clock domain crossing circuit path and a clock domain crossing synchronization inter-register path combinational logic circuit, wherein:
the two-stage synchronization circuit comprises 3 registers, a Clk1 clock domain register inputs a clock domain signal, the clock domain signal passes through a 2-stage register to eliminate metastable state influence, the clock domain signal is obtained by a last-stage clock domain register and has no logic combination, the clock domain signal is used after the Clk2 clock domain signal is subjected to two-stage register synchronization processing, and the clock domain signal is a single-bit signal after the first-stage synchronization.
8. The method for cross-clock-domain automated analysis of a gate-level netlist as claimed in claim 7, wherein:
the clock domain crossing circuit path specifically comprises:
the logic gate has logic combination after the clock domain signal is generated and is acquired by another clock domain register, and the logic gate outputs the clock domain signal after the clock domain signal passes through at least one stage of logic gate and is subjected to synchronization processing of at least two stages of clock domain registers in the Clk2 clock domain.
9. The method for cross-clock-domain automated analysis of a gate-level netlist as claimed in claim 8, wherein:
the cross-clock domain synchronization inter-register path combinational logic circuit comprises:
after clock domain signals are generated, the signals are acquired by another clock domain register and then output to another clock domain register, logic combination exists in the logic gates after passing through at least one stage of logic gates, and the signals are output after being subjected to synchronization processing of at least two stages of clock domain registers in a Clk2 clock domain.
10. A gate-level netlist cross-clock-domain automated analysis system as claimed in claim 9, characterized in that:
the device comprises a simulation library automatic abstraction module, a Verilog program analysis module, a gate-level netlist clock tree and reset tree inference module, a cross-clock domain feature recognition module and an illegal display module, wherein:
loading a simulation library file of a device designed by the programmable logic design gate-level netlist by the simulation library automatic abstraction module, performing language analysis on the Verilog simulation library and the VHDL simulation library respectively, and storing a corresponding analysis result into a symbol table for subsequent clock domain crossing automatic analysis; extracting corresponding module attributes in the simulation library file according to the description of the simulation library file, confirming the register driving clock, the reset signal, the enable signal and the output input port according to logic combination, and abstracting and processing basic component pins in the simulation library; classifying according to the functions of basic components, storing information of the basic components, identifying design ports of the basic components through statement characteristics, storing input ports and output ports into an input and output port list, identifying the basic components according to a hierarchical structure, identifying the types of the components through the identification names of the basic components, extracting, registering and storing the types of the components into a register list, extracting logic combination devices in the basic components and storing the logic combination devices into a logic connection list, identifying the register list and devices outside the logic connection list, identifying the types of other devices and storing identification results into a corresponding list according to the ports, the registers and the logic classification;
screening the Verilog design files by a Verilog program analysis module, preventing error file input, carrying out syntactic analysis on the Verilog design files, establishing a module mapping model, confirming the expression of a connection mode in the Verilog design files, and establishing a module connection model according to the analysis result of the Verilog design files for expressing the connection relationship between a port and a device and between the device and the device;
according to data results output by the Verilog program analysis module and the simulation library automatic abstraction module, the gate-level netlist clock tree and reset tree inference module infers the clock tree through the gate-level netlist clock tree and reset tree inference module, traverses clock pins of all registers and latches, applies stored logic connection relation, traces back the tail end of any pin which can be connected, inputs the clock pin of any register, and acquires a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port; judging the property of the terminal signal of any pin, wherein if the terminal of the pin is an external interface, the interface is the input of a clock domain; if the terminal is the output end of the register, tracing the input clock of the register; if the terminal is a half latch, abandoning the clock path; forming a list by the clock domain of the terminal according to the port name index; simultaneously traversing all the reset pins of the registers and the latches, tracing the tail end to which any pin can be connected through a stored logic connection relation list, and acquiring a clock input related path in a mode of inquiring a connection table until reaching a related input port or a register output port; judging the property of the terminal signal, and if the terminal is an external interface, considering the interface as an input controlled by a reset signal; if the terminal is the output end of the register, tracing the input reset of the register; if the terminal is a half latch, abandoning the reset path; forming a list by indexing the reset signal influence domain of the terminal according to the port name;
the cross-clock domain feature recognition module analyzes the cross-clock domain behavior by using the data output by the clock tree and reset tree inference module, analyzes the clock domain signal intersection, infers a register with a clock domain in which the register is located and a clock domain of an input signal, and takes the input of the register as a preliminarily pre-judged cross-clock domain path; identifying a characteristic circuit in which a combinational logic exists in a clock-crossing domain path, the combinational logic exists behind a first-stage synchronizer, and the clock-crossing path is correctly optimized; recording and retrieving a characteristic circuit path, and storing the illegal path;
and the violation display module displays the violation path.
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| CN115862052A (en) * | 2023-02-24 | 2023-03-28 | 北京芯愿景软件技术股份有限公司 | Method, device, equipment and storage medium for automatically identifying clock crossing circuit |
| CN116306415A (en) * | 2022-12-30 | 2023-06-23 | 芯耀辉科技有限公司 | Static time sequence analysis method and system thereof |
| CN116502578A (en) * | 2023-06-29 | 2023-07-28 | 深圳国微晶锐技术有限公司 | Construction method of netlist reduction time sequence model and static time sequence analysis method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116306415A (en) * | 2022-12-30 | 2023-06-23 | 芯耀辉科技有限公司 | Static time sequence analysis method and system thereof |
| CN116306415B (en) * | 2022-12-30 | 2023-10-20 | 芯耀辉科技有限公司 | Static time sequence analysis method and system thereof |
| CN115862052A (en) * | 2023-02-24 | 2023-03-28 | 北京芯愿景软件技术股份有限公司 | Method, device, equipment and storage medium for automatically identifying clock crossing circuit |
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