JP3072985B2 - Logic simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method, and more particularly to an efficient method for confirming the operation of an electronic circuit after a logic change and confirming the operation of an electronic circuit after converting a logic described at a high level into a low-level description. The present invention relates to a frequently performed logic simulation method.

[0002]

2. Description of the Related Art Conventionally, a logic simulation is generally used as a method for confirming the operation of an electronic circuit in a design stage. In this logic simulation, the operation of the electronic circuit is reproduced on a computer based on a logical file storing the logical connection information of the electronic circuit, and whether or not the electronic circuit operates as intended by the designer is determined. This is manually checked based on a time chart or the like to check whether there is a defect in the logic under design.

[0003] In the event that a logic simulation finds that the logic does not operate as intended by the designer, the designer corrects the logic and confirms that the countermeasures have been taken. Re-simulation is also performed on the other functions that have been performed to confirm that the functional operation has not been affected by the logic modification. The result confirmation in this re-simulation is performed manually.

[0004] When a defect is extracted by adjustment after the electronic circuit is manufactured, the logic file is corrected, the fact that the measure against the defect is taken is confirmed by a logic simulation, and the operation of other functions is also performed. Is re-simulated to confirm again that it is not affected by the logic modification. The result of the re-simulation is also checked manually.

In recent years, since electronic circuits have become larger and more sophisticated, operation confirmation in operation / function level logic simulation has become widespread. However, logic description at the gate level is required for electronic circuit manufacture. Therefore, it is necessary to convert the logic description at the operation / function level into the logic description at the gate level, perform a logic simulation at the gate level, and confirm the operation again. This confirmation is also performed manually.

On the other hand, as a method of confirming the operation of an electronic circuit, as disclosed in Japanese Patent Application Laid-Open No. 3-83170, the specification of an electronic circuit is converted into a logic circuit and combined with the electronic circuit under design. A method of performing a logic simulation is known.

As described in Japanese Patent Application Laid-Open No. 4-153776, a simulation using the same test pattern is performed on a function description circuit model that correctly reflects the function specifications of a logic circuit and a circuit model described with a logical connection. A mismatch pattern is extracted, a test pattern is generated to analyze a logic bug by focusing only on the mismatch point, and a logic simulation is performed on the function description circuit model and the logic connection description circuit model using the test pattern. A technique for outputting a state value list and mismatch information for a logical connection description circuit model is known.

[0008]

However, in the method of manually confirming the result of the logic simulation as described above, the burden on the designer is large, and there is a possibility that the logic failure may be overlooked.

The technique disclosed in Japanese Patent Application Laid-Open No. 3-83170 is not only for a new design, but also for a logic modification. As compared with the case where the logic simulation is performed, there is a problem that the scale of the simulation target is increased and the operation time of the computer for this processing is greatly increased.

The technique disclosed in Japanese Patent Application Laid-Open No. 4-153776 is for detecting a mismatch point between a function description circuit model and a logical connection description circuit model and analyzing a logic bug. There is a problem that the circuit operation after the change cannot be confirmed.

An object of the present invention is to provide a logic simulation method for reducing the number of steps required to check the result of a logic simulation performed at the time of logic modification or at the time when a logic description with a high degree of abstraction is converted to a logic description with a low level of abstraction. It is in.

[0012]

In order to achieve the above object, the present invention provides a simulation result obtained by reproducing the operation of an electronic circuit on an electronic computer based on logical connection information of the electronic circuit. Selecting one comparison means from a plurality of comparison means for comparing data; and using the selected comparison means to simulate normal operation results of the electronic circuit and resimulation result data of the electronic circuit. The method includes a step of comparing and a step of outputting a comparison result.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a system configuration diagram of a logic simulation for verifying the logic of an electronic circuit. In FIG. 1, reference numeral 100 denotes a gate description file that stores gate connection information and a gate delay value of an electronic circuit, and 110 denotes a test data file that stores an input pattern for logic simulation.

Reference numeral 120 denotes an operation level description file for storing an electronic circuit having an operation level equivalent to the simulation target electronic circuit. Reference numeral 130 denotes a logic for inputting the contents of the gate description file 100 and the test data file 110 and outputting a simulation result. This is a simulation processing unit.

The logic simulation processing unit 130 includes a gate description processing unit 140 and a behavior level description processing unit 150.

160 simulates the contents of the gate description file 100 and the test data file 110,
A result file A stores the result of obtaining the internal state, and a result file B 170 stores the result of processing the contents of the behavioral level description file 120 by the behavioral level description processing unit 150.

Reference numeral 180 denotes a judgment unit which inputs the contents of the result file A 160 and the result file B 170 and judges the operation of the electronic circuit to be simulated, and outputs the judgment result to a judgment result list 190.

FIG. 2 is a diagram showing the contents of the behavioral level description file 120. In order to determine whether or not the simulation results operate as intended by the designer, changes in the input signals A201, B202 and S203 are made. After that, the allowable range A regarding the time until the output signal X204 changes.
205 and B206 and comparison mode (COMPARE MODE)
207 and pass / fail judgment time (comparison time range: COMPAR
E TIME) 208 is described.

In FIG. 2, the maximum time difference is set to 5 ns (de) as the time allowable ranges A205 and B206.
lay MAX 5), and the minimum time difference is set to 0 ns (delay MIN 0) although the description is omitted. The pass / fail judgment time 208 is set to 8 to 26 ns (COMPARE TIME = 8 to 2
6) As the determination means, the comparison mode 207 performs the comparison by comparing whether or not the difference between the signal value of the comparison target signal and the change time is within an allowable range (eg, COMPARE).
MODE = 2).

FIG. 3 shows an LSI (Large Scale In) having a selector logic circuit as an electronic circuit to be simulated.
FIG. 2 is a circuit diagram of a large-scale integrated circuit (IC).
00) is stored.

In FIG. 3, input signals A'301, B '
Reference numerals 302, S'303, and output signal X'304 correspond to input signals A201, B202, S203, which are contents of the operation level description file 120 in FIG.

The test data file 110 stores the electronic circuit 3 in which the gate is described for the logic simulation.
00 and an input pattern given to the behavior level description file 120 describing the operation of the electronic circuit 300, and are created for each test item.

The result file B 170 is a result of processing the behavior level description file 120 by the behavior level description processing section 150, and it is assumed that the behavior is already confirmed to be the same as the expected value.

The output signal X obtained by the operation level description
The result of 204 is that the difference between the change times is calculated and output with the minimum value.

FIG. 4 shows an input signal A201 (A'201).
'), B202 (B'202') and S203 (S '
203 ') and an output signal X204 (X'204').
5 is a time chart 400 showing the time chart.

In FIG. 4, the output signal X204 and the output signal X'204 'are signals to be compared, and from the description of the pass / fail judgment time (comparison time range: COMPARE TIME) 208 in FIG. The output signal X204 and the output signal X'204 'which are signals to be compared within the comparison time
The change time of the same signal value is read, and the difference between the change times is obtained.

In this case, the difference between the change times is as follows: the first time = time 3, the second time = time 4, and both are within the allowable range 205 of the change time. Output.

FIG. 5 is a flowchart showing an example of the processing procedure of the logic simulation system. Hereinafter, the processing flow of the logic simulation method according to the present invention will be described with reference to the flowchart of FIG.

First, the contents of the gate description file 100 to be compared and the contents of the test data file 110 to be input to the gate description file 100 are input (steps 501 and 502).

Next, a logic simulation is performed according to the contents of these files (step 503), and the result of the logic simulation at the gate level is output to the result file A160.

Next, in order to compare the simulation results at the gate level and the operation level, a result file A16
From 0, the simulation result of step 503 is read, and at the same time, the simulation result at the already stored operation level is read from the result file B170 (step 504).

Next, the operation level description file 120 is read, and the comparison mode 207 necessary for the comparison processing and information necessary for the comparison mode 207 are read (step 50).
5).

If the comparison mode 207 compares the signal value of the signal to be compared with the change time,
If “step 506: comparison mode (1)” is set, and if the comparison mode 207 compares whether the difference between the signal value of the comparison target signal and the change time is within an allowable range,
"Step 507: Comparison mode (2)"
If the comparison mode 207 is to compare whether or not the signal value of the comparison target signal is equal to the change order, the process proceeds to “Step 50
8: Comparison mode (3) ".

The information necessary for the comparison mode 207 is the allowable range A205 or B206 of the change time when the comparison mode 207 is the "comparison mode (2)" as in the embodiment.

If the pass / fail judgment time 208 is specified, the comparison mode 207 is read at the same time when the comparison mode 207 is read in step 505.

Then, the judgment result of the comparison mode 207 is "comparison mode (1)" (step 506: YES).
If so, the process proceeds to step 509 to compare the signal value of the comparison target signal with the change time in the comparison time range specified by the operation level description, output the comparison result to the determination result list 190 (step 512), and perform the processing. finish.

The determination result of the comparison mode 207 is as follows:
If "comparison mode (2)" (step 507: YES), the flow advances to step 510 to determine whether the difference between the signal value of the comparison target signal and the change time is within the allowable range in the comparison time range specified by the operation level description. The result of the comparison is output to the determination result list 190 (step 512), and the process ends.

Further, the judgment result of the comparison mode 207 is
If "comparison mode (3)" (step 508: YES), the process proceeds to step 511 to compare whether or not the signal value of the comparison target signal and the change order are equal in the comparison time range specified by the operation level description. And the comparison result as the judgment result list 19
0 (step 512), and the process ends.

As a result, the result of the re-simulation after the logic change is conventionally released from the task of manually checking.

[0040]

As described above, according to the present invention,
Based on the logical connection information of the electronic circuit, the operation of the electronic circuit is reproduced on an electronic computer, and the simulation result data at the time of normal operation of the electronic circuit and the resimulation result data after the logic change of the electronic circuit are obtained. For comparison,
A plurality of comparison means (comparison modes) are provided, one of which is selected and simulation result data of the electronic circuit during normal operation is compared with re-simulation result data of the electronic circuit. In this case, the number of steps for confirming the result of the re-simulation performed at the time of correcting the logic can be reduced.

In the mode for comparing whether or not the change times of the data to be compared coincide with each other, it is possible to efficiently determine whether or not there is a mismatch at the change time of the electronic circuit after the logic change.

In the mode for comparing whether or not the difference between the change times of the data to be compared is within an allowable range, it is determined whether or not the time allowable range of the mismatch point with respect to the change time of the electronic circuit after the logic change is good. Can be performed efficiently.

Further, in the mode for comparing whether or not the order of change of the data to be compared is equal, it is possible to efficiently determine whether or not there is a mismatch point in the order of change of the electronic circuit after the logic change.

As a result, there is an effect that the number of steps for confirming the result of the logic simulation conventionally performed manually can be reduced.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing one embodiment of a logic simulation system to which the present invention is applied.

FIG. 2 is an explanatory diagram of a behavior level description file in the embodiment.

FIG. 3 is an explanatory diagram of a gate description file in the embodiment.

FIG. 4 is an explanatory diagram of a time chart in a simulation result file in the embodiment.

FIG. 5 is a flowchart illustrating a processing procedure of a logic simulation method according to the embodiment.

[Explanation of symbols]

100: gate description file, 110: test data file, 120: operation level description file, 130: logic simulation processing unit, 140: gate description processing unit, 150: operation level description processing unit, 160: result file A, 170: result File B, 180... Determination unit, 1
90 ... judgment result list.

(72) Inventor Osamu Tada 810 Shimo-Imaizumi, Ebina-shi, Kanagawa Pref.Hitachi, Ltd. Office Systems Division (72) Inventor Shigeki Yokoya 810 Shimo-Imaizumi, Ebina-shi, Kanagawa Pref. (56) References JP-A-6-58968 (JP, A) JP-A-1-13481 (JP, A) JP-A-4-172563 (JP, A) JP-A-3-1279 (JP, A) JP-A-4-141775 (JP, A) JP-A-5-143670 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50

Claims (3)

(57) [Claims] 1. A method for performing a logic simulation of an electronic circuit that reproduces the operation of the electronic circuit on an electronic computer based on logical connection information of the electronic circuit and outputs the reproduction result as simulation result data. Selecting one comparison means from a plurality of comparison means for comparing the simulation result data; and using the selected comparison means to simulate the simulation result data during normal operation of the electronic circuit and re-execute the electronic circuit. A logic simulation method comprising: comparing simulation result data; and outputting a comparison result. 2. The method according to claim 1, wherein the comparing means includes means for comparing whether or not the change times of the simulation result data match, and determining whether a difference between the change times of the simulation result data is within an allowable range. 2. The logic simulation method according to claim 1, further comprising means for comparing 3. The plurality of comparing means includes means for comparing whether or not the difference between the change times of the simulation result data is within an allowable range, and determining whether or not the change order of the simulation result data is equal. 2. The logic simulation method according to claim 1, further comprising means for comparing.