JPH0745029Y2 - IC test equipment - Google Patents

Description

[Detailed Description of the Invention] "Industrial Application Field" The present invention relates to an IC test apparatus having an output terminal.

"Prior Art" Fig. 2 shows a conventional IC tester. In the figure, 1 indicates the IC under test. The terminals 1A, 1B, ... 1N of this IC under test 1 are input / output terminals. Hereinafter, this input / output terminal is abbreviated as an input / output terminal in this specification.

Reference numeral 2 is a pattern generator, and 3 is an expected value pattern generator. The pattern signal output from the pattern generator 2 is passed through the waveform controllers 4A, 4B and the drive circuits 5A, 5B to the IC under test.
1 is given to each input / output terminal 1A, 1B. Waveform controller 4A (4
Each path of B) and the drive circuit 5A (5B) will be called a signal supply path of a test pattern signal. In this example, only the input / output terminals 1A and 1B of the IC under test 1 will be described.
A pattern signal is given to the other input / output terminals with the same configuration.

The input / output terminals 1A and 1B are switched from the input mode to the output mode by the control signal and output the response signal of the IC under test 1. This response signal is given to the level comparators 6A and 6B, and it is determined whether or not the normal H logic level and L logic level are output.

If the result of the level judgment is good, the level judgment output is given to the digital comparators 7A and 7B and compared with the expected value pattern in the digital comparators 7A and 7B. Each path of the level comparator 6A (6B) and the digital comparator 7A (7B) will be called a signal acquisition path. When a discrepancy occurs with the expected value pattern signal, a defect detection signal FAIL is generated from each of the digital comparators 7A and 7B and the defect of the IC under test 1 is displayed.

The description so far is a normal operation description. Next, the high speed test will be described.

When the operation speed of the IC under test 1 is high, the test time can be shortened by increasing the generation speed of the pattern signal. However, since it is difficult to increase the pattern generation speed of the pattern generator 2, a high speed element has been tested by the following method conventionally. That is, the switching circuit 8 switches the logic waveforms given from the waveform controllers 4A and 4B, and two pattern signals are superimposed and given to the input / output terminal 1A, for example, and a pattern signal that changes at a speed twice the normal speed is inputted. Apply to output terminal 1A.

The switching circuit 8 is composed of a register 8A, an AND gate 8B, and an OR gate 8C. The AND gate 8B is opened by setting the H logic in the register 8A to open the waveform controller.
The logical waveform output from 4B is given to the OR gate 8C, and the OR gate 8C superimposes it on the logical waveform given from the waveform controller 4A.

When the L logic is given to the register 8A, the AND gate 8B is closed, so that the logic waveform signal output from the waveform controller 4B is not superimposed on the input / output terminal 1A. Done.

On the other hand, when the H logic is input to the register 8A, the multiplexer 9 provided between the level comparators 6A and 6B and the digital comparator 7B is switched, and the output of the level comparator 6A is also given to the digital comparator 7B to perform the digital comparison. The state is switched to a state in which the determination result of the response output of the input / output terminal 1A is output from both the devices 7A and 7B.

That is, if the signal supply system path on the waveform controller 5A side is the A channel and the signal supply system path on the waveform controller 5B side is the B channel, the test pattern signal on the A channel side is the input / output terminal.
When the response signal is given to 1A and taken out by the level comparator 6A, the level comparison output is A by the digital comparator 7A.
Compare with the expected value pattern on the channel side. At the same time, when the test pattern signal on the B channel side is given to the input / output terminal 1A through the switching circuit 8 and the response output signal is taken out by the level comparator 6A, the response output signal is sent to the digital comparator 7B through the multiplexer 9. And the expected value pattern on the B channel side is compared. In this way, the input / output terminal 1A is tested at high speed by utilizing the test patterns of the A channel and the B channel.

"Problems to be solved by the invention" As described above, in the high-speed test, one input / output terminal is tested using two channels, A channel and B channel, so it is necessary to test all terminals at one time. Requires a number of channels that is twice the number of terminals of IC1 under test. As a result, there is a drawback that the circuit scale of the IC test apparatus becomes large and becomes expensive.

An object of the present invention is to provide an IC test device that can carry out a high speed test without increasing the circuit scale.

"Means for Solving Problems" In the present invention, a switching circuit capable of superimposing pattern signals on each other is provided in the signal paths of pattern signals forming a pair.

According to the configuration of the present invention, a pair of logical waveform signals output from a pair of waveform controllers can be superimposed on each other and supplied to two input / output terminals. Only by switching the switching circuit, it is possible to switch the system path of the terminal to be subjected to the high speed test. Therefore, all terminals of the IC under test can be tested at high speed without increasing the number of channels.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In the figure, 1 is the test I
C, 2 is a pattern generator, 3 is an expected value pattern generator, 4
A and 4B are waveform controllers, and 5A and 5B are drive circuits as in the case of FIG.

In this invention, switching circuits 11A and 11B for superimposing signals on each other are provided between the waveform controllers 4A and 4B and the drive circuits 5A and 5B.

Each of the switching circuits 11A and 11B is composed of the register 8A, the AND gate 8B whose opening and closing is controlled by the set output of the register 8A, and the OR gate 8C, as described above.

With such a configuration, by inputting H logic to the register 8A of each switching circuit 11A, 11B and controlling the AND gate 8B to open, the logic waveform signals output from the waveform controllers 4A and 4B are output in the OR gate 8C. The signals are superposed on each other and applied to the drive circuits 5A and 5B and input to the input / output terminals 1A and 1B.

The response output signals of the input / output terminals 1A and 1B are level comparators 6A and 6B.
In this example, the level judgment is performed and the level judgment output is given to the digital comparators 7A and 7B via the multiplexers 9A and 9B.

In other words, when these two multiplexers 9A and 9B have separate registers 12A and 12B, respectively, any of the outputs of the level comparators 6A and 6B can be freely selected and provided to the digital comparators 7A and 7B. Indicates.

With this configuration, if the H logic is input to either one of the registers 8A, the high speed test pattern signal can be applied to either one of the input / output terminals 1A or 1B. It is also possible to switch the input / output terminal that gives the high-speed test pattern signal.

Furthermore, the response output of each input / output terminal 1A and 1B is the level comparator 6A, 6
Since the level is compared at B, and the level comparison result is given to the two multiplexers 9A and 9B, the response output from the input / output terminal 1A or the response output from the input / output terminal 1B can be given to the digital comparator 7A. Will also be possible.

Therefore, the digital comparators 7A and 7B can output the pass / fail judgment result of any of the input / output terminals 1A and 1B.

“Effect of device” As described above, according to this device, if the terminals of the IC under test are tested at a high speed by half, a high-speed test can be performed with a circuit of the same scale as the low-speed test. The test apparatus can be provided at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram for explaining a conventional technique. 1 ... IC under test, 2 ... Pattern generator, 3 ... Expected value pattern generator, 4A, 4B ... Waveform controller, 5A, 5B ... Drive circuit, 6A, 6B ... Level comparator, 7A , 7B ... Digital comparator, 8A ... Register, 8B ... And gate, 8C ... Off gate, 9A, 9B ... Multiplexer, 11A, 11B ... Switching circuit, 8A ... Register forming switching circuit, 8B …… Similar AND gate, 8C …… Similar OR gate.

Claims (1)

[Scope of utility model registration request] 1. A waveform controller for converting a pattern signal output from a pattern generator into a test pattern signal having an actual waveform applied to each input / output terminal of an IC under test, and an actual waveform output from this waveform controller. Test pattern signal with
At the timing when a signal supply system path for the test pattern signal, which is composed of a drive circuit for each input / output terminal of the IC, is provided for each input / output terminal of the IC under test and each input / output terminal is switched to the output terminal. , A level comparator for extracting the response output signal of the IC under test output to each input / output terminal, and a digital signal for comparing the expected value pattern with the signal judged to have a normal logic level by this level comparator In an IC tester that is configured with a signal-acquisition path that is composed of a comparator for each input / output terminal of the IC under test, the two signal-supply paths are mutually opposite A switching circuit that switches between the state in which the test pattern signal of itself is superimposed on the line and the state in which it is not superimposed, and the two signal acquisition lines connected to these two signal supply lines are tested.
An IC test apparatus comprising: a multiplexer that switches a response output signal output from the one input / output terminal of the IC to a state in which it is distributed to two digital comparators and a state in which it is not distributed.