JPH0829487A - Circuit for judging propriety of dut - Google Patents

Abstract

PURPOSE:To provide a DUT checking circuit which can judge the propriety of DUT even when a criterion timing is several times a test rate. CONSTITUTION:A timing generating portion 2 outputs test rate signals, and sets and outputs a criterion timing that is asynchronous with the test rate signals, a pattern generating portion 1 outputs application patterns to a DUT10 in synchronization with the test rate signals and outputs expectation patterns, a FIFO3 inputs, in response to a clock signal of the criterion timing, the output of the DUT10 including data for n pieces of test rate signals, and outputs the first n test rate signals in response to a signal inhibited by an inhibit circuit 6, a shift register 4 has n pieces of FFs which receive the test rate signals as clock inputs the shift the expectation patterns as data inputs in sequence, and the output of the FIFO3 is converted into a first input at an exclusive OR gate 5, and a pass or fail is output with the output of the shift register 4 as a second input.

Description

Detailed Description of the Invention

[0001]

This invention relates to an IC to be measured (hereinafter referred to as
Called DUT. ) Is for the determination circuit for determining the quality.

[0002]

2. Description of the Related Art Next, FIG. 3 shows the configuration of a pass / fail judgment circuit for a DUT according to the prior art. In FIG. 3, 10 is a DUT, 11 is a pattern generator, 12 is a timing generator, and 13/15.
Is a flip-flop (hereinafter referred to as FF), and 14 is an exclusive OR gate. In FIG. 3, the pattern generator 11
Inputs an application pattern to the DUT 10 at the timing of the timing generator 12. The output of the DUT 10 is connected to the data terminal of the FF 13, and is output from the FF 13 according to the determination reference timing of the timing generator 12.

The exclusive OR gate 14 receives the output of the FF 13 as a first input and the expected value pattern of the pattern generating section 11 as a second input to the data terminal of the FF 15. The FF 15 outputs pass / fail data using the test rate signal of the timing generator 12 as a clock input.

Next, the operation of FIG. 3 will be described with reference to FIG. FIG. 4 is a timing chart showing the operation of each part of FIG. FIG. 4A shows the DUT 10 from the pattern generator 11.
It is a waveform diagram of the application pattern input to. A in Fig. 4 is D
4 is a waveform diagram of the output of the UT 10, showing the results “1 to 4” corresponding to the pattern of FIG. 4A after the internal delay time of the DUT 10.
Is output.

FIG. 4C is a waveform diagram of the judgment reference timing output from the timing generator 12. By connecting the data of FIG. 4A to the D input of the FF 13 and sampling at the timing of FIG. 4C, the FF 13 outputs the data of FIG.

FIG. 4E is a waveform diagram of an expected value pattern of the pattern generating section 11, which is a waveform diagram serving as a judgment reference pattern. The waveform of FIG. 4E is output in synchronization with the waveform of FIG. FIG. 4F shows the waveform of the output data of the exclusive OR gate 14 with the data of FIG. 4D and the data of FIG. The data of FIG. 4E and the data of FIG. 4E are compared by the exclusive OR 14, and when both inputs of the exclusive OR gate 14 match, the output of the exclusive OR gate 14 becomes “0”.

FIG. 4C is a waveform diagram of the test rate output from the timing generating section 12 as the operation unit of the system. Since the data obtained in FIG. 4 changes at the timing shown in FIG. 4C, the data shown in FIG. 4 is input to the data terminal of the FF15, the waveform is input to the clock as shown in FIG. Convert to. At this time, the output of the FF 15 has a determination result that is deviated by one rate with respect to the application pattern of FIG. In this way, the pass / fail judgment is made for each test rate.

[0008]

However, in the configuration shown in FIG. 3, when the internal delay time of the DUT is large and the output of the device exceeds the test rate, the pass / fail judgment synchronized with the test rate unit can be normally performed. Can not. That is, there is a problem that the determination reference timing output from the timing generation unit cannot be set beyond the test rate time. SUMMARY OF THE INVENTION An object of the present invention is to provide a DUT pass / fail judgment circuit capable of making a pass / fail judgment of a DUT even when the timing of the determination reference is multiple of the test rate.

[0009]

In order to achieve this object, the present invention outputs a test rate signal generated at regular time intervals and sets and outputs a judgment reference timing asynchronous with the test rate signal. The generation unit 2 and the pattern generation unit 1 which receives the test rate signal of the timing generation unit 2 as an input, inputs the applied pattern to the DUT 10 in synchronization with the test rate signal, and outputs the expected value pattern of the DUT 10, and an arbitrary n The output of the DUT 10 containing the data over the test rate signals,
A clock signal of the judgment reference timing is input as an input clock, and a FIFO3 which outputs a signal obtained by inhibiting the first n test rate signals by the inhibit circuit 6 as an output clock, and a test rate signal as a clock input, and an expected value pattern Shift register 4 provided with n FFs for sequentially shifting as a data input
And an output of the FIFO 3 as a first input, an output of the shift register 4 as a second input, and an exclusive OR gate 5 for outputting a pass / fail.

[0010]

Next, FIG. 1 shows the configuration of a pass / fail judgment circuit of the DUT according to the present invention. In FIG. 1, 1 is a pattern generator, 2 is a timing generator, 3 is a FIFO, 4 is a shift register,
Reference numeral 5 is an exclusive OR gate. FIG. 1 shows, as an example, a configuration in which the output waveform of the DUT 10 over two rates can be determined. The pattern generator 1 and the timing generator 2 in FIG. 1 are the same as 11 and 12 in FIG. 3, respectively.

In FIG. 1, the timing generator 2 inputs a reference clock, which is a test rate signal, to the pattern generator 1. The pattern generator 1 inputs the applied pattern to the DUT 10 and the expected value pattern to the shift register 4. The FIFO 3 inputs the output of the DUT 10 to the data terminal, inputs the test rate signal obtained by inhibiting the first two clocks of the test rate signal by the inhibit circuit 6 to the input clock terminal, and determines from the timing generator 2 to the output clock terminal. Input the reference timing clock.

The inhibit circuit 6 can have various configurations, for example, by inputting a test rate signal to a shift register or a counter having a number of stages for inhibiting, and by inverting the output thereof to a test rate signal.
The number of clocks for inhibiting the inhibit circuit 6 is
The configuration may be set arbitrarily.

The shift register 4 is an FF 4 connected in series.
A.4B is provided, and expected value pattern data is input at the timing of the test rate signal of the timing generator 2, and the data is sequentially shifted. In FIG. 1, the output of the DUT 10 is 2
Since it is an example that covers the rate, F of the shift register 4
Although F has a two-stage configuration, the number of stages of the FF changes depending on the number of rates over which the output of the DUT extends, that is, the number of inhibits of the inhibit circuit 6. The exclusive OR gate 5 receives the output of the FIFO 3 and the output of the shift register 4 as input, and determines pass / fail for each test rate signal.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, FIG. 2 shows a timing chart for explaining the operation of each part of FIG. 2A shows the waveform of the clock of the timing generator 2, which generates pulses as test rate signals at regular intervals. 2A shows the waveform of the applied pattern output by the pattern generator 1,
In synchronization with the timing of FIG.
An example of sequentially outputting "e" is shown.

FIG. 2C shows the output waveform of the DUT 10,
FIG. 3 is a waveform diagram of data output for each test rate signal with respect to the application pattern of FIG. 2A. In Figure 2c, the DUT
Due to the internal delay time of 10, the output data shows a state in which the output time is different for each test rate signal.

FIG. 2D is a waveform diagram of the judgment reference timing, and is a waveform diagram of the input clock for inputting the data of FIG. 2C to the FIFO 3 of FIG. In FIG. 2D, timing is generated corresponding to output data having different output times for each test rate signal obtained as a result of executing the application pattern of FIG. 2A. 2e is the FI of FIG. 1 at the timing of FIG.
It is an output waveform of DUT10 input into FO3.

FIG. 2F is a waveform diagram of the expected value pattern output by the pattern generator 1. The expected value pattern data is output in synchronization with the timing shown in FIG. 2A similarly to the timing shown in FIG. In FIG. 2, the expected value data “1 to
5 ”is sequentially generated.

FIG. 2C is a waveform diagram of the output clock input to the FIFO 3 of FIG. 1, and is a waveform diagram obtained by inhibiting the first and second clocks of the waveform of FIG. 2A by the inhibit circuit 6. FI of FIG. 1 at the timing of FIG.
The data of FIG. 2E input to FO3 is output. 2 is a waveform diagram of the output data of the FIFO 3 of FIG.

FIG. 2C shows the output waveform of the shift register 4. In FIG. 2, the data of the expected value pattern of FIG. 2 input at the timing of the test rate signal shown in FIG.
4B sequentially holds and outputs. Figure 2 is the same as Figure 1
2 is the output of the exclusive OR gate 5, and the data of FIG. 2 and the data of FIG. 2 are input, and when they match, the data is output as a path.

[0020]

According to the present invention, the output of the DUT over a plurality of test rate signals is input to the FIFO at a determination reference timing that is asynchronous with the test rate signal, and the number of test rate signals that the DUT output crosses inhibits. The output from the FIFO is output at the timing of the test rate signal, and the expected value pattern is sequentially shifted at the timing of the test rate signal and output by the shift register including the FFs of the number of test rate signals that the output of the DUT straddles. Even if the reference timing becomes a multiple of the test rate, the quality of the DUT can be determined for each test rate signal.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a pass / fail judgment circuit according to the present invention.

FIG. 2 is a timing chart explaining the operation of each unit in FIG.

FIG. 3 is a configuration diagram of a determination circuit of an IC tester according to a conventional technique.

FIG. 4 is a timing chart showing the operation of each part of FIG.

[Explanation of symbols]

 1 ・ 11 pattern generation unit 2 ・ 12 timing generation unit 3 FIFO 4 shift register 514 exclusive OR gate 10 DUT 13 ・ 15 FF

Claims (1)

[Claims] 1. A timing generator that outputs a test rate signal generated at regular time intervals and sets and outputs a judgment reference timing asynchronous with the test rate signal.
(2) and the test rate signal from the timing generator (2) are input,
A pattern generating section (1) for inputting an applied pattern to the IC under test (10) in synchronization with the test rate signal and outputting an expected value pattern of the IC under test (10), and arbitrary n test rate signals Input the output of the IC under test (10) including the data over the test reference signal as the input clock, and use the inhibit signal of the first n test rate signals in the inhibit circuit (6) as the output clock. FIFO to output
(3), a test rate signal as a clock input, an expected value pattern as a data input, a shift register (4) having n flip-flops sequentially shifted, and an output of the FIFO (3) as a first input, Shift register
A pass / fail judgment circuit for a DUT, comprising an exclusive OR gate (5) for outputting a pass / fail with the output of (4) as a second input.