JP3882376B2 - Integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit, and more particularly to an integrated circuit including a test circuit.
[0002]
[Prior art]
FIG. 3 is a block diagram showing a configuration of a first conventional integrated circuit.
[0003]
The integrated circuit 3 operates in accordance with input signals given to the inputs 1-1 to 1-n, and outputs output signals from the outputs 2-1 to 2-n. The integrated circuit 3 is tested by observing the state of the output signal.
[0004]
FIG. 4 is a block diagram of a second conventional integrated circuit composed of a scan circuit and a logic circuit.
[0005]
In the figure, an integrated circuit 4 is composed of a logic circuit 5 and scan FFs (hereinafter abbreviated as FFs) 1 to FFn. The output of FFn is output to ScanOut and the internal state is observed. Here, when ScanClock is input, each FFn is shifted. The output of FFn-1 is shifted to FFn, and the output of FFn-1 can be observed at ScanOut. Also, since the input from ScanIn is shifted to FF1, the internal state can be arbitrarily set. Therefore, the state of all FFn can be observed and arbitrarily set by repeating the shift n times by ScanClock.
[0006]
[Problems to be solved by the invention]
In recent years, with the increase in scale of LSIs, internal tests have become complicated and difficult, and the number of internal pins has also increased. In order to simplify the internal test, a method of performing an isolation test for each internal circuit block is used, but the test is difficult because the number of pins of the LSI does not change.
[0007]
However, in the first conventional integrated circuit, since all pins of the integrated circuit are also used as LSI pins during the LSI isolation test, it is possible to test the AC characteristics, but many test pins are required. there were.
[0008]
In the second conventional integrated circuit, the test can be performed with a small number of test pins. However, since the input and output are synchronized with the test clock, the AC characteristics can be tested. There wasn't.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit that can test the inside of an integrated circuit with a small number of test pins and can also test AC characteristics.
[0010]
[Means for Solving the Problems]
To achieve this object, an integrated circuit includes at least a pair of input and output terminals, a test clock input terminal, a logic circuit having at least a first input node, a second input node, and an output node; A test for supplying input data externally supplied to a terminal to the first input node and the second input node of the logic circuit and supplying output data output from the output node of the logic circuit to the output terminal An integrated circuit comprising a circuit,
The test circuit includes a flip-flop that holds input data externally applied to the input terminal in synchronization with a clock applied to the test clock input terminal,
First, input data given first from the outside to the input terminal is temporarily held by the flip-flop and supplied to the second input node of the logic circuit, and input data given next from the outside directly to the input terminal directly Supplying to the first input node of the logic circuit, the output data output from the output node of the logic circuit is directly supplied to the output terminal.
[0011]
To achieve this object, an integrated circuit includes at least a pair of input and output terminals, a test clock input terminal, a logic circuit having at least an input node, a first output node, and a second output node; Input data externally applied to the input terminal is supplied to the input node of the logic circuit, and output data output from the first output node and the second output node of the logic circuit is supplied to the output terminal. An integrated circuit comprising a test circuit,
The test circuit outputs a sequencer whose state transitions in synchronization with a clock applied to the test clock input terminal, and outputs from the first output node and the second output node of the logic circuit according to the state of the sequencer An output selection circuit for selecting output data to be output,
Input data externally applied to the input terminal is directly supplied to the input node of the logic circuit, and output data output from the first output node of the logic circuit is selected by the output selection circuit and the output Then, output data output from the second output node of the logic circuit is selected by the output selection circuit and supplied to the output terminal.
[0012]
In order to achieve this object, the integrated circuit includes at least a pair of input terminals and output terminals, a test clock input terminal, at least a first input node, a second input node, a first output node, and a second output node. A logic circuit comprising: a logic circuit; and input data externally applied to the input terminal to the first input node and the second input node of the logic circuit, and the first output node and the second input node of the logic circuit An integrated circuit including a test circuit for supplying output data output from an output node to the output terminal,
The test circuit includes a flip-flop that holds input data supplied from the outside to the input terminal in synchronization with a clock applied to the test clock input terminal, and a clock that is applied to the test clock input terminal. A sequencer whose state transitions; and an output selection circuit that selects output data output from the first output node and the second output node of the logic circuit according to the state of the sequencer;
First, input data given first from the outside to the input terminal is temporarily held by the flip-flop and supplied to the second input node of the logic circuit, and input data given next from the outside directly to the input terminal directly The output data is supplied to the first input node of the logic circuit, the output data output from the first output node of the logic circuit is selected by the output selection circuit, supplied to the output terminal, and then the first output node of the logic circuit. Output data output from the two output nodes is selected by the output selection circuit and supplied to the output terminal.
[0013]
In order to achieve this object, the integrated circuit includes a test mode state holding means, another input terminal, and an input selection circuit connected to the second input node of the logic circuit.
When the test mode state is indicated by the test mode state holding means, the input selection circuit selects a value held by the flip-flop, and when the test mode state holding means indicates a normal operation state, the input selection circuit 4. The integrated circuit according to claim 1, wherein input data given from outside is selected to another input terminal.
[0014]
In order to achieve this object, the integrated circuit includes a second other input terminal and a second input selection circuit.
The logic circuit further includes a third input node, and the test circuit further includes a second flip-flop connected in series to the output of the flip-flop,
The second input selection circuit is connected to the third input node;
When the test mode state is indicated by the test mode state holding means, the input selection circuit and the second input selection circuit respectively select a value held by the flip-flop and a value held by the second flip-flop, When the normal operation state is indicated by the test mode state holding means, the input selection circuit and the second input selection circuit are input data externally applied to the other input terminal and the second other input terminal, respectively. The integrated circuit according to claim 4, wherein: is selected.
[0015]
In order to achieve this purpose, the integrated circuit has a clock input terminal,
The logic circuit further includes a clock input node connected to the clock input terminal,
6. The logic circuit according to claim 1, wherein the logic circuit operates based on a clock that is externally supplied to the clock input terminal and has a shorter cycle than a clock applied to the test clock input terminal. The integrated circuit according to any one of claims.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0017]
FIG. 1 is a block diagram of an integrated circuit according to an embodiment of the present invention.
[0018]
In the figure, the integrated circuit 10 is composed of a logic circuit 11 and a test circuit 12, and the test circuit 12 is provided with a sequencer including flip-flop circuits 13 and 14 and selection circuits 15 and 16 on the input side of the logic circuit 11. The output side of the logic circuit 11 is composed of a sequencer composed of flip-flop circuits 17 and 18 and a selection circuit 19. Further, TIN1, TIN2, TIN3, TCLK, MOD, CLK, TOEN, TOUT1, TOUT2, and TOUT3 are terminals, and the input D of the flip-flop circuit 17 is fixed to “1”.
[0019]
Here, it is assumed that the logic circuit 11 has the most critical signal propagation from IN1 to OUT1.
[0020]
During normal operation of the integrated circuit 10, the operation mode terminal MOD, the test clock input terminal TCLK are fixed to "0", the test output enable terminal TOEN is fixed to "1", and the inputs TIN1 to TIN1 to TIN1 of the integrated circuit 10 are directly input nodes. IN1 and TIN2 and TIN3 are respectively logically connected directly to the input nodes IN2 and IN3 of the logic circuit 11 via the selection circuits 15 and 16 that have received the input data “0” of the input MOD of the integrated circuit 10, respectively. Thus, the output node OUT1 of the logic circuit 11 is connected to the output TOUT1 of the integrated circuit 10 via the selection circuit 19, and the output nodes OUT2 and OUT3 are directly connected to TOUT2 and TOUT3. Therefore, during normal operation, the outputs OUT1, OUT2, and OUT3 of the logic circuit 10 can be obtained from TOUT1, TOUT2, and TOUT3 by inputting the data of IN1, IN2, and IN3 to TIN1, TIN2, and TIN3.
[0021]
During the test operation of the integrated circuit 10, the test is performed without using TIN2, TIN3, TOUT2, and TOUT3. TIN1 is connected to IN1 and the input D of the flip-flop circuit 13, and the output Q of the flip-flop circuit 13 is supplied to the selection circuit 15 that has received the input data "1" of the input D of the flip-flop circuit 14 and the input MOD of the integrated circuit 10. Further, the output Q of the flip-flop circuit 14 is connected to IN3 via the selection circuit 16 that has received the MOD input data “1”. The input D of the flip-flop circuit 17 is always “1”, the output Q of the flip-flop circuit 17 is connected to the input D of the flip-flop circuit 18 and the selection circuit 19, and the output Q of the flip-flop circuit 18 is selected. The reset R of the flip-flop circuits 17 and 18 is connected to the circuit 19 and is connected to the input TOEN of the integrated circuit 10. TOUT1 is connected to OUT1 when the MOD input data is "1" and the outputs Q of the flip-flop circuits 17 and 18 are both "0". The MOD input data is "1" and the output Q of the flip-flop circuit 17 is OUT2 is connected when “1” and the output Q of the flip-flop circuit 18 is “0”, and OUT3 is connected when the input data of the MOD is “1” and the outputs Q of the flip-flop circuits 17 and 18 are both “1”. Is done.
[0022]
Next, the operation at each timing during the test operation will be described with reference to the timing chart of FIG.
[0023]
First, in each cycle t0 to t4, arbitrary input data is input from TIN1, and input data from TIN1 is directly input to IN1. A clock signal is input from TCLK at regular intervals, and “1” is always input to MOD.
[0024]
In the t0 cycle, data from TIN1 to IN3 is input.
[0025]
In the t1 cycle, the flip-flop circuit 13 holds the data of IN3 from TIN1 at the rising edge of TCLK. Data from TIN1 to IN2 is input.
[0026]
In the t2 cycle, the flip-flop circuit 14 holds the data of IN3 from the flip-flop circuit 13 at the rising edge of TCLK, and supplies the data to IN3 via the selection circuit 16. Further, the data of IN2 from TIN1 is held by the flip-flop circuit 13 and supplied to IN2 via the selection circuit 15. Further, the IN1 data is supplied from TIN1 to IN1, and the logic circuit 11 is operated by inputting a clock signal from CLK of the integrated circuit 10, and the output data of OUT1 is output to TOUT1 by inputting “1” from TOEN. Is output. As a result, in this t2 cycle, the propagation path of the logic circuit including the latch circuit can be tested and observed at TIN1 and TOUT1 at the same timing as the normal operation with respect to IN1 and OUT1, and the timing from IN1 to OUT1 is the most critical. The AC spec for propagation can be verified.
[0027]
In the t3 cycle, “1” is output from the output Q of the flip-flop circuit 17 and “0” is output from the output Q of the flip-flop circuit 18 in synchronization with the rising edge of the clock signal from TCLK, whereby the output of OUT2 is output to TOUT1. Data is output.
[0028]
In the t4 cycle, both “1” are output from the outputs Q of the flip-flop circuits 17 and 18 in synchronization with the rising edge of the clock signal from TCLK, whereby the output data of OUT3 is output to TOUT1.
[0029]
【The invention's effect】
As described above, the integrated circuit includes at least a pair of input terminals and output terminals, a test clock input terminal, a logic circuit having at least a first input node, a second input node, and an output node, and the input terminals. A test circuit that supplies externally applied input data to the first input node and the second input node of the logic circuit, and supplies output data output from the output node of the logic circuit to the output terminal; An integrated circuit comprising:
The test circuit includes a flip-flop that holds input data externally applied to the input terminal in synchronization with a clock applied to the test clock input terminal,
First, input data given first from the outside to the input terminal is temporarily held by the flip-flop and supplied to the second input node of the logic circuit, and input data given next from the outside directly to the input terminal directly The integrated circuit can be tested with a small number of test pins by supplying the first input node of the logic circuit and supplying the output data output from the output node of the logic circuit directly to the output terminal. And the AC characteristics of the most critical propagation path can be observed.
[0030]
The integrated circuit also includes a logic circuit having at least a pair of input and output terminals, a test clock input terminal, at least an input node, a first output node, and a second output node, and externally applied to the input terminal. Integrated with a test circuit that supplies input data to the input node of the logic circuit and supplies output data output from the first output node and the second output node of the logic circuit to the output terminal. A circuit,
The test circuit outputs a sequencer whose state transitions in synchronization with a clock applied to the test clock input terminal, and outputs from the first output node and the second output node of the logic circuit according to the state of the sequencer An output selection circuit for selecting output data to be output,
Input data externally applied to the input terminal is directly supplied to the input node of the logic circuit, and output data output from the first output node of the logic circuit is selected by the output selection circuit and the output The output data output from the second output node of the logic circuit is then selected by the output selection circuit and supplied to the output terminal, thereby testing the integrated circuit with a small number of test pins. And the AC characteristics of the most critical propagation path can be observed.
[0031]
The integrated circuit also includes a logic circuit having at least a pair of input and output terminals, a test clock input terminal, and at least a first input node, a second input node, a first output node, and a second output node; Input data externally applied to the input terminal is supplied to the first input node and the second input node of the logic circuit, and is output from the first output node and the second output node of the logic circuit. An integrated circuit comprising a test circuit for supplying output data to the output terminal,
The test circuit includes a flip-flop that holds input data supplied from the outside to the input terminal in synchronization with a clock applied to the test clock input terminal, and a clock that is applied to the test clock input terminal. A sequencer whose state transitions; and an output selection circuit that selects output data output from the first output node and the second output node of the logic circuit according to the state of the sequencer;
First, input data given first from the outside to the input terminal is temporarily held by the flip-flop and supplied to the second input node of the logic circuit, and input data given next from the outside directly to the input terminal directly The output data is supplied to the first input node of the logic circuit, the output data output from the first output node of the logic circuit is selected by the output selection circuit, supplied to the output terminal, and then the first output node of the logic circuit. By selecting the output data output from the two output nodes by the output selection circuit and supplying it to the output terminal, the integrated circuit can be tested with a small number of test pins, and the most critical propagation path can be tested. AC characteristics can be observed.
[0032]
The integrated circuit includes a test mode state holding unit, another input terminal, and an input selection circuit connected to the second input node of the logic circuit,
When the test mode state is indicated by the test mode state holding means, the input selection circuit selects a value held by the flip-flop, and when the test mode state holding means indicates a normal operation state, the input selection circuit 4. The integrated circuit according to claim 1, wherein input data externally applied to another input terminal is selected, the integrated circuit can be tested with a small number of test pins, and most critical. AC characteristics of a simple propagation path can be observed.
[0033]
The integrated circuit includes a second other input terminal and a second input selection circuit,
The logic circuit further includes a third input node, and the test circuit further includes a second flip-flop connected in series to the output of the flip-flop,
The second input selection circuit is connected to the third input node;
When the test mode state is indicated by the test mode state holding means, the input selection circuit and the second input selection circuit respectively select a value held by the flip-flop and a value held by the second flip-flop, When the normal operation state is indicated by the test mode state holding means, the input selection circuit and the second input selection circuit are input data externally applied to the other input terminal and the second other input terminal, respectively. The integrated circuit according to claim 4, wherein the integrated circuit can be tested with a small number of test pins, and the AC characteristics of the most critical propagation path can be observed.
[0034]
The integrated circuit includes a clock input terminal,
The logic circuit further includes a clock input node connected to the clock input terminal,
6. The logic circuit according to claim 1, wherein the logic circuit operates based on a clock that is externally supplied to the clock input terminal and has a shorter cycle than a clock applied to the test clock input terminal. The integrated circuit according to any one of the above items, the integrated circuit can be tested with a small number of test pins, and the AC characteristics of the most critical propagation path can be observed.
[Brief description of the drawings]
FIG. 1 is a block diagram of an integrated circuit according to an embodiment of the present invention. FIG. 2 is a timing chart during a test operation of the integrated circuit according to an embodiment of the present invention. 4 Block diagram of second conventional integrated circuit [Explanation of symbols]
3, 4 Integrated circuit 5 Logic circuit 10 Integrated circuit 11 Logic circuit 12 Test circuit 13, 14, 17, 18 Flip-flop circuit 15, 16, 19 Select circuit

Claims (4)

A logic circuit having at least a pair of input and output terminals, a test clock input terminal, at least a first input node, a second input node, an output node, and a clock input node; and an input given to the input terminal from the outside Data is supplied to the first input node and the second input node of the logic circuit, and output data output from the output node of the logic circuit is supplied to the output terminal and to the clock input node An integrated circuit having a connected clock input terminal ,
The test circuit includes a flip-flop that holds input data externally applied to the input terminal in synchronization with a clock applied to the test clock input terminal,
First, input data given first from the outside to the input terminal is temporarily held by the flip-flop and supplied to the second input node of the logic circuit, and input data given next from the outside directly to the input terminal directly Supplying to the first input node of the logic circuit, supplying output data output from the output node of the logic circuit directly to the output terminal, and applying a clock applied to the clock input terminal to the test clock input terminal An integrated circuit characterized in that it is different from the clock to be generated . The integrated circuit further comprises test mode state holding means, another input terminal, and an input selection circuit connected to the second input node of the logic circuit,
When the test mode state is indicated by the test mode state holding means, the input selection circuit selects a value held by the flip-flop, and when the test mode state holding means indicates a normal operation state, the input selection circuit the integrated circuit of claim 1, wherein the selecting the input data supplied from the outside to the other input terminal. The integrated circuit further includes a second other input terminal and a second input selection circuit,
The logic circuit further includes a third input node, and the test circuit further includes a second flip-flop connected in series to the output of the flip-flop,
The second input selection circuit is connected to the third input node;
When the test mode state is indicated by the test mode state holding means, the input selection circuit and the second input selection circuit respectively select a value held by the flip-flop and a value held by the second flip-flop, When the normal operation state is indicated by the test mode state holding means, the input selection circuit and the second input selection circuit are input data externally applied to the other input terminal and the second other input terminal, respectively. The integrated circuit according to claim 2 , wherein: is selected. The clock supplied from the outside to the clock input terminal operates based on a clock having a shorter cycle than the clock applied to the test clock input terminal.
The integrated circuit according to claim 1, wherein:

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