JPS63159773A - Test system for highly integrated circuit - Google Patents

Abstract

PURPOSE:To conduct a fast propagation test equivalently even by a relatively slow LSI tester by shifting the phase of a clock signal which is supplied from the LSI tester to clock input terminals of respective FFs of an LSI. CONSTITUTION:This test system uses the LSI tester which outputs the clock signal at constant cycle time and outputs clock signals which are in optional phase and have optional pulse widths in respective cycles, and the clock signal which is supplied from the LSI tester to clock input terminals of respective FFs I - IV of the LSI 1 is shifted in phase to obtain a clock which is narrowed down in interval in every cycle so that positions of intervals to be narrowed down for 1st and 2nd times are different. For example, the clock is narrowed down in interval between an even and an odd cycle for the 1st time and between an odd and an even cycle for the 2nd time. Those two kinds of clocks are used and the LSI is tested twice, so a fast test is conducted by the relatively slow LSI tester as well as a fast LSI tester.

Description

[Detailed Description of the Invention] [Summary] A highly integrated circuit testing machine (LSI
In a highly integrated circuit testing method using a tester, for example, in the first test, the clock interval between even and odd cycles is narrowed, and in the second test, the clock interval between odd and even cycles is narrowed. Highly integrated circuit (LSI) is tested twice using two types of clocks.
It was designed to test.

[Industrial application field]

The present invention relates to a method for testing high-speed highly integrated circuits (LSI) using a highly integrated circuit tester (LSI tester).

With recent advances in semiconductor technology, logic elements have become highly integrated (
Computer systems using LSI devices are becoming faster and faster, and the period of the clock supplied to the LSI devices is increasing.
There is a trend towards further shortening.

On the other hand, LSI testers that test highly integrated (LSI) devices are currently unable to output short clock pulses of less than a certain period, and are unable to follow the clock period of the computer system.

However, in each cycle of the clock signal output at the constant cycle time, a clock signal having an arbitrary phase and an arbitrary pulse width can be output.

There is a need for a method of testing highly integrated (LSI) circuits that operate at high speed, that is, with short clock cycles, by taking advantage of the characteristics of LSI testers.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram showing a conventional method for testing the propagation time of a circuit between PP and FF.

-i, to test the propagation time of the circuit between flip-flops (FF-FP), the period τ
The pulse train (clock) of
It is possible to do this by inputting the signal to the clock terminal of FP 1 (referred to as FP) and observing the output signal (data) from the output bin of the final stage FP. If 11tsi is operating normally, the data delay time is confirmed to be shorter than the clock cycle τ as shown in the figure.

However, in this method, it is usually necessary to set the period τ to be the same as the clock of the logic device in which the LSI is actually used.
There was a problem with the need for a tester.

In general, high-speed LSI testers are extremely expensive, and LSI testers that can keep up with the recent trends in increasing the speed of logic devices are
The problem was that it didn't actually exist.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide an LSI test method that enables equivalently high-speed propagation tests even with a relatively low-speed LSI tester.

[Means for solving problems]

FIG. 1 is a diagram schematically showing the LSI test method of the present invention.

In the present invention, an LSI tester using a highly integrated circuit tester (LSI tester) outputs a clock signal at a constant cycle time, and in each cycle outputs a clock signal with an arbitrary phase and an arbitrary pulse width. The test method includes each flip-flop (FF) (,1
The phase of the clock signal from the LSI tester supplied to the clock input terminal of ~■) is shifted to generate a clock whose clock interval is narrowed from T to t for each cycle, and at the first and second times. In this test, two tests were performed using clocks in which the positions of the narrowing intervals were different (the first time, the space between odd and even cycles was narrowed, and the second time, the space between even and odd cycles was narrowed). A highly integrated circuit 1 is configured to be tested.

[Effect]

That is, according to the present invention, a highly integrated circuit testing machine (LSI tester) is provided which outputs a clock signal at a constant cycle time, and in each cycle outputs a clock signal with an arbitrary phase and an arbitrary pulse width. In the high-integration circuit test method used, for example, in the first test, the clock interval between even and odd cycles was narrowed, and in the second test, the clock interval between odd and even cycles was narrowed; Since the clock is used to test highly integrated circuits (LSI) in two tests, it is possible to perform tests similar to high-speed LSI tests with relatively low-speed LSI tests. There is.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram schematically showing the LSI test method of the present invention, and FIG. 2 is a diagram showing an example of a circuit for performing an LSI test. Means for supplying the clock outputted from the tester to the clock terminal of the circuit shown in FIG. 2 by making the phase of each cycle of the clock different between the first test and the second test implements the present invention. It is a necessary means to do so. Note that the same reference numerals indicate the same objects throughout the figures.

In this embodiment, as shown in FIG. 2, four stages (■ to ■) of flip-flops (hereinafter referred to as FP) are connected.
The following explanation assumes that a combinational circuit is placed between them, and that the propagation time in the combinational circuit is tested.

In Figure 1, for convenience of explanation, the conventional method is shown on the left side.
The test method of the present invention is shown on the right.

In the conventional system, as shown in the figure, a clock and data are supplied to each FP (1 to ■) of the LSI 1 at a period τ.

At this time, the data taken into the first 0FF (1) at clock 80 is transferred to the second FF (II) at the next clock 80. At this time, the data transfer time between the first PF (I) and the second 0FF (n) is checked with =data.

Similarly, at clock C0, the transfer times between the first and second and the second and third are E:l@
Checked with 0 data. Also, in the case of clock D, the transfer time between each FF is checked using color data, and it is confirmed that the data delay time between FFs is shorter than τ.

In this conventional method, the data transfer speed between the FFs is L
Since this is the same as the operating clock τ of the SI tester, it is not possible to test LSIs whose propagation speed is faster than the clock τ.

Therefore, in the present invention, the right side of FIG.
), the phases of the conventional B clock and D clock are shifted forward, and the clock interval is shortened to T==>t every other cycle as shown in the figure. is the same as the clock cycle of the actual device. Further, data is supplied to the integrated circuit (see FIG. 2) at each test period determined by the operating period of the SI tester.

The operation of the circuit when implementing the present invention is as follows.

First, in the first test, the data of ■ is taken into the first PF (■) at the timing of the A1 clock. Next, the data is transferred to the second PP(n) using the clock of B+, and at this time a delay time of t is guaranteed. Furthermore,
D. Even in the case of a clock, it is possible to transfer data between each FF in t.

As a result, the data transfer test between the A clock, the B clock, and the CI clock could be tested using the clock cycle t of the actual device, but when using the C1 clock, the previous B. The interval with the clock is T, which is larger than the clock cycle t of the actual device, so in the example shown, the log data is the first 0FF (1).
and the second 0FF (II), and the time it takes the country data to transfer between the second PF (u) and the third FF (I Guaranteed transferability has not been tested.

Therefore, in the present invention, the conventional C clock is shifted forward (indicated by C2 clock), as shown on the right side of the figure (indicated by the second time), and the same test is performed one more time.

By doing this, at the time of C2 clock, the transfer between the first 0FF (1) and the second 0FF (II) of the @Lo data that could not be tested before, and the transfer between the second FF (n
) and the third FP (III) can be tested.

As described above, the present invention focuses on the characteristic that even if the speed of the clock output from an LSI tester is relatively low, the phase of the clock pulse can be shifted in each cycle of the clock. For example, by narrowing the clock interval between an odd cycle and an even cycle or between an even cycle and an odd cycle, supplying the two types of clocks to the LSI under test, and performing two tests to obtain an equivalent result. The feature is that the test is performed using a relatively high-speed clock.

C. Effects of the Invention] As explained above in detail, the highly integrated circuit testing method of the present invention outputs a clock signal at a constant cycle time, and in each cycle, outputs a clock signal at an arbitrary phase and at an arbitrary pulse. Highly integrated circuit testing machine that outputs a wide clock signal (
In a highly integrated circuit testing method using an LSI tester, for example, in the first test, the clock interval between even and odd cycles is narrowed, and in the second test, the clock interval between odd and even cycles is narrowed, Highly integrated circuit (
Since the tester is designed to test LSI), it has the advantage that a relatively slow LSI tester can perform the same tests as a high-speed LSI tester.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the LSI test method of the present invention. FIG. 2 is a diagram showing an example of a circuit for performing an LSI test. FIG. 3 is a diagram showing a conventional method for testing the propagation time of a circuit between FFs. It is. In the drawing, 1 is a highly integrated line (LSI). ■～■ are flip-flops (FF). τ, t, and T are clock periods. Eight o ~ Ilo, A + ~ Dr Az ~
Dz is clock. Roro Garden is data. are shown respectively.

Claims (1)

[Claims] A highly integrated circuit testing method using a highly integrated circuit testing machine that outputs a clock signal at a constant cycle time, and in each cycle outputs a clock signal with an arbitrary phase and an arbitrary pulse width. The clock signal is supplied to the clock input terminal of the highly integrated circuit (1) from the highly integrated circuit testing machine, and the phase of the clock signal from the highly integrated circuit testing machine is shifted to narrow the clock interval for each cycle. and, using clocks with different positions of the narrowing interval, 2
A highly integrated circuit testing method characterized by testing highly integrated circuits in multiple tests.