JP2007114031A - Semiconductor device and electronic equipment employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of exclusive input/output terminals required for a semiconductor device having a plurality of test functions, and to make the semiconductor device compact in order to lower its cost. <P>SOLUTION: The semiconductor device 1 which controls timing information, is composed of an oscillator circuit 100 for generating a reference signal and a drive circuit 200 for dividing the reference signal and generating a drive signal. The drive circuit 200 comprises: a first dividing circuit 210 which inputs the reference signal and outputs a first divided signal; a first input signal switching circuit 220 which is controlled by a first control signal for selecting the first divided signal or a test-use acceleration clock signal; a second dividing circuit 230 which inputs an output signal of the first input signal switching circuit 220 and outputs a second divided signal; a second input signal switching circuit 240 which is controlled by a second control signal for selecting the second divided signal or the test-use acceleration clock signal; and a third dividing circuit 250 which inputs an output signal of the second input signal switching circuit 240 and outputs the drive signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device and an electronic apparatus including the same, and more particularly to a semiconductor device for evaluating a timekeeping function.

Conventionally, a semiconductor device that performs characteristic evaluation or function evaluation test by external control,
In order to perform a test by inputting a test signal and install a test mode with multiple test functions, an input terminal for controlling the transition from the normal mode to the test mode, a test signal input terminal, a test function switching signal Three test input terminals or a larger number of test function switching input terminals corresponding to the number of test functions is required.

In order to solve this problem, for example, in Patent Document 1, although there is an acceleration clock input control signal for each frequency-division stage to be accelerated for the acceleration clock input for testing the frequency divider circuit, There is no regularity about the frequency of the frequency dividing circuit to be arbitrarily selected.

JP 2002-184865 A

However, in Patent Document 1, since the frequency of the frequency-dividing circuit to be accelerated is arbitrarily set, it is possible to install a plurality of acceleration clock inputs at any frequency-dividing stage and make full use of simultaneous clock input or the like. There were cases where the number of clock inputs increased, which had an effect on test time (test cost).

The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor device capable of reducing the number of test terminals and shortening the test time.

<Invention 1>
In order to solve the above problems, a semiconductor device according to the present invention includes an oscillation circuit that generates a reference signal and a drive circuit that divides the reference signal to generate a drive signal, and has a clocking function based on the drive signal. In the semiconductor device to be controlled, the drive circuit has a test acceleration clock signal for accelerating and outputting the drive signal, and inputs the reference signal and outputs a first divided signal. A first input signal switching circuit controlled by a first control signal that selects whether to output the first frequency-divided signal or to output the test acceleration clock signal; A second frequency dividing circuit that inputs an output signal of the first input signal switching circuit and outputs a second frequency-divided signal; and outputs the second frequency-divided signal or the test acceleration clock Select whether to output a signal A second input signal switching circuit controlled by a second control signal; and a third frequency dividing circuit for inputting the output signal of the second input signal switching circuit and outputting the drive signal. Is the gist.

According to this configuration, the driving circuit is made to select the test acceleration clock signal for the first control signal and the second control signal, and the predetermined number of test acceleration clock signals are supplied to the second frequency divider circuit. Are simultaneously input to the third frequency divider circuit, the second control signal is switched to a state in which the second frequency divided signal is selected, and the remaining number of test acceleration clock signals are input to the second frequency divider circuit. As a result, the drive signal can be output with a small number of test acceleration clock signals, and the test time can be shortened.

<Invention 2>
In the semiconductor device of the present invention, each of the frequency dividing ratio of the first frequency dividing circuit, the frequency dividing ratio of the second frequency dividing circuit, and the frequency dividing ratio of the third frequency dividing circuit is: Each of the frequency of the first frequency-divided signal, the frequency of the second frequency-divided signal, and the frequency of the drive signal is set to be a power of a predetermined natural number n.

According to this configuration, the first control signal and the second control signal are selected for the test acceleration clock signal for the drive circuit, and the number of tests obtained by subtracting 1 from the frequency of the second divided signal is set. Acceleration clock signal for input is simultaneously input to the second frequency divider circuit and the third frequency divider circuit, and then the second control signal is switched to a state in which the second frequency divider signal is selected, and the remaining number of test accelerations By inputting the clock signal to the second frequency dividing circuit, the drive signal can be output with a small number of test acceleration clock signals, and the test time can be shortened.

<Invention 3>
In the semiconductor device of the present invention, the frequency of the first divided signal is the square of the predetermined natural number n, the frequency of the second divided signal is the first power of the predetermined natural number n, and the drive signal. Is the predetermined natural number n to the 0th power.

According to this configuration, the first control signal and the second control signal are set to a state in which the test acceleration clock signal is selected, and the test acceleration clock signals of the number obtained by subtracting 1 from the frequency of the second frequency division signal are obtained. After being simultaneously input to the second frequency divider circuit and the third frequency divider circuit, the second control signal is switched to a state in which the second frequency divided signal is selected, and the remaining number of test acceleration clock signals are changed to the second frequency signal. By inputting to this frequency divider circuit, the drive signal can be output with a small number of test acceleration clock signals, and the test time can be shortened.

<Invention 4>
Next, an electronic apparatus according to the present invention includes the above-described semiconductor device, and corresponds to, for example, an electronic timepiece, a personal computer, a mobile phone, and a portable information terminal.

Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. In the present embodiment, an analog electronic timepiece as an electronic device that inputs a test acceleration clock signal and performs an acceleration test of a drive circuit will be described, but the present invention is not limited to this, The present invention can be applied to any semiconductor device provided with a test mode for inputting a signal for predetermined function evaluation and an electronic device using the semiconductor device. For example, a digital electronic timepiece may be used.
(First embodiment)

<Configuration of semiconductor device>
FIG. 1 is a block diagram showing the configuration of the semiconductor device according to the first embodiment of the present invention. As shown in the figure, the semiconductor device 1 includes an oscillation circuit 100, a drive circuit 200, a carry generation circuit 300, a clock counter 310 that is a timekeeping function, a three-wire serial interface control circuit 400, a system A control register 500 and a bus 600 are included.

The oscillation circuit 100 generates a reference signal V0 and outputs it to the drive circuit 200. Drive circuit 20
0 inputs the reference signal V0 and generates the drive signal V3.

The 3-wire serial interface control circuit 400 is controlled by a data input / output signal DIO, a clock signal CLK, and a chip enable signal CE from an external device (not shown), and outputs a control signal to the bus 600. The data input / output signal DIO is a first control signal that is a first control signal.
A control signal C1, a second control signal C2 that is a second control signal, and a signal that controls the reset signal are included. The 3-wire serial interface control circuit 400 writes serial data of the data input / output signal DIO to the system control register 500 via the bus 600 based on the timing of the clock signal CLK while the chip enable signal CE is High.

The system control register 500 holds a first control signal C1, a second control signal C2, and a reset signal.

The driving circuit 200 further includes a first frequency dividing circuit 210 that is a first frequency dividing circuit, a first input signal switching circuit 220 that is a first input signal switching circuit, and a second frequency dividing circuit. This circuit includes a divide-by-2 circuit 230, a second input signal switch circuit 240 that is a second input signal switch circuit, and a third divider circuit 250 that is a third divider circuit.

The first frequency dividing circuit 210 receives the reference signal V0 and receives a first frequency divided signal V1 that is a first frequency divided signal.
And carry reference signal V4. The first input signal switching circuit 220 selects the first frequency-divided signal V1 or the test acceleration clock signal TEST by the first control signal C1 and selects the first output signal S.
Output to 1. The first input signal switching circuit 220 outputs the first frequency-divided signal V1 to the first output signal S1 when the first control signal C1 is Low, and the test acceleration clock signal TEST when the first control signal C1 is High. Output to the first output signal S1.

The second divider 230 receives the first output signal S1 and outputs a second divided signal V2 that is a second divided signal. The second input signal switching circuit 240 selects the second frequency-divided signal V2 or the test acceleration clock signal TEST by the second control signal C2, and outputs the selected signal to the second output signal S2. The second input signal switching circuit 240 outputs the second divided signal V2 to the second when the second control signal C2 is Low.
When the second control signal C2 is High, the test acceleration clock signal T is output to the output signal S2.
EST is output to the second output signal S2.

  The third frequency divider 250 receives the second output signal S2 and outputs the drive signal V3.

The carry generation circuit 300 receives the drive signal V3 and the carry reference signal V4, and receives the drive signal V3.
When the carry reference signal V4 is Low, the carry signal UP is output High. The clock counter 310 performs a carry when the carry signal UP changes from Low to High.

During the period when the reset signal is High, the first frequency divider 210, the second frequency divider 230, and the third
The frequency dividing circuit 250 and the internal node of the carry generating circuit 300 are reset to Low, and the first frequency dividing signal V1, the second frequency dividing signal V2, the drive signal V3, and the carry signal UP are reset to Low. The

Next, a method for accelerating the clock counter 310 faster than the normal operation in the semiconductor device 1 and performing an acceleration test of the timekeeping function will be described.

<When test acceleration clock signal is not used>
First, the output of the carry signal when the test acceleration clock signal is not used will be described with reference to FIG. FIG. 2 is a timing chart for explaining the output of the carry signal when the test acceleration clock signal is not used.

When the test acceleration clock signal TEST is not used, an acceleration test of the timekeeping function is performed based on the reference signal V0 generated from the oscillation circuit 100.

Here, the frequency of the reference signal V0 generated from the oscillation circuit 100 is 32768 Hz, the frequency dividing ratio of the first frequency dividing circuit 210 is 1/32, the frequency dividing ratio of the second frequency dividing circuit 230 is 1/32, The frequency dividing ratio of the frequency dividing circuit 250 is 1/32. In this case, the frequency of the first divided signal V1 is 10
24 Hz, the frequency of the second frequency-divided signal V2 is 32 Hz, and the frequency of the drive signal V3 is 1 Hz. The carry reference signal V4 always outputs 1024 Hz.

The clock signal CLK operates from the time point t1 to the time point t2 in FIG. 2 when the chip enable signal CE is High. The reset signal = High from the data input / output signal DIO, the first
The control signal C1 = Low and the second control signal C2 = Low are transmitted, and the system control register 5
Written to 00.

During the period from time t3 to time t4, the current value of the clock counter 310 is read and transmitted from the data input / output signal DIO to the external device.

The reference signal V0 is output 32768 from time t5, and the drive signal V3 is Low at time t6.
Thus, the carry reference signal V4 is also Low. At time t6, the carry signal UP becomes High. Further, when 16 reference signals V0 are output from time t6, carry reference signal V4 changes to High at time t7, and carry signal UP also changes to Low. Carry signal UP is Low
At the time of transition to, the value of the clock counter 310 is carried.

During the period from time t8 to time t9, the current value of the clock counter 310 is read and transmitted from the data input / output signal DIO to the external device.

According to the above method, in order to carry one carry of the clock counter 310, the reference signal V
0 must be output 32768 + 16 = 32784, and the efficiency of the accelerated inspection cannot be increased.

<When the first divided signal and the second divided signal are not in a power relationship>
Next, the output of the carry signal when the first divided signal and the second divided signal are not in a power relationship will be described with reference to FIG. FIG. 3 is a timing chart for explaining the output of the carry signal when the first divided signal and the second divided signal are not in a power relationship.

Here, the frequency of the reference signal V0 generated from the oscillation circuit 100 is 32768 Hz, the frequency dividing ratio of the first frequency dividing circuit 210 is 1/8, the frequency dividing ratio of the second frequency dividing circuit 230 is 1/128, The frequency dividing ratio of the frequency dividing circuit 250 is 1/32. In this case, the frequency of the first divided signal V1 is 40.
96 Hz, the frequency of the second frequency-divided signal V2 is 32 Hz, and the frequency of the drive signal V3 is 1 Hz. The carry reference signal V4 always outputs 1024 Hz. In this case, the frequency of the first frequency-divided signal V1, the frequency of the second frequency-divided signal V2, and the frequency of the drive signal V3 are not in a power relationship. Further, it is assumed that a test acceleration clock signal TEST is input from an external device at a frequency of 4096 Hz.

The clock signal CLK operates from the time point t1 to the time point t2 in FIG. 3 when the chip enable signal CE is High, and the reset signal = High from the data input / output signal DIO, the first
The control signal C1 = High and the second control signal C2 = High are transmitted and written to the system control register 500.

During the period from time t3 to time t4, the current value of the clock counter 310 is read and transmitted from the data input / output signal DIO to the external device.

Since the first control signal C1 = High and the second control signal C2 = High, the first input signal switching circuit 220 and the second input signal switching circuit 240 cause the first output signal S1 and the second output signal S2 to be the test acceleration clock. A signal TEST is output. From time t5, 31 test acceleration clock signals TEST are output. At time t6, the second frequency-divided signal V2 is in the state of 31/128, and the drive signal V3 is in the state of 31/32.

Next, during the period from the time point t7 to the time point t8, the data input / output signal DIO to the second control signal C2
= Low is transmitted and written to the system control register 500. Since the second control signal C2 transitions to Low at time t8, the second output signal S2 is transferred by the second input signal switching circuit 240.
The second frequency-divided signal V2 is output at.

From time t9, 97 test acceleration clock signals TEST are output, and at time t10, the second
The frequency-divided signal V2 is (31 + 97) / 128, and one clock is output from the second frequency-divided signal V2. As a result, the drive signal V3 becomes (31 + 1) / 32, the drive signal V3 becomes Low, and the carry reference signal V4 also becomes Low.

At time t10, the carry signal UP becomes High. Further, when two test acceleration clock signals TEST are output from time t10, the carry reference signal V4 changes to High at time t11, and the carry signal UP also changes to Low. When the carry signal UP changes to Low, the value of the clock counter 310 is carried.

During the period from time t12 to time t13, the current value of the clock counter 310 is read and transmitted from the data input / output signal DIO to the external device.

According to the above method, in order to carry one carry of the clock counter 310, it is necessary to output 31 + 97 + 2 = 130 test acceleration clock signals TEST, and the efficiency of the acceleration test cannot be increased.

<When the first divided signal and the second divided signal are in a power relationship>
Next, the output of the carry signal when the first divided signal and the second divided signal are in a power relationship will be described with reference to FIG. FIG. 4 is a timing chart for explaining the output of the carry signal when the first divided signal and the second divided signal are in a power relationship.

Here, the frequency of the reference signal V0 generated from the oscillation circuit 100 is 32768 Hz, the frequency dividing ratio of the first frequency dividing circuit 210 is 1/8, the frequency dividing ratio of the second frequency dividing circuit 230 is 1/64, The frequency dividing ratio of the frequency dividing circuit 250 is 1/64. In this case, the frequency of the first divided signal V1 is 409.
6 (= 64 squared) Hz, the frequency of the second divided signal V2 is 64 (= 64 raised to the 1st power) Hz, and the frequency of the driving signal V3 is 1 (= 64 raised to the 0th power) Hz. The carry reference signal V4 always outputs 1024 Hz. In this case, the frequency of the first frequency-divided signal V1, the frequency of the second frequency-divided signal V2, and the frequency of the drive signal V3 are in a relation of powers of natural numbers n = 64. Further, it is assumed that a test acceleration clock signal TEST is input from an external device at a frequency of 4096 Hz.

The clock signal CLK operates from the time point t1 to the time point t2 in FIG. 4 when the chip enable signal CE is High, and the reset signal = High from the data input / output signal DIO, the first
The control signal C1 = High and the second control signal C2 = High are transmitted and written to the system control register 500.

During the period from time t3 to time t4, the current value of the clock counter 310 is read and transmitted from the data input / output signal DIO to the external device.

Since the first control signal C1 = High and the second control signal C2 = High, the first input signal switching circuit 220 and the second input signal switching circuit 240 cause the first output signal S1 and the second output signal S2 to be the test acceleration clock. A signal TEST is output. From time t5, 63 test acceleration clock signals TEST are output. At time t6, the second frequency-divided signal V2 is in a 63/64 state, and the drive signal V3 is in a 63/64 state.

Next, during the period from the time point t7 to the time point t8, the data input / output signal DIO to the second control signal C2
= Low is transmitted and written to the system control register 500. Since the second control signal C2 transitions to Low at time t8, the second output signal S2 is transferred by the second input signal switching circuit 240.
The second frequency-divided signal V2 is output at.

One test acceleration clock signal TEST is output from time t9. At time t10, the second frequency-divided signal V2 becomes (63 + 1) / 64, and one clock is output from the second frequency-divided signal V2.
As a result, the drive signal V3 becomes (63 + 1) / 64, the drive signal V3 becomes Low,
The carry reference signal V4 is also Low.

At time t9, the carry signal UP becomes High. Further, when two test acceleration clock signals TEST are output from time t10, the carry reference signal V4 changes to High at time t11, and the carry signal UP also changes to Low. When the carry signal UP changes to Low, the value of the clock counter 310 is carried.

During the period from time t12 to time t13, the current value of the clock counter 310 is read and transmitted from the data input / output signal DIO to the external device.

According to the above method, it is only necessary to output 63 + 1 + 2 = 66 test acceleration clock signals TEST to carry one carry of the clock counter 310, and the efficiency of the acceleration test can be increased.

  According to the embodiment described above, the following effects can be obtained.

In the present embodiment, the frequency of the reference signal V0 generated from the oscillation circuit 100 is 32768 Hz.
The frequency dividing ratio of the first frequency dividing circuit 210 is 1/8, the frequency dividing ratio of the second frequency dividing circuit 230 is 1/64,
By setting the frequency dividing ratio of the third frequency dividing circuit 250 to 1/64, the frequency of the first frequency-divided signal V1 is 4096 (= square of 64) Hz, and the frequency of the second frequency-divided signal V2 is 64 ( = 64 to the power of 1) H
z, the frequency of the drive signal V3 is 1 (= 64 to the 0th power) Hz, and the frequency of the first divided signal V1, the frequency of the second divided signal V2, and the frequency of the drive signal V3 are natural powers of n = 64. Are in a relationship. According to such a configuration, it is possible to carry the value of the clock counter 310 by only 66 outputs from the test acceleration clock signal TEST, and it is possible to increase the efficiency of the acceleration test.

As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, In the range which does not deviate from the meaning of this invention, it can be implemented with various forms. Hereinafter, a modification will be described.

(Modification 1) A first modification of the semiconductor device according to the present invention will be described. In the first embodiment, the case where the frequency of the first frequency-divided signal V1, the frequency of the second frequency-divided signal V2, and the frequency of the drive signal V3 are in a relation of powers of natural numbers n = 64 has been described. Such a configuration may be used. That is, the frequency of the reference signal V0 generated from the oscillation circuit 100 is 32768 Hz, the frequency dividing ratio of the first frequency dividing circuit 210 is 1/32, the frequency dividing ratio of the second frequency dividing circuit 230 is 1/32, and the third frequency dividing frequency. By setting the frequency dividing ratio of the frequency dividing circuit 250 to 1/32, the frequency of the first frequency-divided signal V1 is 1024 (= the square of 32) Hz, and the frequency of the second frequency-divided signal V2 is 32 (= 32). 1st power) Hz
The frequency of the drive signal V3 is 1 (= 32 to the 0th power) Hz, and the frequency of the first divided signal V1, the frequency of the second divided signal V2, and the frequency of the drive signal V3 are powers of a natural number n = 32. Become a relationship. Further, it is assumed that the test acceleration clock signal TEST is input from an external device at a frequency of 1024 Hz. The carry reference signal V4 always outputs 1024 Hz. With such a configuration, it is only necessary to output 31 + 1 + 1 = 33 test acceleration clock signals TEST, and the efficiency of accelerated inspection can be further increased.

1 is a block diagram illustrating a configuration of a semiconductor device according to an embodiment of the present invention. The timing chart explaining the output of the carry signal when not using the acceleration clock signal for a test. The timing chart explaining the output of a carry signal when the first divided signal and the second divided signal are not in a power relationship. The timing chart explaining the output of a carry signal when the first frequency-divided signal and the second frequency-divided signal are in a power relationship.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 100 ... Oscillator circuit, 200 ... Drive circuit, 210 ... 1st frequency divider circuit, 22
0 ... first input signal switching circuit, 230 ... second frequency dividing circuit, 240 ... second input signal switching circuit, 2
50: Third frequency dividing circuit, 300: Carry generating circuit, 310: Clock counter, 400 ... 3
Linear serial interface control circuit, 500 ... system control register, 600 ... bus, V0 ... reference signal, V1 ... first frequency division signal, V2 ... second frequency division signal, V3 ... drive signal, V4 ...
Carry reference signal, S1 ... first output signal, S2 ... second output signal, UP ... carry signal, C1 ...
First control signal, C2 ... second control signal, R ... reset signal, TEST ... test acceleration clock signal, DIO ... data input / output signal, CLK ... clock signal, CE ... chip enable signal.

Claims (4)

In a semiconductor device that includes an oscillation circuit that generates a reference signal and a drive circuit that divides the reference signal to generate a drive signal, and controls a timekeeping function by the drive signal,
The drive circuit is
A test acceleration clock signal for accelerating and outputting the drive signal;
A first frequency divider that inputs the reference signal and outputs a first frequency-divided signal;
A first input signal switching circuit controlled by a first control signal for selecting whether to output the first frequency-divided signal or to output the test acceleration clock signal;
A second frequency dividing circuit for inputting an output signal of the first input signal switching circuit and outputting a second frequency divided signal;
A second input signal switching circuit controlled by a second control signal for selecting whether to output the second frequency-divided signal or to output the test acceleration clock signal;
A third frequency dividing circuit for inputting the output signal of the second input signal switching circuit and outputting the drive signal;
A semiconductor device. 2. The semiconductor device according to claim 1, wherein each of a frequency dividing ratio of the first frequency dividing circuit, a frequency dividing ratio of the second frequency dividing circuit, and a frequency dividing ratio of the third frequency dividing circuit are: The frequency of the first frequency-divided signal, the frequency of the second frequency-divided signal, and the frequency of the drive signal are each set to be a power of a predetermined natural number n. A semiconductor device. 3. The semiconductor device according to claim 1, wherein the frequency of the first frequency-divided signal is the square of the predetermined natural number n, the frequency of the second frequency-divided signal is the power of the predetermined natural number n, The frequency of the drive signal is the predetermined natural number n to the 0th power, and the semiconductor device is characterized in that: The electronic device provided with the semiconductor device as described in any one of Claim 1 to 3.

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